AND8373/D

2 Switch-Forward Current
Mode Converter
Prepared by: Thierry Sutto
ON Semiconductor
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APPLICATION NOTE

Introduction This application note describes the design of 120−W,

A major advantage of the two−switch forward converter 125 kHz, two−switch forward current mode converter with
is that the power switches only block the supply voltage the NCP1252 controller. It can viewed the practical
instead of twice the supply voltage as in the flyback or implementation of the 2−switch forward converter example
single−switch forward converter. described in Ref. [1].
Here after, the complete specification, of the two The NCP1252 controller offers everything to build
switch−forward converter is described: cost−effective and reliable ac−dc switching power supplies
implementing the forward converter: NCP1252 detects an
Table 1. Specification output overload without relying on the auxiliary Vcc, a
Description Value Units Brown−Out input offers protection against low input
Input voltage Range 350−410 Vdc voltages and improves the converter safety. Finally a SOIC8
package saves PCB space and represents a solution of choice
Output Voltage 12 Vdc
in cost sensitive projects.
Output Power 96 W The power supply described here operates from a dc input
Output Peak Power during 5 sec 120 W voltage, as the forward converter is usually connected after
per 1 min a Power Factor Correction (PFC) stage. It generates a 12−V
Minimum Output Load Current(s) 0 Adc output at 10 A. The efficiency at full load is close to 90% at
Number of Outputs 1
the nominal output of the PFC.

Nominal Output Voltage 12 Vdc Power Supply Components Calculation

±5%
Transformer
Maximum Output Current 8 Adc
The following equation extracted from the buck converter
Maximum Output Peak Current 10 Adc running in Continuous Current Mode (CCM), turns ratio
Output ripple 50 mV will determine the turns ratio of the transformer:
Maximum startup time <1 s V out + h @ V bulk min @ DC max @ N (eq. 1)
Standby Power < 100 mW Where:
Target Efficiency at full load 90 % • Vout is the output voltage
@ Vin = 390 V dc
• h is the targeted efficiency
Load Conditions for Efficiency 20, 50 %
Measurements (10%, 20%,..) & 100 • Vbulkmin is the minimum operating input voltage of the
forward
Min Load Efficiency (Pout = 1.2 W) > 50 %
• DCmax is the maximum duty cycle that the NCP1252
Maximum Transient load step of 50 % can deliver
the maximum output current
• N is the turns ratio of the transformer
Maximum Output drop voltage from 250 mV
Iout = 5 to 10 A in 5 ms
Extracting the turns ratio from the previous equation, we
obtain:
V out (eq. 2)
N+ + 12 + 0.085
hV bulk minDC max 0.9 350 0.45

© Semiconductor Components Industries, LLC, 2010 1 Publication Order Number:

March, 2010 − Rev. 1 AND8373/D
 AND8373/D

Using this value in Equation 1, we can estimate the Given a DIout of 5 A, the above room temperature ESR
minimum duty cycle at high line by changing the bulk components would, generate an output voltage undershoot/
voltage parameter: overshoot of:
(eq. 3)
V out 12 DV out + DI outR ESR,max + 5 28.5 m + 142 mV (eq. 7)
DC min + + + 38.2%
hV bulk maxN 0.9 410 0.085
which is acceptable given a specification of 250 mV.
To ensure enough primary magnetizing current to There is a rule of thumb to select an ESR capacitor equal
properly reset the core (drive the stray capacitance and allow to the half of the calculated value with Equation 6. This rule
the voltage across the winding to reverse), one must usually will take into account the process variation of the capacitor
reduce the primary inductance from the core’s ungapped plus some margin for a startup operation of the power supply
value to one that will cause an adequate magnetizing current. at very low ambient temperature.
A popular rule of thumb as to make the magnetizing current The final check will include the circulating rms current.
around 10% of the primary current. Since the primary However, given the nonpulsating nature of the buck output,
current is 0.94 A peak (the calculation of this peak current we do not expect this current to be that high.
is given on the following paragraph), we will let the Considering the output power level and the selected
magnetizing current rise to 0.1 A. The desired primary capacitor, we can consider the total ripple voltage
inductance, then, with a primary voltage of 350 Vdc and a contributed by the ESR term alone. Thus, if we adopt an ESR
pulse duration of 3.6 ms of 22 mW (approximate value at 0°C), the maximum peak to

ǒDCF sw
max
125 k
Ǔ
+ 0.45 , is
peak output ripple current must be lower than:
V ripple 50 m
DI L v v v 2.27 A (eq. 8)
V bulkmin R ESR,max 22 m
L mag + + 350 + 13.4 mH (eq. 4)
10%I p_pk 0.1 0.94 To obtain the output inductor value, we can write the buck
0.45
DC max 125 k ripple expression based on the off−time duration:
Fsw
V out
Based on this assumption the transformer manufacturer DI L + (1 * DC min)T sw (eq. 9)
L
offered the following transformer core: E30/15/7. Using Equation 8, we can derive a minimum inductor
value for L:
LC Output Filter:
(eq. 10)
The crossover frequency fc will arbitrarily be selected at V
L + out (1 * DC min)T sw w 12 (1 * 0.38) 1 w 26 mH
10 kHz. Beyond this value, the converter would pick−up DI L 2.27 125 k
switching noise and would require a more carefull layout. If we consider a 10% drop in the inductor value at high
Below, the stringent dropout specification would lead to the temperature and current, let us adopt a 29 mH output
selection of a larger output capacitor. Considering a voltage inductor. But as this value is not standard part we will stick
drop mostly dictated by fc, the output capacitance and the to a 27−mH normalized value.
step load current, we can derive a first capacitor value by With the selected inductor value, we can calculate the rms
using a formula already encountered: current in the output capacitor:
DI out 5 (eq. 11)
C out w w w 318 mF (eq. 5) 1 * DC min 1 * 0.38 + 1.06 A
2pf cDV out 2p 10 k 0.25 IC ,rms + I out + 10
out Ǹ12t L Ǹ12 2.813
The above case assumes an ESR much lower than the
capacitor impedance at the crossover frequency: Where:
1 1 L out 27 m
R ESR v v v 50 mW (eq. 6) tL + + + 2.813 (eq. 12)
2pf cC out 2p 10 k 318 m Vout 12 1
@ 1 10 125 k
We must also select a capacitor whose worst case ESR Iout Fsw
remains below the capacitor impedance at the crossover Given the equivalent capacitor current capability
frequency, in order to limits its contribution to the transient (5.36 A), there is no problem here.
output drop. We are going to parallel two 1000 mF FM The secondary side peak current will be:
capacitors from Panasonic. DI L
C = 2000 mF, FM series @ 16 V I s_pk + I out ) + 10 ) 2.27 + 11.13 A (eq. 13)
2 2
IC,rms = 5.36 A (2*2.38 A) @ TA = +105°C On the primary side, this current reflects to:
RESR,low = 8.5 mW (19 mW/2) @ TA = +20°C I p_pk + I s_pkN ratio + 11.13 0.085 + 0.946 A (eq. 14)
RESR,high = 28.5 mW (57 mW/2) @ TA = −10°C And the valley reaches

ǒ
I p_valley + I out *
DI L
2
Ǔ ǒ
N ratio + 10 * 2.27
2
Ǔ 0.085 + 0.75 A (eq. 15)

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 AND8373/D

Based on the following Equation 16, we are able to

calculate the rms current of a pulsating waveform with linear I rms + I ǸDC Ǹ1 ) 13 ǒDI2IǓ (eq. 16)

current (see Figure 1):

I(t)

DIL

t
0 DCT T

Figure 1. Pulsating Waveform with Linear Ripple Current

This waveform exactly despits the current we have with calculate the primary rms current, the magnetizing current
a forward converter on the primary or secondary side of the should be added to the Ip_pk calculated with Equation 14.
tranformer. The magnetizing inductance has been previously calculated
When this current is measured on the primary side, DI (Equation 4) with 10% of the primary peak current.
represents the reflected secondary−side ripple summed with Therefore the primary rms current can be written has
the magnetizing current. Thus if we would like to accurately followed:

I p,rms,10% + Ǹ ǒ
DC max (1.1 @ I p_pk) 2 * 1.1 @ I p_pkDI LN )
(DI LN) 2
3
Ǔ
(eq. 17)

I p,rms,10% + Ǹ0.45 (1.1 ǒ 0.946) 2 * 1.1 0.946 2.27 0.085 )

(2.27
3
0.085) 2
Ǔ
+ 0.63 A

Where: If the PFC does not include skip cycle in light−load

• DCmax is the maximum duty cycle that the NCP1252 operation, chances are that its output voltage will reach the
can deliver overvoltage protection (OVP) level. The converter thus
• Ip_pk is the peak current calculated by Equation 14. enters a kind of autorecovery hiccup mode. It is therefore
important to check that one respects Equation 18 despite the
• ΔIL is the maximum output peak to peak current ripple
OVP detection.
• N is the turns ratio of the transformer The FDP16N50 has been selected for this application. Its
Mosfet Selection
specification are as follows:
The mosfets are selected based on the maximum input • Package TO220
voltage and a derating factor kM of 0.85. If we choose 500 V • BVDSS = 500 V
devices (in a two−switch forward converter, the transistor • RDS(on) = 0.434 W at Tj = 110°C (RDS(on) = 0.31 W @
stress is limited to the input voltage), the maximum Tj = 25°C multiplied by 1.4: RDS(on) derating factor for
high−voltage rail must be limited to 110°C)
V bulk,max + BV DSSk M + 500 0.85 + 425 V (eq. 18) • QG = 45 nC
• QGD = 14 nC
Thanks to Equation 17, we can estimate its conduction
losses as
P cond + I p,rms,10% 2 R DS(on) @ T J + 110 oC + 0.632 2 0.434 + 173 mW (eq. 19)
As we are running a 2−switch forward application, the illustrate the 2−switch forward arrangement and the
voltage presents on each power switch at the turn−on is equal simulated voltage present on both power switches.
to the half of the bulk voltage: the two following figures

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 AND8373/D

Bulk

DRV_hi M1 VM1(t)

D3 Lout
Vout
D1

D2
D4 C1

DRV_lo M2 VM2(t)

Figure 2. 2−switch Forward Arrangement

400V Turn
ON VDS of the
power mosfets
300V

200V

100V Turn
OFF

0V
V(VBULK,Q5:c)
750mA
Power mosfets
current
500mA

250mA

0A
SEL>>
860.0us 870.0us 878.1us
−I(RSENSE2) Time
Figure 3. Power Mosfet Curves: VDS(t) and ID(t) of the Both Power Mosfets

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 AND8373/D

At the turn−on the power losses can be expressed as follow:

Dt
VDS(t) V bulk
2
ID(t)
Ip_valley

PSW,on Losses

Figure 4. Turn−on Losses (PSW,on)

The average power losses at the switch on is a triangle Where the overlap (Δt) is estimated via the following
area, the exact calculation can be done via the following equation:
integral calculation: Q GD 14 n
Dt Dt + + + 46.7 ns (eq. 22)
I DRV_pk 0.300
P SW,on + F sw ŕ I (t)VD DS(t)dt This overlap estimation does not take into account that the
0 driver of the NCP1252 is a CMOS type, in that case the
Vbulk (eq. 20) output driver will not deliver a constant current.
I p_valley Dt
+ 2
F sw Nevertheless the estimation is not so wrong. This overlap is
6 true for a bipolar driver stage that it delivers a constant
I p_valleyV bulkDt current.
P SW,on + F sw
12 As we have 2 power mosfets with our application the total
Based on the previous equation we are able to estimate the switch−on losses will the double of the losses from
losses at each power mosfet switch on: Equation 21: 358 mW.
I p_valleyV bulk,maxDt Experimental measurement:
P SW,on + F sw (eq. 21)
12
0.75 410 46.7 n
P SW,on + 125 k + 149 mW
12

ID(t)
500 mA/div

VDS(t)
100 V/div

P(t) = ID(t) VDS(t)

30 W/div

Time
20 ns/div

Figure 5. Switching Losses During the Turn On of the LOW Side Mosfet

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 AND8373/D

ID(t)
500 mA/div

VDS(t)
100 V/div

P(t) = ID(t) VDS(t)

30 W/div

Time
20 ns/div

Figure 6. Switching losses during the turn on of the HIGH side mosfet

Figures 5 and 6 represent the power losses of the power losses have not been well estimated. This is probably due to
mosfets (high and low side mosfet). From these figures we the wrong estimation of the driver current capability
can note that the drain to source voltage on the low and high (IDRV_pk): we took the hypothesis that the driver is able to
side mosfet is not at the half of bulk voltage as expected from deliver a constant current as we have with a bipolar output
the theory and the simulation result. stage (UC384X like). But as the NCP1252’s output driver
Drain to source power mosfet voltage is not equal to the half stage is based on the CMOS technology, the current is
of the bulk voltage due to the parasitic element from the varying with the voltage on the power mosfet gate, thus it is
transformer and the power mosfet. The low side power mosfet really difficult to estimate accurately the overlap.
voltage is equal to 150 V and 240 V for the high side one. As the losses of the power MOSFET in a 2−switch
Thus the measured switch−on losses are the following: forward are very low, the error introduce in these estimations
• High side switch on losses: 386 mW does not impact to much the heat sink calculation.
• Low side switch on losses: 155 mW The losses at the turn off can be calculated using the
If we compare these experimental results with the theory similar method: but now the peak current is at its max value.
from Equation 21 where the switch on losses has been The drain−to−source voltage of the power switch is close to
estimated to 179 mW per switch, we can conclude that the zero and switches to Vbulk.

Dt
VDS(t)
Ip_pk
Vbulk

PSW,off Losses

ID(t)
t

Figure 7. Turn−off Losses (PSW,off)

Based on the equation used for the switch on losses, we are able to estimate the losses at each power mosfet:
I p_pkV bulk,maxDt 0.95 410 40 n
P SW,off + F sw + 125 k + 324 mW (eq. 23)
6 6
The overlap (Δt) is estimated via the following equation:
Q GD 14 n
Dt + + + 40 ns (eq. 24)
I DRV_pk 0.350

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 AND8373/D

We are now able to estimate the overall losses on each Where:

power mosfet: • Switch−on losses: PSW,on = 149 mW
P losses + P SW,on ) P cond ) P SW,off • Conduction losses: Pcond = 173 mW
+ 0.149 ) 0.173 ) 0.324 (eq. 25) • Switch−off losses: PSW,off = 324 mW
P losses + 646 mW Once we have the total dissipation budget per MOSFET,
a heatsink can be calculated.

Rqj−c Rqc−hs Rqhs−a

Tj Tc Ths Ta

Plosses

Figure 8. Thermal path between the power mosfet and the heat sink

Where: As the magnetizing and demagnetizing voltage are similar

• Tj is the junction temperature of the power mosfet (Vbulk, thanks to the 2−switch forward structure); both on
• Tc is the case temperature of the power mosfet and reset times are equal.
• Ths is the heat sink temperature L mag 13.4 m
t reset + I mag,pk + 94 m + 3.6 ms (eq. 29)
• Ta is the ambient temperature V bulkmin 350

• Rθj−c is the thermal resistance between the junction and The average current can now be derived in a snapshot:
the case of the power mosfet (t on ) t reset)I mag_pk
I mag_avg +
• Rθc−hs is the thermal resistance between the case of the 2
Fsw
power mosfet and the heat sink
• Rθhs−a is the thermal resistance between the heat sink
and the ambient temperature.
ǒ DCmax
Fsw
Ǔ
) t reset I mag_pk
+
The following condition has to be checked to prevent any 2
Fsw (eq. 30)
over heating of the power mosfet during worst case
operation: ǒ 0.45
125 k
) 3.6 m Ǔ 94 m
T jmax * T ambmax u P losses ȍ Rq (eq. 26) +
2
125 k
Or it can be written as follow:
I mag_avg + 42.3 mA
T jmax * T ambmax
R qhsa t * ǒR qjc ) R qchsǓ Diode such as the MUR160 accommodates the
P losses demagnetization task easily. Usually, in off−line application
as the magnetizing current remains low any 1 A high voltage
t 110 * 65 * (1 ) 1.2) (eq. 27)
0.646 diode (500 or 600 V) can do the job.
Let us now take care of the secondary diodes. In the
R qhsa t 67.4 oCńW
forward converter, both secondary−side diodes sustain a
Thus the thermal resistance of the heat sink should be similar peak inverse voltage (PIV). Given a turns ratio of
lower than 67.4°C/W. A KL194/25.4/SW from Seifert 0.085 and the diode’s derating factor kD, the diodes have to
(ref.[2]) has been selected (14°C/W). sustain the following PIV:
Diodes Selection NV bulkmax
PIV + + 0.085 410 + 58 V (eq. 31)
The choice of the primary freewheeling diodes depends kD 0.60
on the transformer magnetizing inductor. The magnetizing Thanks to the low PIV value, we are able to select the
peak current can be calculated via the following equation: following Schottky diode reference: MBRB30H60CT.
V bulk,min DC max (eq. 28) This diode (30 A, 60 V in a TO−220) case features a
I mag_pk + + 350 45% + 94 mA
maximum drop of 0.5 V at 125°C (see Figure 9)
L mag F sw 13.4 m 125 k

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 AND8373/D

100
IF, INSTANTANEOUS FORWARD CURRENT (A)
On average these diodes would dissipate around 5.3 W or
4.4% of the total output power. In order to improve the
efficiency it can be interesting to implement a synchronous
rectification to replace them.
TJ = 125°C
10 For these diodes, we can re−use Equation 27 to calculate
the required heat sink.
T Jmax * T AMBmax
* ǒR qj−c ) R qc−hsǓ
TJ = 25°C
R qhs−a t
P losses
1
Vf = 0.5 V @ 10 A t 125 * 65 * (2 ) 1.2) (eq. 34)
& TJ = 125°C 5.33
R qhs−a t 8.06 oCńW

0.1 Thus the thermal resistance of the heat sink should be

0 0.2 0.4 0.6 0.8 1.0 1.2 lower than 8°C/W.
VF, INSTANTANEOUS FORWARD VOLTAGE (V) For the demonstration board, the following heat sink has
been selected KL195/25.4/SW from Seifert (ref.[2]). It
Figure 9. MBRB30H60CT, Maximum Forward
provides a low thermal resistance of 6.2°C/W.
Voltage versus Instaneous Current

The series diode would then dissipate the following power NCP1252 Component Selection
in worst case conditions (Low line and maximum duty Switching Frequency Selection
cycle). A resistor connected between the Rt pin and the ground
(eq. 32)
precisely sets the switching frequency between 50 kHz and
P d_on + V fI outDC max + 0.5 10 0.45 + 2.25 W
a maximum of 500 kHz. The following curve helps to select
The freewheeling diode would dissipate slightly more as the resistor according the selected switching frequency.
it conducts during the off time:
P d_off + V fI out(1 * DC min) (eq. 33)
+ 0.5 10 (1 * 0.39) + 3.05 W
Switching frequency versus Rt resistor
500
Switching frequency, Fsw (kHz)

450
400
350
300
250
200
150
100
50
0
0 20 40 60 80 100
Rt resistor (kOhm)

Figure 10. Switching Frequency Selection

The following equation could also be used to calculate the If we select a 33 kW resistor, this will yield:
resistor value according to the switching frequency 1.95 10 9V R (eq. 36)
selection: F sw + t
+ 1.95 10 9 2.2 + 130 kHz
Rt 33 k
1.95 10 9V R
t
Rt + (eq. 35) The measurement on the final board with a resistor equal
F sw
to 33 kW gives us 130 kHz for the switching frequency.
Where: This oscillator resistor will be laid out as close as possible
• VRt is the internal voltage reference present on the Rt to the Rt pin (pin #4) of the NCP1252 and its ground (pin #5).
pin and equal to 2.2 V. As these pins are really close together, it will be not so
If we assume a switching frequency of 125 kHz, difficult to take into account this requirement. The
robustness of the controller against electrical noise will be
R t + 1.95 10 9 2.2 + 34.3 kW
125 k improved.

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 AND8373/D

Sense Resistor measurement and it will improve the robustness of the

The NCP1252 featuring a maximum peak current to 1 V, power supply. Nevertheless this time constant should not be
the sense resistor is computed via the following expression, too large compared to the switching period of the controller.
where a 20% margin appears on the primary peak current It is usually recommended to select a 150−300−ns time
(10% for the magnetizing current and 10% for general constant for the current sense filter network.
margin): The NCP1252 provides an internal ramp compensation
F CS 1 appearing on the CS pin. The resistor of the RC filter will
R sense + + + 884 mW (eq. 37)
1.2I p_pk 1.2 0.946 play a double function: ramp compensation and time
The power dissipation of the sense resistor with a 20% constant for filtering. Thus the ramp compensation will fix
margin on the primary peak current amounts to: the resistor value of the RC filter and then the capacitor will
(eq. 38) be adjusted to respect the time constant previously defined.
PR + I p,rms,20% 2R sense + 0.695 2 0.884 + 427 mW One of the following chapters describes how to calculate
sense
the ramp compensation resistor.
Where:
• Ip,rms,20% is the rms current of the primary peak current Brown−out
with 20% margin on the peak current By monitoring the level on BO pin, the NCP1252 protects
As we are using 1206 resistor type sizes with a limited the forward converter against low input voltage conditions.
power dissipation of 250 mW, we have to place 2 resistors When the BO pin level falls below the VBO level, the
in parallel in order to fit the authorized power capability. controllers stops pulsing until the input level goes back to
Thus we select 2 resistors of 1.5 W. The new power normal and resumes the operation via a new soft start
dissipation will be 362 mW for both resistors and 180 mW sequence.
for each one. The brown−out comparator features a fixed voltage
Despite the presence of a Leading Edge Blanking (LEB = reference level (VBO). The hysteresis is implemented by
130 ns), it is recommended to insert between the sense using the internal current connected between the BO pin and
resistor and the CS pin of the controller a small RC filter in the ground when the BO pin is below the internal voltage
order to remove any parasitic noise from the application. reference (VBO).
This small RC network will “clean” the current sense

S
Q
Vbulk Q

RB O u p R
BO
−
BOK
shutdown Grand
+
RB Olo
Re se t
VBO
UVLO reset

IBO

Figure 11. BO Pin Setup

The following equations show how to calculate the When BO pin voltage is below VBO (internal voltage
resistors for BO pin. reference), the internal current source (IBO) is activated. The
First of all, select the bulk voltage value at which the following equation can be written:
controller must start switching (Vbulkon) and the bulk
voltage for shutdown (Vbulkoff) the controller. ǒ
V bulkON + R BOup I BO )
V BO
R BOlo
Ǔ) V BO (eq. 39)
Where:
When BO pin voltage is higher than VBO, the internal
• Vbulkon = 370 V
current source is now disabled. The following equation can
• Vbulkoff = 350 V be written:
• VBO = 1 V (fixed internal voltage reference) V bulkoffR BOlo
• IBO = 10 mA (fixed internal current source) V BO +
R BOlo ) R BOup
(eq. 40)

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 AND8373/D

From Equation 40 RBOup can be extracted: We selected the following values for the brown out

R BOup + ǒ V bulkoff * V BO
V BO
ǓR BOlo (eq. 41)
resistor divider:
• RBOlo = 5.1 KW + 680 W
• RBOup = 1 MW + 1 MW
Equation 41 is substituted in Equation 39 and solved for
RBOlo, yields: Soft Start

R BOlo + ǒ
V BO V bulkon * V BO
I BO V bulkoff * V BO
*1 Ǔ (eq. 42)
The soft start of the NCP1252 controls the peak current of
the forward converter during the startup sequence: this
prevent any over stress on the power components (primary
RBOup can be also written independently of RBOlo by mosfet, secondary diode and magnetic component like
substituting Equation 42 into Equation 41 as follow: transformer and inductor) during this critical phase and it
V bulkon * V bulkoff reduces the output overshoot.
R BOup + (eq. 43)
The soft start pin provides a current source connected to
I BO
an internal voltage reference. Thus a capacitor connected to
From Equation 42 and Equation 43, the resistor divider
this current source generates a linear voltage slope that
value can be calculated:
controlling the peak current of the power supply via the
ǒ
R BOlo + 1 370 * 1 * 1 + 5731 W
10 m 350 * 1
Ǔ current sense resistor. The SS pin voltage is divided by 4 to
scale down the SS pin voltage to a compatible CS pin
R BOup + 370 * 350 + 2.0 MW voltage.
10 m

Clock

CS S
Rcomp Q DRV
LEB
Q
Rsense
Soft Start
Status R

Vdd
Fixe d
Iss De lay UVLO
120 ms +
−
SS

Soft start
Grand Reset

Figure 12. Soft Start Principle

Based on the following well known equation: T SS 15 m

C SS + I SS + 10 m + 37.5 nF (eq. 45)
V SS V SS 4.0
I SS + C SS (eq. 44)
T SS If we select Css = 33 nF, the soft start duration measured
By extracting from the previous equation the capacitor (see Figure 13) on the demoboard is equal to 13 ms.
value we are able to calculate the soft start duration: if we
select Tss = 15 ms,

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 AND8373/D

Soft Start pin

T ss = 13 ms (2 V/div)

V ss = 4 V

CS pin
(0.5 V/div)

Time
(4 ms/div)

Figure 13. Soft Start Duration Illustration

Figure 13 illustrates that the max voltage on the soft start half of the switching frequency and occur only during
pin is equal to 6.6 V, but the peak current of the forward Continuous Conduction Mode (CCM) with a duty−cycle
transformer linearly ramps from zero to 4.0 V. Above 4.0 V close or above 50%. To lower the current loop gain, one
on the SS pin, the controller will clamp to the max peak usually injects between 50 and 100% of the inductor
current. downslope. Figure 14 depicts how internally the ramp is
At the beginning of the soft start the peak current variation generated:
is not linear due to the Discontinuous Mode Current (DCM) The ramp compensation applied on CS pin is buffered
operation of the forward at low peak current and low voltage from the internal oscillator ramp. A switch placed between
on the output. the buffered internal oscillator ramp and Rramp disconnects
the ramp compensation during the off−time DRV signal.
Ramp Compensation Selection
Ramp compensation is a known means to cure
subharmonic oscillations. These oscillations take place at
Vdd

FB 2R Clock

R S
Q DRV
path
Q

R
Buffered
Ramp

Rramp
−
Rcomp CS
LEB +
Rsense

Figure 14. Ramp Compensation Setup

In the NCP1252, the internal ramp swings with a slope of: In a forward application the secondary−side downslope
V ramp viewed on a primary side requires a projection over the sense
S int + F (eq. 46) resistor Rsense. Thus:
DC max sw
(V out ) V f) N S
S sense + R (eq. 47)
L out N P sense

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 AND8373/D

where: transformer magnetizing inductance. In some case illustrate

• Vout is output voltage level here after the power supply does not need additional ramp
• Vf the freewheel diode forward drop compensation due to the high level of the natural primary
ramp.
• Lout, the secondary inductor value
The natural primary ramp is extracted from the following
• Ns/Np the transformer turn ratio formula:
• Rsense: the sense resistor on the primary side V bulk
Assuming the selected amount of ramp compensation to S natural + R (eq. 50)
L mag sense
be applied is δcomp, then we must calculate the division ratio
to scale down Sint accordingly: Then the natural ramp compensation will be:
S sensed comp S natural
Ratio + (eq. 48) d natural_comp + (eq. 51)
S int S sense
If the natural ramp compensation (δnatural_comp) is higher
A few line of algebra determined Rcomp:
than the ramp compensation needed (δcomp), the power
R comp + R ramp Ratio (eq. 49) supply does not need additional ramp compensation. If not,
1 * Ratio
only the difference (δcomp−δnatural_comp) should be used to
The previous ramp compensation calculation does not
calculate the accurate compensation value.
take into account the natural primary ramp created by the
Thus the new division ratio is:
S sense(d comp * d natural_comp)
if d natural_comp t d comp å Ratio + (eq. 52)
S int
Then Rcomp can be calculated with the same equation used • Vbulk = 350 V, minimum input voltage at which the
when the natural ramp is neglected. power supply works.
If we assume that our forward is based on the following • Duty cycle max : DCmax = 50%
information:
• Vramp = 3.5 V, Internal ramp level.
2 switch−Forward Power supply specification:
• Regulated output: 12 V • Rramp = 26.5 kW, Internal pull−up resistance
• Lout = 27 mH • Targeted ramp compensation level: 100%
• Vf = 0.5 V (drop voltage on the regulated output) • Transformer specification:
− Lmag = 13 mH
• Current sense resistor : 0.75 W − Ns/Np = 0.087
• Switching frequency : 125 kHz Internal ramp compensation level
V ramp
S int + F å S int + 3.5 125 kHz + 875 mVńms (eq. 53)
DC max sw 0.50
Secondary−side downslope projected over the sense resistor is:
(V out ) V f) N S (12 ) 0.5)
S sense + R å S sense 0.087 0.75 + 30.21 mVńms (eq. 54)
L out N P sense 27 @ 10 −6
Natural primary ramp:
V bulk
S natural + R å S natural + 350 −3 0.75 + 20.19 mVńms (eq. 55)
L mag sense 13 @ 10
Thus the natural ramp compensation is:
S natural
d natural_comp + å d natural_comp + 20.19 + 66.8% (eq. 56)
S sense 30.21
Here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be
added to prevent sub−harmonics oscillation.
S sense(d comp * d natural_comp) 30.21(1.00 * 0.67)
Ratio + å Ratio + + 0.0114 (eq. 57)
S int 875
We can know calculate external resistor (Rcomp) to reach the correct compensation level.
R comp + R ramp Ratio å R 3 0.0114 + 305 W
comp + 26.5 @ 10 (eq. 58)
1 * Ratio 1 * 0.0114
Thus with Rcomp = 330 W, 100% compensation ramp is applied on the CS pin.

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 AND8373/D

As the ramp compensation resistor is now calculated, we If we select a 680−pF normalized value for CCS we are
are able to calculate the capacitor value of the RC network really close to the targeted time constant of 220 ns.
connected to the CS pin. The following figure illustrates the behavior of the RC
If we assume the time constant of the RC network is equal filtering network.
to 220 ns, the capacitor value will be:
t RC 220 n
C CS + + + 666 pF (eq. 59)
R Comp 330

V Rsense
(0.5 V/div)

CS pin
(0.5 V/div)

Time
(2 ms/div)
Figure 15. Comparison of the Voltage on the Current Sense
Resistor and After the RC Filter

After filtering the current information of the forward wire: if the original ground wire is used, the current
converter provided to the controller is free of noise. measurement will be worse than in reality. The following
Note: The measurements done in Figure 15 have to be figure shows a comparison of the wrong and correct current
done by respecting a true clean ground probe connection. measurements over the sense resistor.
Usually the scope probe is delivered with a long ground

Current
measurement
on Sense
:resistor with

standard probe
(0.5 V/div)

Short gnd
connection
(0.5 V/div)

Time
(4 ms/div)

Figure 16. Current Sense Measurement on Sense

Resistor with Standard and Short Ground Connection

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 AND8373/D

Both following figures illustrate the different probe

connection for measuring the current sense information.
Figure 17 illustrates the standard probe connection: but as GND
the probe’s ground wire is quite long, the measurement connection
generates noise (see Figure 16 probe measurement
comparison).

Rsense Current
Rsense sense
information

Figure 18. Current Sense Measurement on Sense

Resistor with Short Ground Connection of the Probe

Figure 17. Current Sense Measurement on Sense Secondary diode snubber calculation:
Resistor with Standard Probe Connection Without snubbing elements (R2&C2, R4&C6) in parallel
with the secondary diodes (D5): some oscillations appear
Figure 18 illustrates the correct connection for measuring across the secondary diode. These oscillations are the result
on a power supply the current sense information. This of the leakage inductance of the secondary side of the
connection has been done just by removing the plastic tips transformer with the capacitor behavior of the diode when
protection of the standard probe and by soldering two short it blocks. Thus in the worst case condition (max input
wires directly to the sense resistor pads. voltage) it is possible that the maximum reverse voltage of
the diode has been reached; with all the consequence.

Figure 19. Secondary Diode Snubbing

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 AND8373/D

As depicted by the following figure without snubbing element the oscillations at the nominal input voltage reach the
maximum reverse voltage of the diode (60 V).

62 V with max
VRRM = 60 V for
the MBRB30H60!!! Voltage
accross the
forward diode
of D5
(10 V/div)

Time
(2 ms/div)

Figure 20. Voltage Applied to the Forward Diode of D5

The principle of the snubber placed in parallel of each will be adjusted to damp completely all the oscillations
diode is damp the oscillations. The oscillations take place at implying a quality coefficient (Q) of 1:
the end of the conduction of the diode and they are the R damp + L leakw r + 118 n 2p 22 M + 16 W (eq. 60)
consequences of the leakage inductance of the secondary
winding and the parasitic diode behavior of the diode. After selecting a 22−W resistor for both secondary diodes,
Knowing the leakage inductance of the secondary the oscillation voltage is now limited to 36 V compared to
winding of the transformer and the oscillation frequency we 62 V without snubber at similar input voltage (373 Vdc). A
are able to determine the resistor to be placed in parallel of 2.2−nF capacitor is placed in series with the resistor in order
the diode to damp the oscillations. In that case the resistor to limit the losses due to the resistor presence.

Voltage
36 V with snubber
on each diode accross the
freewheeling
diode of D5
(10 V/div)

Voltage
accross the
forward diode
of D5
(10 V/div)

Time
(2 ms/div)

Figure 21. Voltage Applied to the Secondary Diodes (D5) with Snubber

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 AND8373/D

Board Performances
The following figures illustrate the general performances of this demoboard.
Startup Delay
As depicted by Figure 22, when the VCC voltage is rising from zero and crossing VCC(ON) level, the NCP1252 sends the first
pulses on the DRV pin only when the 120−ms startup delay is elapsed.

Vcc pin
(5 V/div)
Delay: 120 ms

SS pin
(5 V/div)

DRV pin
(10 V/div)

Time
(40 ms/div)

Figure 22. Startup Delay

Soft Start compare to the middle and the end of the soft start: this non
Figure 23 depicts a soft start sequence. The CS pin voltage linearity is related due to the DCM (Discontinuous Current
is following the shape of the SS pin voltage. At the beginning Mode) mode of operation of the forward during the first 2 or
of the soft start period, the peak current variation is not linear 3 ms of the soft start when the output voltage is low (< 1 V).

SS pin
(2 V/div)

CS pin
(500 mV/div)

12 Vout
(5 V/div)

Time
(4 ms/div)

Figure 23. Soft Start at Full Load (10 A)

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 AND8373/D

Jittering Frequency
The Jittering frequency featured by the NCP1252 helps to switching frequency selected by the resistor connected to Rt
spread out the switching noise and eases the filtering of the pin with a frequency modulation of 330 Hz. The jittering
power supply. The following figure illustrates the digital modulation can be also observed by measuring the Rt pin
jittering frequency of the NCP1252: ±5% of the centered voltage.

Center:131 kHz Max: 137 kHz

Switching
frequency
(5 kHz/div)
Min: 125 kHz

DRV pin
(10 V/div)

Time
(400 ms/div)

Figure 24. Jittering Frequency Measurement

No Load Regulation demonstration board does not have any dummy load and
Thanks to the skip cycle feature implemented on the ensure a correct no load regulation. This regulation is
NCP1252, it is possible to achieve a real no load regulation achieved by skipping some driving cycles and by forcing the
without triggering any over voltage protection. The NCP1252 in burst mode of operation.

FB pin
(200 mV/div)

DRV pin
(10 V/div)

Time
(400 ms/div)

Figure 25. No Load Regulation (Real No Load to

the Output) Vout = 12.096 V

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 AND8373/D

Step Load Stability figures show the fast transient response without any
In order to test the close loop stability, a maximum step oscillations and exhibit a low drop voltage 165 mV (1.3% of
load of 5 A have been applied on the output. The following the nominal output).

FB pin
(2 V/div)

165 mV
Ac coupling on
12−V output
(0.1 V/div)

Time
(1 ms/div)
Figure 26. Step Load Response from 5 A to 10 A

FB pin
(2 V/div)

165 mV
Ac coupling on
12−V output
(0.1 V/div)

Time
(1 ms/div)
Figure 27. Step Load Response from 0.5 A to 5.5 A

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 AND8373/D

Efficiency
The efficiency measurements have been done at room temp at different load conditions and at the nominal load with different
input voltage.

Efficiency versus Output load at ambient temperature

95%

90%

85%

80%
Efficiency (%)

75%

70%

65%

60%

55%
50%
0.0 2.0 4.0 6.0 8.0 10.0
Iout (A)
Figure 28. Efficiency Measurement at Room Temperature and Nominal
Input Voltage (390 V dc) versus Output Load Variation

Efficiency versus Input voltage at ambient temperature

91.0%

90.5%

90.0%
Efficiency (%)

89.5%

89.0%

88.5%

88.0%
360 370 380 390 400 410
Vin (V dc)
Figure 29. Efficiency Measurement at Room Temperature and
Nominal Output Load (10 A dc) versus Intput Voltage

One possible way to improve the efficiency of the demoboard is to implement a synchronous rectification, it will improve
by some percent the overall efficiency.

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 D1N4937 SLB4−I/ 90
Vbulk J1
HS1 Mosfet HS2 Mosfet C1 47uF D1
DRV_H TP 1 450V SLB4−I/ 90
1 1 J2

1
1 1 M1 C2
DRV_HI R2 22R 2. 2nF
0
Demoboard Schematics

D3 R3 2W 100V 2306−H−RC 1 TP 2
2 2

FDP16N50
1SMA5931 47k V12V
2 2 D4 MU R 160 1 L1 2
12V SLB4−I/ 90
KL194 0 KL194 0 J3
T1 10 D5 R4 27uH
MB RB30H60 22R TP 1 6
HS3 Diode 1 C4 C5

1
DRV_HI_ref D6 out put _power
Main Board with its Auxiliary Supply

2W 1000uF / F M 1000uF / F M
1 MUR160 C6 2. 2nF TP 1 5
1 16V 16V out put _power
TP 3 5 6 100V
D R V_H _ref 0 SLB4−I/ 90
XFM R1 R6 J4
2 TP 4 2. 2nF
DRV_L V12V
2 10R

1
KL195 M2 C7
DRV_LO 0 R8 R9a
180R 15k

F D P16N 50
J5 D8 FB J6
2 1SMA5931 R10
1 47k R11 2 1
1k R9b
U2 3k

20
GN D R12 C9 GN D
0 0 CS R13 SF H 615A_4 10nF
Vbulk 1R 5
1R 5 U3
TL 4 3 1
AND8373/D

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R14 TP 5 TP 6 0
1M 1% FB SS R15
4. 7k

1
1
R16
1M 1% 33nF C10
FB U4 0

Figure 30. Main Demoboard Schematic

BO NCP1252 0
R17 0 C11 VC C C12
1 NC VC C Daughter board connectors

1
200k 1% TP 7
1nF 2 FB SS 8 35V C13 J204
Vc c 0 Vc c DRV_HI
C14 1 3 BO 7 100nF J202
TP 8 CS DRV Vc c DRV_HI_ref 1
6 D9 1 2
1nF
4 RT DRV

1
6200 1% R19 CS2 GN D 5 BZ X84C 18/ Z TX 2 DRV DRV_LO 3
3 CS 4
CS GN D GN D 5

1
R21 1k R20 0 TP 9 0
C15 DRV 0 0

1
220pF 39k
R18 H EAD ER 3 H EAD ER 5
100 1% TP 10
CS1 0 0 TP 1 1
Rt

0
 AND8373/D

As depicted by Figure 30, the NCP1252 feedback is • Self Vcc supply: in that case the NCP1010 regulator
implemented via a TL431 arranged in a Type 2 corrector. (see Figure 31) is used to build the 15 V output via a
The power supply can be connected directly to a dc source, buck converter for stepping down the main bulk voltage
where the minimum startup voltage is 370 Vdc. There are 2 to the Vcc level. This auxiliary self supply is
options for supplying the Vcc to the NCP1252: implemented on the main board close to the bulk
• External Vcc supply: in that case the dedicated voltage.
connector for the Vcc can be used to supply the 15 Vdc
to the demoboard. The NCP1010 controller for the
auxiliairy supply must be removed from the board.

U104
1 GN D 8
2 VC C GN D 7
3 NC
4 GND DRAIN 5 Vbulk
FB
NCP1010P60
+
C102
47uF / 25V
C101 R101 D101
1n 1k BZ X84C 12

R102
0 1k
L101
1 2 Vc c
2. 2m H
+ C103
D102 47uF / 25V
MUR1 6 0

0
Figure 31. Auxiliary Supply Based on the NCP1010 @ 65 kHz

Daughter Board: Driver Stage We selected to drive also the low side power mosfet with the
The daughter board or the drivers for the high side and low pulse transformer to prevent any difference on the way to
side mosfet is done with a pulse transformer from PREMO. drive the low and high side mosfet.

D 301
MMBT489LT1G MMSD 4148
R301 D 302
Q301 XFM R 2 47R MMS D4 1 4 8
R 302 6 4
47
C 302 R 304 1k
1 Vc c 3 Q303
2 DRV 220nF
Q302 C 301 MMBT589LT1G
3 GN D DRV_HI 1
MMBT589LT1G 10n 5
DRV_HI_ref 2
J 202
H EAD ER 3 D R V_LO 3
1 2 DRV_LO_ref 4
R 305 D 303
U 301 5
2 1 47R MMS D4 1 4 8
J 301 0 J 302
H EAD ER 5
GN D R 306
Q304
1k

MMBT589LT1G
Figure 32. Daughter Board: Driver Stage

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 AND8373/D

Demo Board Picture

DCin+

DCin GND

Daughter
Board Drivers

Out GND 12 V Out

Figure 33. Top View of the Demo Board

NCP1252 with its

Surrounding Components

Figure 34. Bottom View of the Demo Board

References
1. C. Basso, “Switch Mode Power Supplies: SPICE Simulations and Practical Designs”, McGraw−Hill, 2008.
2. Heatsink manufacturer link: http://www.seifert−electronic.de/en/produkt.php?id=50 or direct link to the datasheet
http://www.digtion−medien.de/seifert/Uploads/seifert_punkte/pdfs/50%5B0%5D.pdf

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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22