A B C D E

1 1

Compal Confidential
2 2

QCL70 MB Schematic Document

LA-8222P
3 3

Rev: 1.0
2012.01.09

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 1 of 61
A B C D E
 1 2 3 4 5

Compal Confidential
ZZZ1
QCL70
PCB-MB
PCB P/N for Load BOM DDR3 1333/1600MHz 1.5V DDR3-SO-DIMM X 2
BANK 0, 1, 2, 3
A DAZ0NE00100 Mobile +1.5V, +0.75VS A

Dual Channel Page 10, 11

NV N13P-GL / GS PEG 16X Ivy Bridge

(N13M-GE1) Processor
rPGA 988B Socket
Page 4 ~ 9
Page 20 ~ 29 +VCC_CORE, +VCCP,
+VCC_GFXCORE_AVG, +1.5V_CPU_VDDQ, port 5,1
+1.8VS, _VCCSA
USB conn x2
USB Board Page 33
FDI x8
DMI x4
(UMA) 100MHz port 3
100MHz Camera
5GB/s
2.7GT/s Page 30

LCD conn LVDS, EDID, DISPOFF#, PWM USB2.0

Page 30
port 4 Card Reader Memory Card Slot
SD/MMC
RTS5137 Page 34
RGB, HV Sync, DDC Page 34
CRT Conn
B
Page 30 Intel port 10
B

MiniCard-2
HDMI, DDC
PANTHER-POINT Page 41

HDMI PCH
Page 35
port 0,2
USB3.0 conn x2
USB3.0 port 1,3
Page 37
HM76/HM75
Audio Jack (HP)
Page 33

Azalia Realtek
FCBGA 989 Balls ALC269 Page 33 Audio Jack (MIC)
Page 33

Page 12 ~ 19 SATA
2.5" SATA HDD Connector Speaker Connector
port 0 Page 33
C Page 31 C

PCI-e
port 1
+1.05VS, +1.8VS, +3VS, 2.5" SATA HDD Connector
port 1 port 2 +3V_PCH, +5V_PCH, +RTCVCC,
+VCCAFDI_VRM Page 31
LAN/CRT Board Mini Card-1
10/100/1000 LAN WLAN port 2
Realtek GbE Bluetooth SATA ODD Connector
RTL8111F Page 32 Page 41 Page 31

SPI SPI ROM

4MB For win7
8MB For win8
Page 12
LPC BUS

Touch Pad CONN. ENE KB9012QF

D
Page 39 Reserve KB930QF
+3VLP/+3VALW Int. KBD
D

page 40
Page 39
DC/DC Interface CKT.
Page 29,42

SPI ROM
Security Classification Compal Secret Data Compal Electronics, Inc.
Fan Control Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

Page 38 Page 40 SCHEMATIC A8222

128KB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 2 of 61
1 2 3 4 5
 A

X76@:

VRAMX16X8 HYN 128*16*8 CLKOUT DESTINATION USB3 PORT DESTINATION USB2 PORT DESTINATION
ZZZ X76L01@ ZZZ2 X76L02@ ZZZ3 X76L15@

PCI0 PCH_LOOPBACK 1 USB2.0+3.0 0 USB2.0+3.0

2G SAM 2G B HYN 2G D HYN PCI1 EC PCH 2 USB2.0+3.0 1 USB2.0+3.0

ZZZ5 X76L05@ ZZZ6 X76L06@
PCI2 None 3 None 2 USB2

PCI3 LPC Debug Port 4 None 3 CAMERA

1G SAM 1G HYN

PCI4 None 4 Card Reader

VRAMX16X8-GS N13P-GS N13P-GL
ZZZ11 X76L12@ ZZZ12 X76L11@ 5 USB2
GS@ GL@ Voltage Rails
U10 GS@ U10 GL@ 6 None
Power Plane Description S1 S3 Deep S5
GS 2G SAM GS 2G HYN S3
VIN Adapter power supply (19V) N/A N/A N/A N/A PCH 7 None
N13P-GS N13P-GL BATT+ Battery power supply (12.6V) N/A N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A N/A 8 None
+3VLP 3.3V power rail for 51ON power management ON ON ON ON
GEL@: N13M-GE1 or N13P-GL N13M-GE1 N13M-GE1 x8
GS@: N13P-GS +3VALW 3.3V always on power rail ON ON ON AC/ON; DC/OFF 9 None
GE@ GE8@
+LAN_IO 3.3V power rail for ethernet ON ON OFF OFF
DIS@: VGA componet U10 GE@ U10 GE8@
+3VS_WLAN 3.3V power rail for WLAN/BT Combo ON OFF OFF OFF 10 JMINI1 (WLAN) Bluetooth
9012@: EC(ENE 9012 chip)
+3V_PCH 3.3V power rail for PCH suspend well plane ON ON OFF OFF
XDP@: Intel debug port
+3VS 3.3V power rail for DDR SPI,PCH,HDD,Audio,Card Reader ON OFF OFF OFF 11 None
930@: EC(ENE 930 chip) N13M-GE1 N13M-GE1 x8
+3VSG 3.3V power rail for VGA ON OFF OFF OFF
IU3@: USB3.0 by PCH PS8520 ASM1466 +LCDVDD 3.3V power rail for LCD ON OFF OFF OFF 12 None
USB30@: USB3.0 controller IC ZZZ9 PAR8520@ ZZZ10 ASM1466@
+5VALW 5V always on power rail ON ON ON AC/ON; DC/OFF
+5V_PCH 5V power rail for PCH suspend well plane ON ON OFF OFF 13 None
AI@: AI Charger
+5VS 5V power rail for HDD,AUDIO,FAN,Touch PAD ON OFF OFF OFF
NAI@: Non AI Charger
+5VS_ODD 5V power rail for SATA ODD ON OFF OFF OFF
PS8520 ASM1466
+1.8VS 1.8V power rail for CPU,PCH ON OFF OFF OFF
W7@: WIN7 PCI EXPRESS DESTINATION
+1.05VS 1.05V power rail for PCH ON OFF OFF OFF
W8@: WIN8
+VCCP 1.05V power rail for CPU VCCIO,PCH ON OFF OFF OFF
1 Lane 1 10/100/1G LAN 1

+1.05VSG 1.05V power rail for N13P ON OFF OFF OFF

+1.5V 1.5V power rail for DDR3 system memory ON ON ON OFF
Lane 2 MINI CARD WLAN
+1.5V_CPU_VDDQ 1.5V power rail CPU VDDQ ON OFF OFF OFF
SMBUS Control Table +1.5VSG 1.5V power rail for N13P,VRAM ON OFF OFF OFF
Lane 3 None
+1.5VS 1.5V power rail for PCH,WLAN/BT combo ON OFF OFF OFF
SOURCE MINI1 BATT PCH EC SODIMM DGPU +0.75VS 0.75V power rail for DDR VREF ON OFF OFF OFF
Lane 4 None
+VCCSA VCCSA for CPU system agent ON OFF OFF OFF
EC_SMB_CK1
EC_SMB_DA1
KB930 X V X X X X +VCC_CORE
+VCC_GFXCORE_AXG
CORE Voltage for CPU
1.5V power rail for N13P,VRAM
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
Lane 5 None
EC_SMB_CK2
EC_SMB_DA2
KB930 X X V X X V +VGA_CORE CORE Voltage for N13P Graphics ON OFF OFF ON OFF OFF OFF
Lane 6 None
PCH_SMBCLK
PCH_SMBDATA PCH V X X X V X Lane 7 None
SATA DESTINATION
PCH_SMLCLK
SATA0 HDD Lane 8 None
PCH_SMLDATA PCH
X X X V X V
SATA1 HDD
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION
SATA2 ODD
CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 CLK_SD_48M
SATA3 None
CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None
SATA4 None
CLKOUT_PCIE2 None CLKOUTFLEX2 None SATA5 None
CLK CLKOUT_PCIE3 None CLKOUTFLEX3 None QCL70 * 16 (LA8222P)
Board ID Table for AD channel
CLKOUT_PCIE4 None Vcc 3.3V +/- 5%
Ra / Rc 100K +/- 5%
CLKOUT_PCIE5 None Symbol Note : Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
33K +/- 5% 0.634 V 0.819V 0.945 V
CLKOUT_PCIE6 None : means Digital Ground

CLKOUT_PCIE7 None Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
: means Analog Ground SCHEMATIC A8222
CLKOUT_PEG_B None THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 3 of 61
A
 5 4 3 2 1

+VCCP

1
JCPU1I
R1 PEG_ICOMPI and RCOMPO signals should be shorted and routed
24.9_0402_1% with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms T35 F22

2
JCPU1A VSS161 VSS234
T34 VSS162 VSS235 F19
D PEG_COMP D
PEG_ICOMPI J22 T33 VSS163 VSS236 E30
PEG_ICOMPO J21 T32 VSS164 VSS237 E27
14 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22 T31 VSS165 VSS238 E24
14 DMI_CRX_PTX_N1 B25 DMI_RX#[1] T30 VSS166 VSS239 E21
14 DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] 20 T29 VSS167 VSS240 E18
14 DMI_CRX_PTX_N3 B24 K33 PCIE_GTX_CRX_N15 DIS@ C1 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N15 T28 E15
DMI_RX#[3] PEG_RX#[0] PCIE_GTX_CRX_N14 DIS@ C2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N14 VSS168 VSS241
PEG_RX#[1] M35 1 2 T27 VSS169 VSS242 E13
14 DMI_CRX_PTX_P0 B28 L34 PCIE_GTX_CRX_N13 DIS@ C3 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N13 T26 E10
DMI_RX[0] PEG_RX#[2] PCIE_GTX_CRX_N12 DIS@ C4 0.22U_0402_10V6K PCIE_GTX_C_CRX_N12 VSS170 VSS243
14 DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 1 2 P9 VSS171 VSS244 E9
14 DMI_CRX_PTX_P2 A24 J32 PCIE_GTX_CRX_N11 DIS@ C5 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N11 P8 E8

DMI
DMI_RX[2] PEG_RX#[4] PCIE_GTX_CRX_N10 DIS@ C6 0.22U_0402_10V6K PCIE_GTX_C_CRX_N10 VSS172 VSS245
14 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34 1 2 P6 VSS173 VSS246 E7
H31 PCIE_GTX_CRX_N9 DIS@ C7 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N9 P5 E6
PEG_RX#[6] PCIE_GTX_CRX_N8 DIS@ C8 0.22U_0402_10V6K PCIE_GTX_C_CRX_N8 VSS174 VSS247
14 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 1 2 P3 VSS175 VSS248 E5
E22 G30 PCIE_GTX_CRX_N7 DIS@ C9 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N7 P2 E4
14 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] VSS176 VSS249
F21 F35 PCIE_GTX_CRX_N6 DIS@ C10 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N6 N35 E3
14 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS177 VSS250
D21 E34 PCIE_GTX_CRX_N5 DIS@ C11 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N5 N34 E2
14 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] VSS178 VSS251
E32 PCIE_GTX_CRX_N4 DIS@ C12 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N4 N33 E1
PEG_RX#[11] PCIE_GTX_CRX_N3 DIS@ C13 0.22U_0402_10V6K PCIE_GTX_C_CRX_N3 VSS179 VSS252
14 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2 N32 VSS180 VSS253 D35
D22 D31 PCIE_GTX_CRX_N2 DIS@ C14 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N2 N31 D32
14 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS181 VSS254
F20 B33 PCIE_GTX_CRX_N1 DIS@ C15 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N1 N30 D29

PCI EXPRESS* - GRAPHICS

14 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] VSS182 VSS255
C21 C32 PCIE_GTX_CRX_N0 DIS@ C16 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N0 N29 D26
14 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS183 VSS256
PCIE_GTX_C_CRX_P[0..15] 20 N28 VSS184 VSS257 D20
J33 PCIE_GTX_CRX_P15 DIS@ C17 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P15 N27 D17
PEG_RX[0] PCIE_GTX_CRX_P14 DIS@ C18 0.22U_0402_10V6K PCIE_GTX_C_CRX_P14 VSS185 VSS258
PEG_RX[1] L35 1 2 N26 VSS186 VSS259 C34
K34 PCIE_GTX_CRX_P13 DIS@ C19 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P13 M34 C31
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_CRX_P12 DIS@ C20 0.22U_0402_10V6K PCIE_GTX_C_CRX_P12 VSS187 VSS260
14 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35 1 2 L33 VSS188 VSS261 C28
FDI_CTX_PRX_N1 H19 H32 PCIE_GTX_CRX_P11 DIS@ C21 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P11 L30 C27
14 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] VSS189 VSS262
FDI_CTX_PRX_N2 E19 G34 PCIE_GTX_CRX_P10 DIS@ C22 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P10 L27 C25
14 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS190 VSS263
FDI_CTX_PRX_N3 F18 G31 PCIE_GTX_CRX_P9 DIS@ C23 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P9 L9 C23
14 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS191 VSS264
14 FDI_CTX_PRX_N4
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
B21
C20
FDI1_TX#[0] Intel(R) FDI PEG_RX[7] F33
F30
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_P7
DIS@
DIS@
C24
C25
1
1
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P7
L8
L6
VSS192 VSS265 C10
C1
14 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] VSS193 VSS266
FDI_CTX_PRX_N6 D18 E35 PCIE_GTX_CRX_P6 DIS@ C26 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P6 L5 B22
C 14 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] VSS194 VSS267 C
FDI_CTX_PRX_N7 E17 E33 PCIE_GTX_CRX_P5 DIS@ C27 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P5 L4 B19
14 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_P3
DIS@
DIS@
C28
C29
1
1
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P3
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_CRX_P2 DIS@ C30 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P2 L1 B13
14 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS198 VSS271
FDI_CTX_PRX_P1 G19 C33 PCIE_GTX_CRX_P1 DIS@ C31 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P1 K35 B11
14 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] VSS199 VSS272
FDI_CTX_PRX_P2 E20 B32 PCIE_GTX_CRX_P0 DIS@ C32 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P0 K32 B9
14 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
FDI_CTX_PRX_P3 G18 K29 B8
14 FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] 20 VSS201 VSS274
FDI_CTX_PRX_P4 B20 M29 PCIE_CTX_GRX_N15 DIS@ C33 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15 K26 B7
14 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] VSS202 VSS275
FDI_CTX_PRX_P5 C19 M32 PCIE_CTX_GRX_N14 DIS@ C34 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N14 J34 B5
14 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] VSS203 VSS276
FDI_CTX_PRX_P6 D19 M31 PCIE_CTX_GRX_N13 DIS@ C35 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N13 J31 B3
14 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] VSS204 VSS277
FDI_CTX_PRX_P7 F17 L32 PCIE_CTX_GRX_N12 DIS@ C36 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N12 H33 B2
14 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] VSS205 VSS278
L29 PCIE_CTX_GRX_N11 DIS@ C37 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N11 H30 A35
+VCCP FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N10 DIS@ C38 0.22U_0402_10V6K PCIE_CTX_C_GRX_N10 VSS206 VSS279
14 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2 H27 VSS207 VSS280 A32
14 FDI_FSYNC1 FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_N9 DIS@ C39 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N9 H24 A29
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N8 DIS@ C40 0.22U_0402_10V6K PCIE_CTX_C_GRX_N8 VSS208 VSS281
PEG_TX#[7] J30 1 2 H21 VSS209 VSS282 A26
14 FDI_INT FDI_INT H20 J28 PCIE_CTX_GRX_N7 DIS@ C41 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7 H18 A23
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N6 DIS@ C42 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6 VSS210 VSS283
PEG_TX#[9] H29 1 2 H15 VSS211 VSS284 A20
1

14 FDI_LSYNC0 FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N5 DIS@ C43 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5 H13 A3
R2 FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N4 DIS@ C44 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4 VSS212 VSS285
14 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2 H10 VSS213
F27 PCIE_CTX_GRX_N3 DIS@ C45 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3 H9
24.9_0402_1% PEG_TX#[12] PCIE_CTX_GRX_N2 DIS@ C46 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2 VSS214
PEG_TX#[13] D28 1 2 H8 VSS215
F26 PCIE_CTX_GRX_N1 DIS@ C47 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1 H7
2

PEG_TX#[14] PCIE_CTX_GRX_N0 DIS@ C48 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0 VSS216

PEG_TX#[15] E25 1 2 H6 VSS217
EDP_COMP A18 H5
eDP_COMPIO PCIE_CTX_C_GRX_P[0..15] 20 VSS218
A17 M28 PCIE_CTX_GRX_P15 DIS@ C49 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15 H4
eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_P14 DIS@ C50 0.22U_0402_10V6K PCIE_CTX_C_GRX_P14 VSS219
B16 eDP_HPD# PEG_TX[1] M33 1 2 H3 VSS220
M30 PCIE_CTX_GRX_P13 DIS@ C51 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P13 H2
PEG_TX[2] PCIE_CTX_GRX_P12 DIS@ C52 0.22U_0402_10V6K PCIE_CTX_C_GRX_P12 VSS221
eDP_COMPIO L31 1 2 H1
PEG_TX[3] PCIE_CTX_GRX_P11 DIS@ C53 0.22U_0402_10V6K PCIE_CTX_C_GRX_P11 VSS222
and ICOMPO C15 eDP_AUX PEG_TX[4] L28 1 2 G35 VSS223
signals D15 K30 PCIE_CTX_GRX_P10 DIS@ C54 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P10 G32
eDP_AUX# PEG_TX[5] PCIE_CTX_GRX_P9 DIS@ C55 0.22U_0402_10V6K PCIE_CTX_C_GRX_P9 VSS224
K27 1 2 G29
eDP

should be PEG_TX[6] PCIE_CTX_GRX_P8 DIS@ C56 0.22U_0402_10V6K PCIE_CTX_C_GRX_P8 VSS225

PEG_TX[7] J29 1 2 G26 VSS226
B shorted C17 J27 PCIE_CTX_GRX_P7 DIS@ C57 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7 G23 B
near balls eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_P6 DIS@ C58 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6 VSS227
F16 eDP_TX[1] PEG_TX[9] H28 1 2 G20 VSS228
and routed C16 G28 PCIE_CTX_GRX_P5 DIS@ C59 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5 G17
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_P4 DIS@ C60 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4 VSS229
with G15 eDP_TX[3] PEG_TX[11] E28 1 2 G11 VSS230
typical F28 PCIE_CTX_GRX_P3 DIS@ C61 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3 F34
PEG_TX[12] PCIE_CTX_GRX_P2 DIS@ C62 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2 VSS231
impedance C18 eDP_TX#[0] PEG_TX[13] D27 1 2 F31 VSS232
E16 E26 PCIE_CTX_GRX_P1 DIS@ C63 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P1 F29
<25 mohms eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P0 DIS@ C64 0.22U_0402_10V6K PCIE_CTX_C_GRX_P0 VSS233
D16 eDP_TX#[2] PEG_TX[15] D25 1 2
F15 eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE
CONN@

TYCO_2013620-2_IVY BRIDGE

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 4 of 61
5 4 3 2 1
 5 4 3 2 1

+3V_PCH +3VALW

JCPU1B

2
PR-7
R577 R576
A28 CLK_CPU_DMI_R R18 1 2 0_0402_5% 0_0402_5% 0_0402_5%
BCLK CLK_CPU_DMI 13 +3VS
C26 A27 CLK_CPU_DMI#_R R19 1 2 0_0402_5%

MISC

CLOCKS
16 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 13 @

0.1U_0402_16V4Z~D
1
1
+1.5V_CPU_VDDQ
AN34 SKTOCC# 1

C65
D CLK_CPU_DPLL_R R21 1K_0402_1% D
DPLL_REF_CLK A16 1 2

1
A15 CLK_CPU_DPLL#_R R22 1 2 1K_0402_1% +VCCP R3
DPLL_REF_CLK# 10K_0402_5% R4
2
200_0402_1%
PAD T1 @ H_CATERR# AL33

2
CATERR#

5
U1

2
R9 1 2 S_PWG 1

P
14 SYSTEM_PWROK @ 0_0402_5% A VDDPWRGOOD
4

THERMAL
H_PECI H_DRAMRST# D_PWG O
40 H_PECI AN33 PECI SM_DRAMRST# R8 H_DRAMRST# 6 14 PM_DRAM_PWRGD 1 2 2 B

G
R11 0_0402_5%
74AHC1G09GW TSSOP 5P

DDR3
MISC

3
R23 1 2 PR-7
+3V_PCH
40,43 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 PROCHOT# SM_RCOMP[0] AK1 SM_RCOMP0 200_0402_1% R14
56_0402_5% A5 SM_RCOMP1
SM_RCOMP[1] SM_RCOMP2
SM_RCOMP[2] A4

H_THERMTRIP# AN32
16 H_THERMTRIP# THERMTRIP# +3VS +VCCP

0.1U_0402_16V4Z

1
AP29 XDP_PRDY# 1
PRDY# XDP_PREQ# R15
PREQ# AP27

C69
75_0402_5%
AR26 XDP_TCK
TCK XDP_TMS 2
AR27

PWR MANAGEMENT

2
TMS

JTAG & BPM

H_PM_SYNC AM34 AP30 XDP_TRST#
14 H_PM_SYNC PM_SYNC TRST#

1
AR28 XDP_TDI_R U2 R17

P
TDI

NC
PR-2 AP26 XDP_TDO_R 2 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
TDO 15,32,36,40,41 PLT_RST# A Y
16 H_CPUPWRGD H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33 43_0402_1%
UNCOREPWRGOOD

G
R12 33_0402_5%
C SN74LVC1G07DCKR_SC70-5 C

1
R36 AL35 XDP_DBRESET#_R1 1 2 @
DBR# XDP_DBRESET#_R 12,14
VDDPWRGOOD 1 2 VDDPWRGOOD_R V8 R37 0_0402_5% R20
130_0402_1% SM_DRAMPWROK
0_0402_5%
AT28 XDP_BPM#0 PR-7
BPM#[0] XDP_BPM#1
AR29

2
BPM#[1] XDP_BPM#2
BPM#[2] AR30
BUF_CPU_RST# AR33 AT30 XDP_BPM#3
RESET# BPM#[3] XDP_BPM#4
BPM#[4] AP32
AR31 XDP_BPM#5
BPM#[5] XDP_BPM#6
BPM#[6] AT31
AR32 XDP_BPM#7
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
CONN@
PR-17

1 2 VDDPWRGOOD_R @ 1 2 H_DRAMRST# PU/PD for JTAG signals

C72 12P_0402_50V8J C70 100P_0402_50V8J
+VCCP

Reserve for EMI please close to JCPU1 Reserve for EMI please close to JCPU1
XDP_TMS 51_0402_5% 1 2 R26

XDP_TDI_R 51_0402_5% 1 2 R27

B PR-2 1 2 H_CPUPWRGD_R +3VS B
C640 100P_0402_50V8J
XDP_DBRESET#_R1 1K_0402_5% 1 2 R24 XDP_TDO_R 51_0402_5% 1 2 R29

Reserve for EMI please close to JCPU1

H_CPUPWRGD_R 10K_0402_5%1 2 R25 XDP_TCK 51_0402_5% 1 2 R32

XDP_TRST# 51_0402_5% 1 2 R33

@ 1 2 H_PECI
C68 100P_0402_50V8J

@ 1 2 XDP_DBRESET#_R1
C71 100P_0402_50V8J
Reserve for EMI please close to JCPU1
DDR3 Compensation Signals
Reserve for EMI please close to JCPU1
PR-17
1 2 BUF_CPU_RST# SM_RCOMP0 140_0402_1%1 2 R34
C647 100P_0402_50V8J
SM_RCOMP1 25.5_0402_1%1 2 R38

SM_RCOMP2 200_0402_1%1 2 R39

Reserve for EMI please close to JCPU1

A +VCCP A
Processor Pullups

H_PROCHOT# 62_0402_5%
1 2 R16

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 5 of 61
5 4 3 2 1
 5 4 3 2 1

JCPU1C

JCPU1D

10 DDR_A_D[0..63] SA_CLK[0] AB6 DDRA_CLK0 10

SA_CLK#[0] AA6 DDRA_CLK0# 10
DDR_A_D0 C5 V9 AE2
SA_DQ[0] SA_CKE[0] DDRA_CKE0 10 11 DDR_B_D[0..63] SB_CLK[0] DDRB_CLK0 11
DDR_A_D1 D5 AD2
SA_DQ[1] SB_CLK#[0] DDRB_CLK0# 11
DDR_A_D2 D3 DDR_B_D0 C9 R9
SA_DQ[2] SB_DQ[0] SB_CKE[0] DDRB_CKE0 11
DDR_A_D3 D2 DDR_B_D1 A7
DDR_A_D4 SA_DQ[3] DDR_B_D2 SB_DQ[1]
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 10 D10 SB_DQ[2]
D DDR_A_D5 DDR_B_D3 D
C6 SA_DQ[5] SA_CLK#[1] AB5 DDRA_CLK1# 10 C8 SB_DQ[3]
DDR_A_D6 C2 V10 DDR_B_D4 A9 AE1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 10 SB_DQ[4] SB_CLK[1] DDRB_CLK1 11
DDR_A_D7 C3 DDR_B_D5 A8 AD1
SA_DQ[7] SB_DQ[5] SB_CLK#[1] DDRB_CLK1# 11
DDR_A_D8 F10 DDR_B_D6 D9 R10
SA_DQ[8] SB_DQ[6] SB_CKE[1] DDRB_CKE1 11
DDR_A_D9 F8 DDR_B_D7 D8
DDR_A_D10 SA_DQ[9] DDR_B_D8 SB_DQ[7]
G10 SA_DQ[10] RSVD_TP[1] AB4 G4 SB_DQ[8]
DDR_A_D11 G9 AA4 DDR_B_D9 F4
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D10 SB_DQ[9]
F9 SA_DQ[12] RSVD_TP[3] W9 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D13 F7 DDR_B_D11 G1 AA2
DDR_A_D14 SA_DQ[13] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G8 SA_DQ[14] G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D15 G7 DDR_B_D13 F5
DDR_A_D16 SA_DQ[15] DDR_B_D14 SB_DQ[13]
K4 SA_DQ[16] RSVD_TP[4] AB3 F2 SB_DQ[14]
DDR_A_D17 K5 AA3 DDR_B_D15 G2
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D16 SB_DQ[15]
K1 SA_DQ[18] RSVD_TP[6] W10 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D19 J1 DDR_B_D17 J8 AB1
DDR_A_D20 SA_DQ[19] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
J5 SA_DQ[20] K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D21 J4 DDR_B_D19 K9
DDR_A_D22 SA_DQ[21] DDR_B_D20 SB_DQ[19]
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# 10 J9 SB_DQ[20]
DDR_A_D23 K2 AL3 DDR_B_D21 J10
SA_DQ[23] SA_CS#[1] DDRA_SCS1# 10 SB_DQ[21]
DDR_A_D24 M8 AG1 DDR_B_D22 K8 AD3
SA_DQ[24] RSVD_TP[7] SB_DQ[22] SB_CS#[0] DDRB_SCS0# 11
DDR_A_D25 N10 AH1 DDR_B_D23 K7 AE3
SA_DQ[25] RSVD_TP[8] SB_DQ[23] SB_CS#[1] DDRB_SCS1# 11
DDR_A_D26 N8 DDR_B_D24 M5 AD6
DDR_A_D27 SA_DQ[26] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N7 SA_DQ[27] N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D28 M10 DDR_B_D26 N2
DDR_A_D29 SA_DQ[28] DDR_B_D27 SB_DQ[26]
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 10 N1 SB_DQ[27]
DDR_A_D30 N9 AG3 DDR_B_D28 M4
SA_DQ[30] SA_ODT[1] DDRA_ODT1 10 SB_DQ[28]
DDR_A_D31
DDR_A_D32
M7
AG6
SA_DQ[31] DDR SYSTEM MEMORY A RSVD_TP[9] AG2
AH2
DDR_B_D29
DDR_B_D30
N5
M2
SB_DQ[29] SB_ODT[0] AE4
AD4
DDRB_ODT0 11

DDR SYSTEM MEMORY B

SA_DQ[32] RSVD_TP[10] SB_DQ[30] SB_ODT[1] DDRB_ODT1 11
DDR_A_D33 AG5 DDR_B_D31 M1 AD5
DDR_A_D34 SA_DQ[33] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AK6 SA_DQ[34] AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D35 AK5 DDR_B_D33 AM6
DDR_A_D36 SA_DQ[35] DDR_B_D34 SB_DQ[33]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 10 AR3 SB_DQ[34]
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D35 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AP3 SB_DQ[35]
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D36 AN3
SA_DQ[38] SA_DQS#[1] SB_DQ[36] DDR_B_DQS#[0..7] 11
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN1 SB_DQ[38] SB_DQS#[1] F3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D39 AP2 K6 DDR_B_DQS#2
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AP5 SB_DQ[40] SB_DQS#[3] N3
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AH8 SA_DQ[44] SA_DQS#[7] AM15 AT5 SB_DQ[42] SB_DQS#[5] AP9
DDR_A_D45 AH9 DDR_B_D43 AT6 AK12 DDR_B_DQS#6
DDR_A_D46 SA_DQ[45] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AL9 SA_DQ[46] AP6 SB_DQ[44] SB_DQS#[7] AP15
DDR_A_D47 AL8 DDR_B_D45 AN8
DDR_A_D48 SA_DQ[47] DDR_B_D46 SB_DQ[45]
AP11 SA_DQ[48] DDR_A_DQS[0..7] 10 AR6 SB_DQ[46]
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D47 AR5
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D48 SB_DQ[47]
AL12 SA_DQ[50] SA_DQS[1] F6 AR9 SB_DQ[48] DDR_B_DQS[0..7] 11
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AM11 SA_DQ[52] SA_DQS[3] N6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AP12 SA_DQ[54] SA_DQS[5] AM9 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AJ14 SA_DQ[56] SA_DQS[7] AM14 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D57 AH14 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D58 SA_DQ[57] DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AL15 SA_DQ[58] AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D59 AK15 DDR_B_D57 AN14
DDR_A_D60 SA_DQ[59] DDR_B_D58 SB_DQ[57]
AL14 SA_DQ[60] DDR_A_MA[0..15] 10 AR14 SB_DQ[58]
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D59 AT14
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AJ15 SA_DQ[62] SA_MA[1] W1 AT12 SB_DQ[60] DDR_B_MA[0..15] 11
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D61 AN15 AA8 DDR_B_MA0
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
SA_MA[3] W7 AR15 SB_DQ[62] SB_MA[1] T7
V3 DDR_A_MA4 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[5] V2 SB_MA[3] T6
W3 DDR_A_MA6 T2 DDR_B_MA4
SA_MA[6] DDR_A_MA7 SB_MA[4] DDR_B_MA5
10 DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 SB_MA[5] T4
B DDR_A_MA8 DDR_B_MA6 B
10 DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 SB_MA[6] T3
V6 W5 DDR_A_MA9 AA9 R2 DDR_B_MA7
10 DDR_A_BS2 SA_BS[2] SA_MA[9] 11 DDR_B_BS0 SB_BS[0] SB_MA[7]
AD8 DDR_A_MA10 AA7 T5 DDR_B_MA8
SA_MA[10] 11 DDR_B_BS1 SB_BS[1] SB_MA[8]
V4 DDR_A_MA11 R6 R3 DDR_B_MA9
SA_MA[11] 11 DDR_B_BS2 SB_BS[2] SB_MA[9]
W4 DDR_A_MA12 AB7 DDR_B_MA10
SA_MA[12] DDR_A_MA13 SB_MA[10] DDR_B_MA11
10 DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 SB_MA[11] R1
AD9 V5 DDR_A_MA14 T1 DDR_B_MA12
10 DDR_A_RAS# SA_RAS# SA_MA[14] SB_MA[12]
AF9 V7 DDR_A_MA15 AA10 AB10 DDR_B_MA13
10 DDR_A_WE# SA_WE# SA_MA[15] 11 DDR_B_CAS# SB_CAS# SB_MA[13]
AB8 R5 DDR_B_MA14
11 DDR_B_RAS# SB_RAS# SB_MA[14]
AB9 R4 DDR_B_MA15
11 DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE
CONN@
TYCO_2013620-2_IVY BRIDGE
CONN@
+1.5V
1

R40
1K_0402_5%
Q6
BSS138_SOT23
2
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# 10,11

R41 1K_0402_5%
G
2
1

A A
R42 1 @ 2 DRAMRST_CNTRL_PCH 9,13,40
4.99K_0402_1% 0_0402_5% R43
1 2 EC_DRAMRST_CNTRL_PCH 40
0_0402_5% R44
2

PR-7
Instant ON
C73
0.047U_0402_16V7K Security Classification Compal Secret Data Compal Electronics, Inc.
2011/08/23 2012/12/31 Title
Issued Date Deciphered Date SCHEMATIC A8222
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 6 of 61
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

JCPU1E

CFG2
D D
VCC_DIE_SENSE AH27

1
CFG0 AK28 AH26
CFG[0] VSS_DIE_SENSE R45
AK29 CFG[1]
CFG2 AL26 1K_0402_1%
CFG[2]
AL27 CFG[3]
CFG4 AK26 L7

2
CFG5 CFG[4] RSVD28
AL29 CFG[5] RSVD29 AG7
CFG6 AL30 AE7
CFG[6] RSVD30
AM31 CFG[7] RSVD31 AK2
AM32 CFG[8]
AM30 W8

CFG
CFG10 CFG[9] RSVD32
AM28 CFG[10]
+VCC_GFXCORE_AXG CFG11 AM26 PEG Static Lane Reversal - CFG2 is for the 16x
CFG12 CFG[11]
AN28 CFG[12] RSVD33 AT26
+VCC_CORE CFG13 AN31 AM33
CFG14 CFG[13] RSVD34
AN26 CFG[14] RSVD35 AJ27 1:(Default) Normal Operation; Lane #
1

CFG15 AM27 CFG2

?? CFG16 AK31
CFG[15] definition matches socket pin map definition
R46 CFG17 CFG[16]
AN29 CFG[17] 0:Lane Reversed
1

49.9_0402_1%
R48 @
2

49.9_0402_1% T8
@ RSVD37 CFG4
RSVD38 J16
VCC_AXG_VAL_SENSE AJ31 H16
2

VAXG_VAL_SENSE RSVD39

1
VSS_AXG_VAL_SENSE AH31 G16
VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD40 @R47
@ R47
AJ33 VCC_VAL_SENSE
VSS_VAL_SENSE AH33 1K_0402_1%
VSS_VAL_SENSE
Please place as close as JCPU1

2
AJ26 RSVD5 RSVD_NCTF1 AR35
AT34

RESERVED
RSVD_NCTF2
RSVD_NCTF3 AT33
C C
RSVD_NCTF4 AP35
RSVD_NCTF5 AR34

Display Port Presence Strap

F25 RSVD8
F24 RSVD9
F23 RSVD10 1 : Disabled; No Physical Display Port
D24 RSVD11 RSVD_NCTF6 B34 CFG4 attached to Embedded Display Port
G25 RSVD12 RSVD_NCTF7 A33
G24 RSVD13 RSVD_NCTF8 A34
E23 RSVD14 RSVD_NCTF9 B35 0 : Enabled; An external Display Port device is
D23 C35
C30
RSVD15 RSVD_NCTF10 connected to the Embedded Display Port
RSVD16
A31 RSVD17
B30 RSVD18
B29 RSVD19
D30 AJ32 CFG6
RSVD20 RSVD51
B31 RSVD21 RSVD52 AK32
A30 CFG5
RSVD22
C29 RSVD23

1
?? VSS_AXG_VAL_SENSE
AN35 R49 R50
BCLK_ITP 1K_0402_1% 1K_0402_1%
J20 RSVD24 BCLK_ITP# AM35
VSS_VAL_SENSE B18 @ @
RSVD25

2
1

R51 R52 J15 AT2

49.9_0402_1% 49.9_0402_1% RSVD27 RSVD_NCTF11
RSVD_NCTF12 AT1
@ @ AR1
RSVD_NCTF13
2

B B

KEY B1 PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

Please place as close as JCPU1
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
TYCO_2013620-2_IVY BRIDGE
disabled
CONN@ 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 7 of 61
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+VCCP
+VCC_CORE
8.5A
97AAG35
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
D D
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
AF32 VCC14 VCCIO13 H14
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12

PEG AND DDR

VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
C C
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
AA30 VCC46 +VCCP
AA29 VCC47
AA28 PR-7
VCC48
AA27 VCC49
AA26 VCC50

0.1U_0402_16V4Z
Y35 H_CPU_SVIDCLK 1 2
CORE SUPPLY

VCC51 VR_SVID_CLK 50
Y34 1 R53 0_0402_5%
VCC52
Y33 VCC53 Place the PU

C74
Y32
Y31
VCC54 @ resistors close to CPU
VCC55

1
2
Y30 VCC56
Y29 R54
VCC57
Y28 VCC58 75_0402_5%
Y27 VCC59
Y26

2
VCC60
V35 VCC61
V34 AJ29 H_CPU_SVIDALRT# R55 1 2
SVID

VCC62 VIDALERT# VR_SVID_ALRT# 50

V33 AJ30 H_CPU_SVIDCLK 43_0402_1%
VCC63 VIDSCLK VR_SVID_DAT
V32 VCC64 VIDSOUT AJ28
+VCCP
V31 VCC65
V30 VCC66

0.1U_0402_16V4Z
V29 VCC67
B B
V28 VCC68 Place the PU 1
V27 VCC69 resistors close to CPU
1

V26 VCC70 R56 @ C75

U35 VCC71 130_0402_1% 2
U34 VCC72
U33 VCC73
U32
2

VCC74 VR_SVID_DAT
U31 VCC75 VR_SVID_DAT 50
U30 VCC76
U29 VCC77
U28 VCC78
U27 VCC79
U26 VCC80
R35 +VCC_CORE
VCC81
R34 VCC82
R33 VCC83
1

R32 VCC84
R31 R57
VCC85
R30 VCC86 100_0402_1%
R29 PR-7
VCC87
R28
SENSE LINES

VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R 1 2 VCCSENSE 50
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R58 1 2 0_0402_5% VSSSENSE 50
P35 R59 0_0402_5%
VCC91 +VCCP
P34 VCC92
1

P33 R60
VCC93 R61
P32 VCC94 VCCIO_SENSE B10 2 1
P31 A10 10_0402_1% 100_0402_1%
VCC95 VSS_SENSE_VCCIO
P30 VCC96
P29
2

VCC97
P28 VCC98
P27 VCC99 VCCIO_SENSE 48
A A
P26 VCC100
1

R62
0_0402_5%

Security Classification Compal Secret Data COMPAL Electronics，Inc

2

TYCO_2013620-2_IVY BRIDGE CONN@ 2011/08/23 2012/12/31 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 8 of 61
5 4 3 2 1
 5 4 3 2 1

+VCC_GFXCORE_AXG
JCPU1H

1
AT35 VSS1 VSS81 AJ22
R67 AT32 AJ19
100_0402_1% Place near CPU AT29
VSS2
VSS3
VSS82
VSS83 AJ16
AT27 VSS4 VSS84 AJ13
AT25 AJ10

2
VSS5 VSS85
VCC_AXG_SENSE 50 AT22 VSS6 VSS86 AJ7
+VCC_GFXCORE_AXG
AT19 AJ4

JCPU1G
POWER 1 2
VSS_AXG_SENSE 50
+V_SM_VREF should
AT16
AT13
AT10
VSS7
VSS8
VSS9
VSS87
VSS88
VSS89
AJ3
AJ2
AJ1
R68 100_0402_1% VSS10 VSS90
have 10 mil trace width AT7 VSS11 VSS91 AH35
33A AT4 VSS12 VSS92 AH34
AT24 AK35 AT3 AH32

SENSE
LINES
D VAXG1 VAXG_SENSE +1.5V VSS13 VSS93 D
AT23 AK34 +1.5V_CPU_VDDQ AR25 AH30
VAXG2 VSSAXG_SENSE VSS14 VSS94
AT21 VAXG3 AR22 VSS15 VSS95 AH29
AT20 VAXG4 AR19 VSS16 VSS96 AH28
AT18 VAXG5 2 1 AR16 VSS17 VSS98 AH25

1
AT17 0_0402_5% R69 @ AR13 AH22
VAXG6 R70 R71 VSS18 VSS99
AR24 VAXG7 AR10 VSS19 VSS100 AH19
AR23 1K_0402_1% 1K_0402_1% AR7 AH16
VAXG8 Q8 @ VSS20 VSS101
AR21 VAXG9 AR4 VSS21 VSS102 AH7
AR20 @ AR2 AH4

2
VAXG10 VSS22 VSS103

D
AR18 AL1 +V_SM_VREF_CNT 3 1 +V_SM_VREF AP34 AG9
VAXG11 SM_VREF VSS23 VSS104
AR17 VAXG12 1 AP31 VSS24 VSS105 AG8

1
AP24 AP28 AG4

VREF
VAXG13 VSS25 VSS106

1
0.1U_0402_16V7K R72 PMV45EN_SOT23-3

G
AP23 AP25 AF6

2
VAXG14 C149 1K_0402_1% R73 VSS26 VSS107
AP21 VAXG15 AP22 VSS27 VSS108 AF5
+V_DDR_REFA_R 2 @ 1K_0402_1%
AP20 VAXG16 SA_DIMM_VREFDQ B4 AP19 VSS28 VSS109 AF3
AP18 D1 +V_DDR_REFB_R AP16 AF2

2
VAXG17 SB_DIMM_VREFDQ RUN_ON_CPU1.5VS3 VSS29 VSS110
AP17 AP13 AE35

2
VAXG18 VSS30 VSS111
AN24 VAXG19 AP10 VSS31 VSS112 AE34
AN23 VAXG20 AP7 VSS32 VSS113 AE33
AN21 VAXG21 AP4 VSS33 VSS114 AE32
AN20 +1.5V_CPU_VDDQ AP1 AE31
VAXG22 VSS34 VSS115
AN18 AN30 AE30

DDR3 -1.5V RAILS

VAXG23 VSS35 VSS116
AN17 VAXG24 5A AN27 VSS36 VSS117 AE29
AM24 AF7 AN25 AE28

GRAPHICS
AM23
AM21
VAXG25
VAXG26
VAXG27
VDDQ1
VDDQ2
VDDQ3
AF4
AF1
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

330U_D2_2VM_R6M
AM20 VAXG28 VDDQ4 AC7 1 AN16 VSS40 VSS121 AE9
AM18 VAXG29 VDDQ5 AC4 1 1 1 1 1 1 AN13 VSS41 VSS122 AD7

C84

C78
AM17 AC1 + AN10 AC9
VAXG30 VDDQ6 VSS42 VSS123

C79

C80

C81

C82

C83
AL24 VAXG31 VDDQ7 Y7 AN7 VSS43 VSS124 AC8
AL23 VAXG32 VDDQ8 Y4 AN4 VSS44 VSS125 AC6
2 2 2 2 2 2 2 3
AL21 VAXG33 VDDQ9 Y1 AM29 VSS45 VSS126 AC5
AL20 VAXG34 VDDQ10 U7 AM25 VSS46 VSS127 AC3
AL18 VAXG35 VDDQ11 U4 AM22 VSS47 VSS128 AC2
AL17 VAXG36 VDDQ12 U1 AM19 VSS48 VSS129 AB35
AK24 VAXG37 VDDQ13 P7 AM16 VSS49 VSS130 AB34
C AK23 VAXG38 VDDQ14 P4 AM13 VSS50 VSS131 AB33 C
AK21 VAXG39 VDDQ15 P1 AM10 VSS51 VSS132 AB32
AK20 VAXG40 AM7 VSS52 VSS133 AB31
AK18 VAXG41 AM4 VSS53 VSS134 AB30
AK17 VAXG42 AM3 VSS54 VSS135 AB29
AJ24 VAXG43 AM2 VSS55 VSS136 AB28
AJ23 VAXG44 AM1 VSS56 VSS137 AB27
AJ21 VAXG45 AL34 VSS57 VSS138 AB26
AJ20 VAXG46 AL31 VSS58 VSS139 Y9
AJ18 VAXG47 6A AL28 VSS59 VSS140 Y8
AJ17 VAXG48 VCCSA1 M27 +VCCSA AL25 VSS60 VSS141 Y6
SA RAIL

AH24 VAXG49 VCCSA2 M26 AL22 VSS61 VSS142 Y5

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM
AH23 VAXG50 VCCSA3 L26 1 AL19 VSS62 VSS143 Y3

10U_0603_6.3V6M

330U_D2_2VM_R6M
AH21 J26 1 1 1 1 @ AL16 Y2
VAXG51 VCCSA4 + VSS63 VSS144
AH20 VAXG52 VCCSA5 J25 AL13 VSS64 VSS145 W35

C86

C87

C88

C89

C85
AH18 VAXG53 VCCSA6 J24 AL10 VSS65 VSS146 W34
AH17 VAXG54 VCCSA7 H26 AL7 VSS66 VSS147 W33
2 2 2 2 2 3
VCCSA8 H25 AL4 VSS67 VSS148 W32
AL2 VSS68 VSS149 W31
AK33 VSS69 VSS150 W30
+1.8VS AK30
AK27
VSS70 VSS151 W29
W28
VSS71 VSS152
AK25 W27
1.8V RAIL

VSS72 VSS153
VCCSA_SENSE H23 +VCCSA_SENSE 49 AK22 VSS73 VSS154 W26
1.5A AK19 VSS74 VSS155 U9
R277 AK16 U8
VSS75 VSS156

1
1 2 +1.8VS_CPU_VCCPLL B6 AK13 U6
VCCPLL1 @ R74 VSS76 VSS157
A6 C22 AK10 U5
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 49 VSS77 VSS158

10U_0805_6.3VAM

1U_0402_6.3V6K

1U_0402_6.3V6K

0_0805_5% 1 1 1 1 A2 C24 0_0402_5% AK7 U3

VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 49 VSS78 VSS159
330U_D2_2VM_R6M

AK4 VSS79 VSS160 U2

C94

C95

C96

C97

+ AJ25
2
PR-7 VSS80
2 2 2 VCCIO_SEL +3VS
VCCIO_SEL A19
2 3

TYCO_2013620-2_IVY BRIDGE CONN@ TYCO_2013620-2_IVY BRIDGE

2

CONN@
B R75 B
10K_0402_5% @
1

+1.5V_CPU_VDDQ 5A
+1.5V_CPU_VDDQ +1.5V
+1.5V Q7 +1.5V_CPU_VDDQ
+5VALW +5VALW AO4304L_SO8
C90 2 1 0.1U_0402_16V7K 8 1
7 2

20K_0402_5%
Q9 6 3 1
1

D BSS138_SOT23

10U_0603_6.3V6M
C91 2 1 0.1U_0402_16V7K 5

C76

R64
2 DRAMRST_CNTRL_PCH 6,13,40 R63
+V_DDR_REFA G R65 36.5K_0402_1%

4
+V_DDR_REFB C92 2
S 2 1 0.1U_0402_16V7K 100K_0402_5%
3

2
R77 1 @ 2 0_0402_5% +V_DDR_REFA_R
R78 1 @ 2 0_0402_5% +V_DDR_REFB_R RUN_ON_CPU1.5VS3

3
C93 2 1 0.1U_0402_16V7K
1

Q4B
1

2
D RUN_ON_CPU1.5VS3# 5
DRAMRST_CNTRL_PCH 2 Q10 R79 R80 C77
G 1K_0402_1% 1K_0402_1% 2N7002KDWH_SOT363-6 2200P_0402_50V7K

1
S BSS138_SOT23 @ @
3

R66 Q4A
40 CPU1.5V_S3_GATE 1 2 2
M3 Circuit (Processor Generated SO-DIMM VREF_DQ) 2N7002KDWH_SOT363-6
0_0402_5%
1

A RUN_ON_CPU1.5VS3# 42 A

PR-7

Security Classification Compal Secret Data COMPAL Electronics，Inc

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 9 of 61
5 4 3 2 1
 5 4 3 2 1

+1.5V 3.56A
+1.5V +1.5V 6 DDR_A_D[0..63]

1
6 DDR_A_DQS[0..7]
R81
1K_0402_1% DDR3 SO-DIMM A 6 DDR_A_DQS#[0..7]
JDIMM1
6 DDR_A_MA[0..15]

2
+V_DDR_REFA 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
VSS2 DQ4

0.1U_0402_10V6K

2.2U_0402_6.3V6M
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C98

C99
1 1 DDR_A_D1 7 8
DQ1 VSS3
1

9 10 DDR_A_DQS#0
R82 VSS4 DQS#0 DDR_A_DQS0
11 DM0 DQS0 12
D D
13 VSS5 VSS6 14
1K_0402_1% 2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7
2

DQ3 DQ7
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24 Layout Note:
25 VSS9 VSS10 26 Place near JDIMM1
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST# +1.5V
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,11
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DQ10 DQ14

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15

C100
37 VSS13 VSS14 38 1

C101

C102

C103

C104

C105

C106

C107
DDR_A_D16 39 40 DDR_A_D20 1 1 1 1 1 1 1
DDR_A_D17 DQ16 DQ20 DDR_A_D21 +
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 @
DDR_A_DQS2 DQS#2 DM2 2 2 2 2 2 2 2 2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72 Layout Note: Place these 4 Caps near
Command and Control signals of JDIMM1
C C
DDRA_CKE0 73 74 DDRA_CKE1 +1.5V
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
6 DDR_A_BS2 79 BA2 A14 80

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
81 VDD3 VDD4 82

C110

C111

C112

C113
DDR_A_MA12 83 84 DDR_A_MA11 1 1 1 1
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4 2 2 2 2
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
6 DDRA_CLK0 DDRA_CLK0 101 102 DDRA_CLK1
CK0 CK1 DDRA_CLK1 6
6 DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# 6 +1.5V
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6
6 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# 6

1
111 VDD13 VDD14 112
6 DDR_A_WE# DDR_A_WE# 113 114 DDRA_SCS0# R83 Layout Note:
WE# S0# DDRA_SCS0# 6
6 DDR_A_CAS# DDR_A_CAS# 115 116 DDRA_ODT0 1K_0402_1%
CAS# ODT0 DDRA_ODT0 6 Place near JDIMM1.203,204
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDRA_ODT1
DDRA_ODT1 6

2
DDRA_SCS1# A13 ODT1
6 DDRA_SCS1# 121 S1# NC2 122
123 VDD17 VDD18 124
125 126 +VREF_CA +0.75VS
NCTEST VREF_CA
127 VSS27 VSS28 128

0.1U_0402_10V6K

2.2U_0402_6.3V6M
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C108

C109
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37
133 VSS29 VSS30 134

1U_0402_6.3V6K
C114

1U_0402_6.3V6K
C115

1U_0402_6.3V6K
C116

1U_0402_6.3V6K
C117
B DDR_A_DQS#4 R84 B
135 DQS#4 DM4 136
DDR_A_DQS4 137 138 1K_0402_1% 1 1 1 1
DQS4 VSS31 DDR_A_D38 2 2
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44 2 2 2 2
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
197 SA0 EVENT# 198
A PCH_SMBDATA A
+3VS 199 VDDSPD SDA 200 PCH_SMBDATA 11,13,39,41
2.2U_0402_6.3V6M

0.1U_0402_10V6K

201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK 11,13,39,41
C119

1 1 203 VTT1 VTT2 204 +0.75VS

1

1
C153

10K_0402_5%
R85

10K_0402_5%
R86

205 206 [email protected]

G1 G2
2 2
TYCO_2-1932323-1_204P 9.2H Security Classification Compal Secret Data Compal Electronics, Inc.
2

CONN@
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 10 of 61
5 4 3 2 1
 5 4 3 2 1

+1.5V
+1.5V +1.5V

3.56A

1
R87
6 DDR_B_DQS#[0..7]
+V_DDR_REFB 1K_0402_1%
JDIMM2
6 DDR_B_D[0..63]
1 2

2
VREF_DQ VSS1 DDR_B_D4
0.1U_0402_10V6K 3 VSS2 DQ4 4 6 DDR_B_DQS[0..7]
R88 DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5
2.2U_0402_6.3V6M

1 1 DDR_B_D1 7 8
DQ1 VSS3 6 DDR_B_MA[0..15]

1
C120

9 10 DDR_B_DQS#0
C121 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12
13 VSS5 VSS6 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16
1K_0402_1%

D DDR_B_D3 DDR_B_D7 D
17 18
2

DQ3 DQ7
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,10
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44 Layout Note: Place these 4 Caps near Layout Note:
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS#2 DM2 Command and Control signals of JDDRH Place near JDDRH
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23 +1.5V +1.5V
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
55 56 DDR_B_D28 @
VSS20 DQ28

C122
DDR_B_D24 57 58 DDR_B_D29 1
DQ24 DQ29

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C123

C124

C125

C126

C127

C128

C129

C130
DDR_B_D25 59 60 1 1 1 1 1 1 1 1
DQ25 VSS21

C131

C132

C133

C134
61 62 DDR_B_DQS#3 +
VSS22 DQS#3 1 1 1 1
63 64 DDR_B_DQS3
DM3 DQS3 @ @
65 VSS23 VSS24 66
DDR_B_D26 DDR_B_D30 2 2 2 2 2 2 2 2 2
67 DQ26 DQ30 68
DDR_B_D27 DDR_B_D31 2 2 2 2
69 DQ27 DQ31 70
71 VSS25 VSS26 72

6 DDRB_CKE0 DDRB_CKE0 73 74 DDRB_CKE1

C CKE0 CKE1 DDRB_CKE1 6 C
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92 Layout Note:
93 VDD7 VDD8 94 Place near JDDRH.203 and 204
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100 +0.75VS
DDRB_CLK0 VDD9 VDD10 DDRB_CLK1
6 DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 6
6 DDRB_CLK0# DDRB_CLK0# 103 104 DDRB_CLK1#
CK0# CK1# DDRB_CLK1# 6
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 6 +1.5V

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K
6 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# 6

C135

C136

C137

C138
111 VDD13 VDD14 112 1 1 1 1
6 DDR_B_WE# DDR_B_WE# 113 114 DDRB_SCS0#
WE# S0# DDRB_SCS0# 6

1
6 DDR_B_CAS# DDR_B_CAS# 115 116 DDRB_ODT0
CAS# ODT0 DDRB_ODT0 6
117 118 R89
DDR_B_MA13 VDD15 VDD16 DDRB_ODT1 1K_0402_1% 2 2 2 2
119 A13 ODT1 120 DDRB_ODT1 6
6 DDRB_SCS1# DDRB_SCS1# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CB
125 NCTEST VREF_CA 126
0.1U_0402_10V6K

127 VSS27 VSS28 128

2.2U_0402_6.3V6M
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C139

DDR_B_D33 131 132 DDR_B_D37 1 1

DQ33 DQ37

1
C140
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 R90
DDR_B_DQS4 DQS#4 DM4 1K_0402_1%
137 DQS4 VSS31 138
B DDR_B_D38 2 2 B
139 VSS32 DQ38 140
DDR_B_D34 141 142 DDR_B_D39

2
DDR_B_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_B_D44
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152
153 154 DDR_B_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_B_DQS#7
VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
1 R91 2 195 VSS51 VSS52 196
10K_0402_5% 197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 VDDSPD SDA 200 PCH_SMBDATA 10,13,39,41
0.1U_0402_10V6K

201 202 PCH_SMBCLK

SA1 SCL PCH_SMBCLK 10,13,39,41
2.2U_0402_6.3V6M

C142

A A
1 1 1 2 203 VTT1 VTT2 204 +0.75VS
R92 10K_0402_5%
[email protected]
C141

205 G1 G2 206
2 2 TYCO_2-2013287-1_204P
CONN@ 5.2H
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 11 of 61
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1 +3V_PCH

0.1U_0402_16V4Z~D
Please close to JXDP2
1 2 PCH_RTCX2 1
R93 10M_0402_5% C143 JXDP2
Y1 1
XDP@ 1
1 2 2 2
+RTCVCC 2
3 3
4 4
32.768KHZ_12.5PF_9H03200019 1 2 SM_INTRUDER# 5
R94 1M_0402_5% 5
6 6
7 7
1 1 8 8
1K_0402_5% 9
C144 C145 R95 XDP@2 RSMRST#_XDP 9
14,40 PCH_RSMRST# 1 10 10
18P_0402_50V8J 18P_0402_50V8J R96 1 XDP@ 2 PCH_PWRBTN#_XDP 11
2 2 14,40 PBTN_OUT# 11
D 0_0402_5% 12 D
12
13 13
+1.05VS R97 1 XDP@ 2 14
0_0402_5% 14
15 15
+3V_PCH R98 1 XDP@ 2 +3V_PCH_XDP 16
0_0402_5% 16
CLRP1 & CLRP2 place near DIMM XDP_DBRESET#_R
17
18
17
U3A 5,14 XDP_DBRESET#_R 18
19 19
far away hot spot PCH_JTAG_TDO 20
+RTCVCC PCH_RTCX1 LPC_AD0 20
1 A20 RTCX1 FWH0 / LAD0 C38 LPC_AD0 40,41 21 21

1
CMOS A38 LPC_AD1 PCH_JTAG_TDI 22
FWH1 / LAD1 LPC_AD1 40,41 22

LPC
C146 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2 PCH_JTAG_TMS 23
RTCX2 FWH2 / LAD2 LPC_AD2 40,41 23
1U_0603_10V6K SHORT PADS C37 LPC_AD3 24
LPC_AD3 40,41

2
2 PCH_RTCRST# FWH3 / LAD3 24
1 2 D20 RTCRST# 25 25 G1 27
R99 20K_0402_5% D36 LPC_FRAME# PCH_JTAG_TCK 26 28
FWH4 / LFRAME# LPC_FRAME# 40,41 26 G2
1 2 PCH_SRTCRST# G22
R100 20K_0402_5% SRTCRST# LPC_LDRQ0# ACES_87152-26051
1 LDRQ0# E36 @ T12 PAD~D

RTC
SM_INTRUDER# K22 K36 LPC_LDRQ1# @ CONN@
INTRUDER# LDRQ1# / GPIO23 T13 PAD~D
C147 CLRP2
PR-7 1U_0603_10V6K SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 40

2
2 ME CMOS INTVRMEN SERIRQ
40 HDA_SDO 1 2 HDA_SDOUT
R101 0_0402_5% AM3 SATA_PRX_DTX_N0 31
HDA_BIT_CLK SATA0RXN
N34 HDA_BCLK SATA0RXP AM1 SATA_PRX_DTX_P0 31
HDA for AUDIO HDD1 +3VS

SATA 6G
SATA0TXN AP7 SATA_PTX_DRX_N0 31
HDA_SYNC L34 AP5
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 31
33 HDA_BITCLK_AUDIO 1 2 HDA_BIT_CLK
R102 33_0402_5% HDA_SPKR T10 AM10 SATA_PRX_DTX_N1 31 SERIRQ R103 2 1 10K_0402_5%
SPKR SATA1RXN
SATA1RXP AM8 SATA_PRX_DTX_P1 31
1 HDA_RST# K34 AP11 HDD2 +RTCVCC PCH_GPIO21 R104 2 1 10K_0402_5%
HDA_RST# SATA1TXN SATA_PTX_DRX_N1 31
@ C148 AP10
SATA1TXP SATA_PTX_DRX_P1 31
10P_0402_50V8J PCH_SATALED#R105 2 1 10K_0402_5%
HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 31 PCH_INTVRMEN R106 2 1 330K_0402_5%
2 33 HDA_SDIN0 HDA_SDIN0 SATA2RXN
AD5 SATA_PRX_DTX_P2 31 BBS_BIT0_R R107 2 1 10K_0402_5%
SATA2RXP
Reserve for EMI G34 HDA_SDIN1 SATA2TXN AH5 SATA_PTX_DRX_N2 31 ODD
please close to RH170 SATA2TXP AH4 SATA_PTX_DRX_P2 31
C34 HDA_SDIN2
INTVRMEN

IHDA
C SATA3RXN AB8 C

33 HDA_RST_AUDIO# 1 2 HDA_RST# A34 HDA_SDIN3 SATA3RXP AB10

AF3
* H：Integrated
L：Integrated
VRM enable
VRM disable +3VS
R108 33_0402_5% SATA3TXN
HDA_SDOUT SATA3TXP AF1
33 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT
R109 33_0402_5% A36 HDA_SDO HDA_SPKR R110 @ 1 1K_0402_5%

SATA
SATA4RXN Y7 2
SATA4RXP Y5
PCH_SPI_WP C36 HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP
AD3
AD1 *LOW=Default
HIGH=No Reboot
N32 HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK J3 AB1
JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA
JTAG_TMS SATAICOMPO
1

JTAG
R111 R112 R113
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
@ @ @ JTAG_TDI SATAICOMPI R114 37.4_0402_1%
200_0402_5% 200_0402_5% 200_0402_5%
PCH_JTAG_TDO H1 JTAG_TDO +1.05VS_SATA3
AB12
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SATA3RCOMPO

AB13 SATA3_COMP 1 2
SATA3COMPI
1

R116 R117 R118 R115 49.9_0402_1%

100_0402_1% 100_0402_1% 100_0402_1% PCH_SPI_CLK_RR T3 AH1 RBIAS_SATA3 1 2

SPI_CLK SATA3RBIAS R120 750_0402_1%
PCH_SPI_CS#_RR Y14
2

SPI_CS0# R123
T1 2 1 FLASH_EN HDA_SYNC
SPI_CS1#
SPI

P3 PCH_SATALED#
SATALED# PCH_SATALED# 39
10K_0402_5% This signal has a weak internal pull-down
R124 2 1 PCH_JTAG_TCK PCH_SPI_SI_RR V4 V14 PCH_GPIO21 On Die PLL VR is supplied by
51_0402_5% SPI_MOSI SATA0GP / GPIO21
1.5V when smapled high
PCH_SPI_SO_RR U3 P1 BBS_BIT0_R
+5VS SPI_MISO SATA1GP / GPIO19 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
B PANTHER-POINT_FCBGA989 B
Please place to close to U3 +3V_PCH
2
G

33 HDA_SYNC_AUDIO 1 2 3 1 HDA_SYNC HDA_SYNC R128 2 1 1K_0402_5%

R127 33_0402_5%
S

BSS138_SOT23
1

Q11
R129
1M_0402_5%

+3V_PCH
2

+3V_SPI
SPI ROM ( 4M/8MByte ) 1
U4
VDD FLASH_EN
4 VDD SEL 12 FLASH_EN 40
+3V_SPI 9 VDD
19 VDD YA 2 +3V_SPI
R132 1 2PCH_SPI_WP# 5 PCH_SPI_CS#_R
3.3K_0402_5% YB PCH_SPI_CLK PCH_SPI_CLK_R +RTCBATT
+3VS 24 A0 YC 6 1 2
0.1U_0402_16V4Z

R131 PCH_SPI_CS#_RR 22 0_0402_5%

R134 1 B0
2PCH_SPI_HOLD# PCH_SPI_CLK_RR 1 2 PCH_SPI_CLK_RRR 18 8 PCH_SPI_SI_R R133
1 C0 YD
RTC Battery

1
3.3K_0402_5% C150 0_0402_5% PCH_SPI_SI_RR 17 11 PCH_SPI_SO_R EMI
PCH_SPI_SO_RR D0 YE R136
EMI 14 E0
PCH_SPI_WP# 2
23 3
MAX. 8000mil 1K_0402_5%
+3VALW A1 GND
39,40 KSI4 KSI4 21 7 D1

2
@ U5 KSI5 B1 GND +RTCVCC
39,40 KSI5 16 C1 GND 10
PCH_SPI_WP 1 2 PCH_WP 8 4 39,40 KSI6 KSI6 15 20 2 W=20mils
VCC VSS D1 GND
1

R137 0_0402_5% Q63 D KSI7

39,40 KSI7 13 W=20mils 1
PCH_SPI_WP# E1
40 EC_SPI_WP 1 2 2 3 W 3 +CHGRTC
R135 0_0402_5% PI3V512QE_QSOP24

0.1U_0402_16V4Z
G W=20mils
S PCH_SPI_HOLD# 7 1
3

HOLD C154 DAN202UT106_SC70-3

2N7002KW 1N SOT323-3 PCH_SPI_CS#_R 1 S
C152 R139 PCH_SPI_CLK_R 2
A 6 C A
2 1 1 2PCH_SPI_CLK_RRR
@ 33_0402_5% @ PCH_SPI_SI_R 5 2 PCH_SPI_SO_R
22P_0402_50V8J D Q
Reserve for EMI please close to U4 W25Q32BVSSIG_SO8
W7@
U5

W8@
C155
R142
2
@
1 1 2PCH_SPI_CLK_R
0_0402_5% @
Security Classification Compal Secret Data Compal Electronics, Inc.
W25Q64FVSSIG_SO8 Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
10P_0402_50V8J 8M ROM=SA000039A20
Reserve for EMI please close to U5 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 12 of 61
5 4 3 2 1
 5 4 3 2 1

SMBALERT# 2 1 +3V_PCH
R149 10K_0402_5%
SMBCLK 1 2
R150 2.2K_0402_5%
SMBDATA 1 2
U3B R151 2.2K_0402_5%
SML0CLK 1 2
D PCIE_PRX_GLANTX_N1 BG34 R152 2.2K_0402_5% D
32 PCIE_PRX_GLANTX_N1 PERN1
32 PCIE_PRX_GLANTX_P1 PCIE_PRX_GLANTX_P1 BJ34 E12 SMBALERT# SML0DATA 1 2
PERP1 SMBALERT# / GPIO11 SMBALERT# 39
10/100/1G LAN ---> C158 1 2 0.1U_0402_16V7K PCIE_PTX_GLANRX_N1_C AV32 R153 2.2K_0402_5%
32 PCIE_PTX_GLANRX_N1 PETN1
C159 1 2 0.1U_0402_16V7K PCIE_PTX_GLANRX_P1_C AU32 H14 SMBCLK PCH_SMLCLK 1 2
32 PCIE_PTX_GLANRX_P1 PETP1 SMBCLK
MEMORY R154 2.2K_0402_5%
41 PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_N2 BE34 C9 SMBDATA PCH_SMLDATA 1 2
PCIE_PRX_WLANTX_P2 PERN2 SMBDATA R155 2.2K_0402_5%
41 PCIE_PRX_WLANTX_P2 BF34 PERP2
MiniWLAN (Mini Card 1)---> C160 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2_C BB32
41 PCIE_PTX_WLANRX_N2 PETN2
C161 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_P2_C AY32 PCH_HOT# 1 2
41 PCIE_PTX_WLANRX_P2 PETP2

SMBUS
A12 DRAMRST_CNTRL_PCH R156 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 6,9,40
BG36 PERN3
BJ36 C8 SML0CLK DRAMRST_CNTRL_PCH 1 2
PERP3 SML0CLK R157 1K_0402_1%
AV34 PETN3
AU34 G12 SML0DATA
PETP3 SML0DATA
36 PCIE_PRX_USB3TX_N4 PCIE_PRX_USB3TX_N4 BF36
USB30@ PCIE_PRX_USB3TX_P4 PERN4 DRAMRST_CNTRL_PCH
36 PCIE_PRX_USB3TX_P4 BE36 PERP4 2 1
USB3.0 controller ---> C1043 1 2 0.1U_0402_16V7K PCIE_PTX_USB3RX_N4_C AY34 C13 PCH_HOT# R750 100K_0402_1%
36 PCIE_PTX_USB3RX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C1044 1 2 0.1U_0402_16V7K PCIE_PTX_USB3RX_P4_C BB34 @
36 PCIE_PTX_USB3RX_P4 PETP4
USB30@ E14 PCH_SMLCLK PCH_SMLCLK 20,40
SML1CLK / GPIO58

PCI-E*
BG37 PERN5 PCH_SMLDATA
EC
BH37 PERP5 SML1DATA / GPIO75 M16 PCH_SMLDATA 20,40
AY36 PETN5
BB36 PETP5
BJ38 PERN6
BG38 PERP6

Controller
AU36 M7 @ T14 PAD CLKIN_DMI2# R158 1 2 10K_0402_5%
PETN6 CL_CLK1 CLKIN_DMI2 R159 10K_0402_5%
AV36 PETP6 1 2
CLKIN_DMI# R160 1 2 10K_0402_5%

Link
BG40 T11 @ T15 PAD CLKIN_DMI R161 1 2 10K_0402_5%
PERN7 CL_DATA1 CLKIN_DOT96# R162 10K_0402_5%
BJ40 PERP7 1 2
C AY40 CLKIN_DOT96 R163 1 2 10K_0402_5% C
PETN7 @ T16 PAD CLKIN_SATA# R164 10K_0402_5%
BB40 PETP7 CL_RST1# P10 1 2
CLKIN_SATA R165 1 2 10K_0402_5%
BE38 CLK_PCH_14M R166 1 2 10K_0402_5%
PERN8
BC38 PERP8
AW38 PETN8
AY38 If use extenal CLK gen, please place close to CLK gen
PETP8 else, please place close to PCH
M10 PEG_CLKREQ#_R
PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ#_R 20
R167 1 2 0_0402_5% PCIE_LAN# Y40
32 CLK_PCIE_LAN# CLKOUT_PCIE0N
10/100/1G LAN ---> R168 1 2 0_0402_5% PCIE_LAN Y39
32 CLK_PCIE_LAN CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA#
CLKOUT_PEG_A_N CLK_PCIE_VGA# 20
R169 1 2 10K_0402_5% LANCLK_REQ# CLK_PCIE_VGA

CLOCKS
+3V_PCH J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA 20 VGA
32 LANCLK_REQ#
R170 2 1 0_0402_5% PCIE_WLAN# AB49 AV22 CLK_CPU_DMI#
41 CLK_PCIE_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5 +3VS +3VS
R171 2 1 0_0402_5% PCIE_WLAN AB47 AU22 CLK_CPU_DMI
41 CLK_PCIE_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
MiniWLAN (Mini Card 1)---> +3VS R172 2 1 10K_0402_5%
41 WLANCLK_REQ# WLANCLK_REQ# M1 PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12
CLKOUT_DP_P AM13

2
AA48 CLKOUT_PCIE2N
AA47 R173 R174
CLKOUT_PCIE2P CLKIN_DMI#
CLKIN_DMI_N BF18 2.2K_0402_5% 2.2K_0402_5%
+3VS R175 1 2 10K_0402_5% V10 BE18 CLKIN_DMI
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

1
2
R1054 2 USB30@ 1 0_0402_5% PCIE_USB30# Y37 BJ30 CLKIN_DMI2#
36 CLK_PCIE_USB30# CLKOUT_PCIE3N CLKIN_GND1_N
R1055 2 USB30@ 1 0_0402_5% PCIE_USB30 Y36 BG30 CLKIN_DMI2 SMBCLK 6 1
36 CLK_PCIE_USB30 CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 10,11,39,41
USB3.0 controller --->
+3V_PCH R176 2 1 10K_0402_5% A8 2N7002KDWH_SOT363-6
PCIECLKRQ3# / GPIO25 CLKIN_DOT96#
36 CLKREQ_USB30# CLKIN_DOT_96N G24 Q2A
B E24 CLKIN_DOT96 B
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N

5
Y45 CLKOUT_PCIE4P
AK7 CLKIN_SATA#
R177 CLKIN_SATA_N
+3V_PCH 2 1 10K_0402_5% L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5 CLKIN_SATA SMBDATA 3 4 PCH_SMBDATA 10,11,39,41
2N7002KDWH_SOT363-6
V45 K45 CLK_PCH_14M Q2B
CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
+3V_PCH R178 2 1 10K_0402_5% L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 15

AB42 V47 XTAL25_IN

CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
@ @
R180 C162 +3V_PCH R179 1 2 10K_0402_5% PEG_B_CLKREQ# E6
CLK_PCI_LPBACK2 PEG_B_CLKRQ# / GPIO56
1 1 2
33_0402_5% 22P_0402_50V8J Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
XCLK_RCOMP R181 90.9_0402_1%
Reserve for EMI please close to V40 CLKOUT_PCIE6N
U3 V42 CLKOUT_PCIE6P
+3V_PCH R182 1 2 10K_0402_5% PCIE_CLKREQ6# T13 PCIECLKRQ6# / GPIO45
XTAL25_IN V38 K43 CLK_SD_48M_R 1 2 CLK_SD_48M
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_SD_48M 34
R185 0_0402_5%
FLEX CLOCKS

V37 CLKOUT_PCIE7P
2 1 XTAL25_OUT F47 @ T17 PAD
1M_0402_5% R183 R184 1 CLKOUTFLEX1 / GPIO65
+3V_PCH 2 10K_0402_5% GPIO46 K12 PCIECLKRQ7# / GPIO46
H47 @ T18 PAD
PAD T48 @ CLK_BCLK_ITP# CLKOUTFLEX2 / GPIO66
Y2 AK14 CLKOUT_ITPXDP_N
PAD T49 @ CLK_BCLK_ITP AK13 K49 @ T19 PAD
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
A 1 3 A
1 3 PANTHER-POINT_FCBGA989
GND GND
2 2 4 2
C164
C163 25MHZ_10PF_ 7V25000014 12P_0402_50V8J
12P_0402_50V8J
1 1 @ @

CLK_PCH_14M
R189 C165 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 1 2 Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
33_0402_5% 22P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 13 of 61
5 4 3 2 1
 5 4 3 2 1

PCH_ENBKL
U3C 40 PCH_ENBKL
U3D

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4 1 R190 2 J47 AP43

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1 100K_0402_5% M45 L_BKLTEN SDVO_TVCLKINN
4 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 4 30 PCH_ENVDD L_VDD_EN SDVO_TVCLKINP AP45
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
4 DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 4 30 PCH_INV_PWM P45 L_BKLTCTL SDVO_STALLN AM42
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 4 AM40
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5 SDVO_STALLP
4 DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 4 30 PCH_LCD_CLK T40 L_DDC_CLK
4 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 4 K47 AP39
DMI1RXP FDI_RXN6 30 PCH_LCD_DATA L_DDC_DATA SDVO_INTN
4 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 4 AP40
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7 CTRL_CLK SDVO_INTP
D 4 DMI_CTX_PRX_P3 BJ20 DMI3RXP T45 L_CTRL_CLK
D
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 4 CTRL_DATA P39
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 L_CTRL_DATA
4 DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 4
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK HDMICLK_NB 35
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4 R191 2.37K_0402_1%~D AF36 M39 HDMIDAT_NB
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA HDMIDAT_NB 35
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 4 T20
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4 PAD~D AE48
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 LVD_VREFH
4 DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 4 AE47 LVD_VREFL DDPB_AUXN AT49
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4 AT47
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 DDPB_AUXP
DMI_CRX_PTX_P2 AY18 AT40 TMDS_B_HPD
4 DMI_CRX_PTX_P2 DMI2TXP DDPB_HPD TMDS_B_HPD 35
DMI_CRX_PTX_P3 AU18 PCH_TXCLK- AK39
4 DMI_CRX_PTX_P3 DMI3TXP 30 PCH_TXCLK- LVDSA_CLK#

LVDS
AW16 FDI_INT PCH_TXCLK+ AK40 AV42 TMDS_B_DATA2#
FDI_INT FDI_INT 4 30 PCH_TXCLK+ LVDSA_CLK DDPB_0N TMDS_B_DATA2# 35
DDPB_0P AV40 TMDS_B_DATA2 TMDS_B_DATA2 35
+1.05VS_VCC_EXP BJ24 AV12 FDI_FSYNC0 PCH_TXOUT0- AN48 AV45 TMDS_B_DATA1#
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4 30 PCH_TXOUT0- LVDSA_DATA#0 DDPB_1N TMDS_B_DATA1# 35
PCH_TXOUT1- AM47 AV46 TMDS_B_DATA1
30 PCH_TXOUT1- TMDS_B_DATA1 35

Digital Display Interface

DMI_IRCOMP FDI_FSYNC1 PCH_TXOUT2- LVDSA_DATA#1 DDPB_1P
1 2 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4 30 PCH_TXOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0# TMDS_B_DATA0# 35
R192 49.9_0402_1% AJ48 LVDSA_DATA#3 DDPB_2P AU47 TMDS_B_DATA0 TMDS_B_DATA0 35
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AV47 TMDS_B_CLK#
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4 DDPB_3N TMDS_B_CLK# 35
R193 750_0402_1% PCH_TXOUT0+ AN47 AV49 TMDS_B_CLK
30 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P TMDS_B_CLK 35
4mil width and place BB10 FDI_LSYNC1 PCH_TXOUT1+ AM49
FDI_LSYNC1 FDI_LSYNC1 4 30 PCH_TXOUT1+ LVDSA_DATA1
PCH_TXOUT2+ AK49
within 500mil of the PCH 30 PCH_TXOUT2+
AJ47
LVDSA_DATA2
P46
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA P42
A18 DSWODVREN
DSWVRMEN PCH_TZCLK-
30 PCH_TZCLK- AF40 LVDSB_CLK#
R800 1 @ 2 0_0402_5% PCH_DPWROK PCH_TZCLK+

System Power Management

PCH_DPWROK 40 30 PCH_TZCLK+ AF39 LVDSB_CLK DDPC_AUXN AP47
40 SUSACK# R802 1 @ 2 SUSACK#_R C12 E22 PCH_DPWROK_R AP49
0_0402_5% SUSACK# DPWROK R194 1 DDPC_AUXP
2 0_0402_5% PCH_RSMRST#_R 30 PCH_TZOUT0-
PCH_TZOUT0- AH45 LVDSB_DATA#0 DDPC_HPD AT38
PCH_TZOUT1- AH47
30 PCH_TZOUT1- LVDSB_DATA#1
5,12 XDP_DBRESET#_R XDP_DBRESET#_R K3 B9 WAKE# 1 R195 2 PCIE_WAKE# 32,36,41 PCH_TZOUT2- AF49 AY47
SYS_RESET# WAKE# 30 PCH_TZOUT2- LVDSB_DATA#2 DDPC_0N
0_0402_5% AF45 AY49
PR-7 PR-7 LVDSB_DATA#3 DDPC_0P
DDPC_1N AY43
SYSTEM_PWROK 1 2 SYSTEM_PWROK_I P12 N3 PM_CLKRUN# 1 R267 2 PM_CLKRUNEC# 40 PCH_TZOUT0+ AH43 AY45
SYS_PWROK CLKRUN# / GPIO32 30 PCH_TZOUT0+ LVDSB_DATA0 DDPC_1P
R196 0_0402_5% @ 0_0402_5% PCH_TZOUT1+ AH49 BA47
30 PCH_TZOUT1+ LVDSB_DATA1 DDPC_2N
PCH_TZOUT2+ AF47 BA48
C 30 PCH_TZOUT2+ LVDSB_DATA2 DDPC_2P C
40 PCH_PWROK 1 2 PM_PWROK_R L22 G8 SUS_STAT# T22 PAD AF43 BB47
R197 0_0402_5% PWROK SUS_STAT# / GPIO61 LVDSB_DATA3 DDPC_3N
DDPC_3P BB49
PR-7 R198 1 2 0_0402_5% L10 N14 SUSCLK 2 R199 1
APWROK SUSCLK / GPIO62 SUSCLK_R 40
0_0402_5% PCH_CRT_BLU N48 M43
30 PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
PCH_CRT_GRN P49 M36
30 PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PCH_CRT_RED T49
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 40 30 PCH_CRT_RED CRT_RED
PR-7 AT45
DDPD_AUXN

CRT
12,40 PCH_RSMRST# 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4# PCH_CRT_DDC_CLK T39 AT43
RSMRST# SLP_S4# PM_SLP_S4# 40 30 PCH_CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
R200 0_0402_5% PCH_CRT_DDC_DAT M40 BH41
30 PCH_CRT_DDC_DAT CRT_DDC_DATA DDPD_HPD
R801 1 @ 2 SUSWARN#_R K16 F4 PM_SLP_S3# R201 33_0402_5% BB43
40 SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 40 DDPD_0N
0_0402_5% 30 PCH_CRT_HSYNC 1 2 HSYNC_PCH M47 BB45
CRT_HSYNC DDPD_0P
PR-7
30 PCH_CRT_VSYNC 1 2 VSYNC_PCH M49 CRT_VSYNC DDPD_1N BF44
12,40 PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 T23 PAD R202 33_0402_5% BE44
R203 0_0402_5% PWRBTN# SLP_A# DDPD_1P
DDPD_2N BF42
D2 CRT_IREF T43 BE42
AC_PRESENT_R T24 PAD DAC_IREF DDPD_2P
40,44 ACIN 1 2 H20 ACPRESENT / GPIO31 SLP_SUS# G16 T42 CRT_IRTN DDPD_3N BJ42
@ BG42
DDPD_3P

1
RB751V-40_SOD323-2
PCH_GPIO72 E10 AP14 H_PM_SYNC PANTHER-POINT_FCBGA989
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
Reserve 40 AC_PRESENT R751 1 2 0_0402_5% R204
1K_0402_0.5%
RI# A10 K14 PCH_GPIO29 T25 PAD

2
PR-7 RI# SLP_LAN# / GPIO29

PANTHER-POINT_FCBGA989

@ 1 2 XDP_DBRESET#_R
C166 100P_0402_50V8J

B +3VS B

Reserve for EMI please close to U3

1 2 PCH_CRT_DDC_CLK
R206 2.2K_0402_5%
1 2 PCH_CRT_DDC_DAT
R207 2.2K_0402_5%
+3VS 1 2 CTRL_CLK
R208 2.2K_0402_5%
5

PR-7 U7 1 2 CTRL_DATA +3VS

1 2 2 +RTCVCC R209 2.2K_0402_5%
P

50 VGATE
R210 0_0402_5% B 4 SYSTEM_PWROK R211 1 2 2.2K_0402_5% PCH_LCD_CLK
Y SYSTEM_PWROK 5
PCH_PWROK 1 A R212 1 2 2.2K_0402_5% PCH_LCD_DATA
G

DSWODVREN R213 2 1 330K_0402_5%

NC7SZ08P5X_NL_SC70-5
3

DSWODVREN R214 2 @ 1 330K_0402_5%

+3V_PCH DSWODVREN - On Die DSW VR Enable

* H：Enable
L：Disable 1 2 PCH_CRT_BLU
PCH_GPIO29 R230 1 2 10K_0402_5% R215 150_0402_1%~D
1 2 PCH_CRT_GRN
R216 150_0402_1%~D
PCH_GPIO72 R217 1 2 10K_0402_5% 1 2 PCH_CRT_RED
R218 150_0402_1%~D
RI# R219 1 2 10K_0402_5% 1 2 PCH_ENVDD
R220 @ 100K_0402_5%~D
WAKE# R221 1 2 10K_0402_5% +3VS

AC_PRESENT_R R222 1 2 200K_0402_5%

1

SUSWARN#_R R223 1 2 10K_0402_5%

R224
@ 8.2K_0402_5%
A A
PCH_DPWROK R803 2 @ 1 100K_0402_5%
2

PCH_RSMRST# R225 1 2 10K_0402_5% PM_CLKRUN#

2

R130
PM_PWROK_R 2 1 10K_0402_5%

SYSTEM_PWROK_I
R226 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 Issued Date 2011/10/19 Deciphered Date 2012/12/31 Title
1

@ R227 100K_0402_5% Intel CRB EMRLDLKE2 Rev1.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 14 of 61
5 4 3 2 1
 5 4 3 2 1

U3E

RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25
BJ16
TP3
AT10
GPIO19 => BBS_BIT0
TP4 RSVD5
BG16
AH38
TP5 RSVD6 BC8 GPIO51 => BBS_BIT1
TP6
AH37 TP7 RSVD7 AU2 Boot BIOS Strap
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3 BBS_BIT0 BBS_BIT1 Boot BIOS
C18 AT1
N30
TP10 RSVD10
AY3
Location
TP11 RSVD11
D
H3 TP12 RSVD12 AT5 0 0 LPC D
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1 0 1 Reserved(NAND)
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3 Panther Point USB Port Mapping 1 0 Reserved
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3 1 1 SPI *
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8 USB 2.0 Port Number USB 3.0 Port Number

RSVD
RSVD21 BD4
RSVD22 BF6
0 1
B21 AV5 NV_ALE
TP21 RSVD23
M20 TP22 RSVD24 AV10
AY16 TP23 1 2 Intel Anti-Theft Techonlogy
BG46 TP24 RSVD25 AT8
High=Endabled
RSVD26 AY5 2 3 NV_ALE
BA2 Low=Disable(floating)
37 USB3_RX1_N BE28 USB3Rn1
RSVD27 *
37 USB3_RX2_N BC30 USB3Rn2 RSVD28 AT12 3 4 +1.8VS
BE32 USB3Rn3 RSVD29 BF3
BJ32 USB3Rn4
37 USB3_RX1_P BC28 NV_ALE @ R228 1 2 1K_0402_5%
USB3Rp1
37 USB3_RX2_P BE30 USB3Rp2
BF32 USB3Rp3
BG32 C24 USB20_N0
USB3Rp4 USBP0N USB20_N0 37
AV26 A24 USB20_P0 USB2/3 port 1
37 USB3_TX1_N USB3Tn1 USBP0P USB20_P0 37
BB26 C25 USB20_N1
37 USB3_TX2_N USB3Tn2 USBP1N USB20_N1 37
AU28 B25 USB20_P1 USB2/3 port 2
USB3Tn3 USBP1P USB20_P1 37
AY30 C26 USB20_N2
USB3Tn4 USBP2N USB20_N2 33
AU26 A26 USB20_P2 USB2 Conn. R
37 USB3_TX1_P USB3Tp1 USBP2P USB20_P2 33
AY26 K28 USB20_N3
C 37 USB3_TX2_P USB3Tp2 USBP3N USB20_N3 30 C
AV28 H28 USB20_P3 Camera
USB3Tp3 USBP3P USB20_P3 30
AW30 E28 USB20_N4 USB20_N4 34
USB3Tp4 USBP4N USB20_P4
USBP4P D28
USB20_N5
USB20_P4 34 Card Reader
USBP5N C28 USB20_N5 33
A28 USB20_P5 USB20_P5 33 USB2 Conn. R
USBP5P
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28 HM76 not Support USB Port6,7 +3V_PCH
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# PIRQC# USBP8N USB_OC0# 10K_0402_5% R76
G38 PIRQD# USBP8P K30
USB_OC2# 10K_0402_5%
1 2
R229
Over Current Pin Default Usage
USBP9N G30 1 2
DGPU_HOLD_RST# C46 E30 USB_OC7# 10K_0402_5% 1 2 R582
REQ1# / GPIO50 USBP9P

USB
PCH_GPIO52 C44 C30 USB20_N10 USB_OC5# 10K_0402_5% 1 2 R725
REQ2# / GPIO52 USBP10N USB20_N10 41
29,53 DGPU_PWR_EN
DGPU_PWR_EN E40 A30 USB20_P10
USB20_P10 41 Mini Card(WLAN) Bluetooth OC Pin PCH Mapping
REQ3# / GPIO54 USBP10P
USBP11N L32
D47 GNT1# / GPIO51 USBP11P K32
E42 GNT2# / GPIO53 USBP12N G32 0 Port 0 & 1
41 PCH_WAN_RADIO_OFF# PCH_WAN_RADIO_OFF# F46 E32 USB_OC1# 10K_0402_5% 1 2 R780
GNT3# / GPIO55 USBP12P USB_OC4# 10K_0402_5% R781
USBP13N C32 1 2
USBP13P A32 USB_OC3# 10K_0402_5% 1 2 R782 1 Port 2 & 3
C167 PCH_GPIO2 G42 USB_OC6# 10K_0402_5% 1 2 R783
@ ODD_DA# ODD_DA# PIRQE# / GPIO2
1 2 31 ODD_DA# G40 PIRQF# / GPIO3 Within 500 mils
0.1U_0402_16V4Z~D PCH_GPIO4 C42 PIRQG# / GPIO4 USBRBIAS# C33 USBRBIAS 1 2 2 Port 4 & 5
PCH_GPIO5 D44 R231 22.6_0402_1%
PIRQH# / GPIO5
Reserve for EMI please close to U3
USBRBIAS B33 3 Port 6 & 7
PAD T26 @ K10 PME#
PCH_PLTRST# C6 PLTRST# OC0# / GPIO59 A14 USB_OC0#
USB_OC0# 37 (For USB Port0, 1) 4 Port 8 & 9
K20 USB_OC1# (For USB Port2)
OC1# / GPIO40 USB_OC1# 37
B17 USB_OC2# (For USB Port5)
OC2# / GPIO41 USB_OC2# 37
B
13 CLK_PCI_LPBACK
CLK_PCI_LPBACK R232 2 1 22_0402_5% CLK_PCI0 H49 CLKOUT_PCI0 OC3# / GPIO42 C16 USB_OC3# 5 Port 10 & 11 B
CLK_PCI_LPC R233 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
40 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
CLK_LPC_DEBUG1 R234 1 2 22_0402_5% CLK_PCI3 J48 A16 USB_OC5#
41 CLK_LPC_DEBUG1 CLKOUT_PCI2 OC5# / GPIO9
K42 CLKOUT_PCI3 OC6# / GPIO10 D14 USB_OC6# 6 Port 12 & 13
PR-8 @ H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14
+3V_PCH +3VS
PANTHER-POINT_FCBGA989

1
R445 R444
0_0402_5% @ 0_0402_5%
1 @ 2
+3VS R236 0_0402_5%
2

2
PCH_GPIO4 8.2K_0402_5% 1 2 R784 +3VS PR-8 +3VS
PCI_PIRQB# 8.2K_0402_5% 1 2 R785
2

PCI_PIRQD# 8.2K_0402_5% 1 2 R786 @ C168 C169 DIS@

PCI_PIRQC# 8.2K_0402_5% 1 2 R787 R238 1 2 1 2
10K_0402_5% 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
5

5
U8 U9
DIS@ PCH_PLTRST#
B 2

P
VCC
1

1 PCH_PLTRST# 2 1 R240 4
IN1 20 DGPU_RST# Y
PCH_WAN_RADIO_OFF# 8.2K_0402_5% 1 2 R788 4 100_0402_5% 1 DGPU_HOLD_RST#
5,32,36,40,41 PLT_RST# OUT A

G
PCI_PIRQA# 8.2K_0402_5% 1 2 R789 2
GND

IN2

1
ODD_DA# 8.2K_0402_5% 1 2 R790 DIS@ NC7SZ08P5X_NL_SC70-5

3
PCH_GPIO5 8.2K_0402_5% 1 2 R791 R241
100K_0402_5%
3

MC74VHC1G08DFT2G_SC70-5 DIS@

2
PCH_GPIO52 8.2K_0402_5% 1 2 R792
A PCH_GPIO2 8.2K_0402_5% 1 2 R793 A
1 @ 2
DGPU_HOLD_RST# 1 R244 2 10K_0402_5% R235 0_0402_5%
@
1 R443 2 10K_0402_5%
1

DGPU_PWR_EN
Security Classification Compal Secret Data Compal Electronics, Inc.
1 R288 2 10K_0402_5% R243
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
@ 100K_0402_5%
SCHEMATIC A8222
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 15 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS

CRT_DET 1 @ 2 10K_0402_5%
R245 U3F
ODD_DETECT# 1 2 200K_0402_5%
R246 CRT_DET T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 31
PCH_GPIO16 1 2 10K_0402_5% DMI Termination Voltage
R247 PCH_GPIO1 A42 B41 PCH_GPIO69 @ T27 PAD
PCH_BT_ON TACH1 / GPIO1 TACH5 / GPIO69
1 2 10K_0402_5% Set to Vcc when HIGH
R248 USB30_SMI# H36 C41 GPIO70 @ T28 PAD +3VS NV_CLE
KB_RST# 36 USB30_SMI# TACH2 / GPIO6 TACH6 / GPIO70
1 2 10K_0402_5% Set to Vss when LOW
R249 40 EC_SCI# EC_SCI# E38 A40 GPIO71 @ T29 PAD
TACH3 / GPIO7 TACH7 / GPIO71

2
D PCH_GPIO48 1 2 10K_0402_5% D
R250 EC_SMI# C10 R251 +1.8VS
40 EC_SMI# GPIO8
PCH_GPIO22 1 @ 2 10K_0402_5% 10K_0402_5%
R252 C4 LAN_PHY_PWR_CTRL / GPIO12

1
ODD_EN# 1 2 10K_0402_5%

1
R253 EC_LID_OUT# 1 2 PCH_LID_SW_IN# G2 P4 GATEA20
40 EC_LID_OUT# GPIO15 A20GATE GATEA20 40
DGPU_PWROK 1 2 10K_0402_5% 0_0402_5% R579 R254
R255 AU16 2.2K_0402_5%
PR-7 PCH_GPIO16 PECI
U2

2
PCH_GPIO22 SATA4GP / GPIO16
2 1 10K_0402_5% RCIN# P5 KB_RST# 40
DF_TVS 2 1 H_SNB_IVB# 5
R812 1K_0402_5% R256

GPIO
DGPU_PWROK D40 AY11
40 DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5

CPU/MISC
CLOSE TO THE BRANCHING POINT
PCH_GPIO22 T5 AY10 H_THERMTRIP#_C 1 2 H_THERMTRIP# H_THERMTRIP# 5
SCLOCK / GPIO22 THRMTRIP# 390_0402_5% R258
1
E8 T14 @
GPIO24 INIT3_3V# 0.1U_0402_16V7K
+3VS DS_WAKE# 1 @ 2 PCH_GPIO27 E16 AY1 DF_TVS C151
40 DS_WAKE# GPIO27 DF_TVS 2
R804 0_0402_5%
PCH_GPIO28 P8 @ 1 2 H_CPUPWRGD
PCH_GPIO69 GPIO28 C170 100P_0402_50V8J
1 2 TS_VSS1 AH8
10K_0402_5% R807 PCH_BT_ON K1
41 PCH_BT_ON STP_PCI# / GPIO34
2 1 PCH_GPIO1 AK11
10K_0402_5% R257 TS_VSS2
K4 GPIO35
1 @ 2 PCH_GPIO37
TS_VSS3 AH10 Reserve for EMI please close to UH1
10K_0402_5% R259 ODD_DETECT# V8
31 ODD_DETECT# SATA2GP / GPIO36
2 1 PCH_GPIO38 AK10
10K_0402_5% R260 PCH_GPIO37 TS_VSS4
M5 SATA3GP / GPIO37
2 1 PCH_GPIO39
10K_0402_5% R261 PCH_GPIO38 N2 P37 @ T30 PAD
PCH_GPIO49 SLOAD / GPIO38 NC_1
1 2
10K_0402_5% R262 PCH_GPIO39 M3
C USB30_SMI# SDATAOUT0 / GPIO39 C
2 1
10K_0402_5% R263 PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
2 R265 1 0_0402_5% PCH_GPIO49 V3 BG48
30 CABC_SAVING SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
R264 2 1 PCH_GPIO37 @
100K_0402_5% HDD2_DETECT# D6 BH3
GPIO57 VSS_NCTF_17

VSS_NCTF_18 BH47

A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

+3VALW
A45 VSS_NCTF_3 VSS_NCTF_21 BJ45

NCTF
1 @ 2 DS_WAKE# A46 BJ46
10K_0402_5% R805 VSS_NCTF_4 VSS_NCTF_22
A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

1 2 PCH_GPIO27 A6 BJ6
@ R266 10K_0402_5% VSS_NCTF_6 VSS_NCTF_24
B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

+3V_PCH
BD49 VSS_NCTF_10 VSS_NCTF_28 D49

BE1 VSS_NCTF_11 VSS_NCTF_29 E1

PCH_GPIO28 1 2 10K_0402_5%
R268 BE49 E49
B VSS_NCTF_12 VSS_NCTF_30 B
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
HDD2_DETECT# 1 2 10K_0402_5%
R269 BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PCH_LID_SW_IN# 1 2 1K_0402_5% PANTHER-POINT_FCBGA989

R270
EC_SMI# 1 2 10K_0402_5% trace out
R271
GPIO28 trace out
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable
1 2 PCH_GPIO28

@ R272 1K_0402_5%~D

+3VS
2

High: CRT Plugged R273

10K_0402_5%
A A
1

CRT_DET
1

D
2 Q12
30 CRT_DET#
G 2N7002KW 1N SOT323-3
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 16 of 61
5 4 3 2 1
 5 4 3 2 1

PCH Power Rail Table

+1.05VS Refer to CPU EDS R1.5
U3G POWER +3VS S0 Iccmax
PJP802 Voltage Rail Voltage Current (A)
1300mA L1

0.01U_0402_16V7K

0.1U_0402_16V7K
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC BLM18PG181SN1_0603
AC23 VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
PAD-OPEN 4x4m 1 1 1 1 AD21

CRT
VCCCORE[3]

C171

C172
AD23 U47 C173
@ VCCCORE[4] VSSADAC

C175

C176

C177
C174 AF21 10U_0805_6.3VAM V5REF 5 0.001

VCC CORE
10U_0805_6.3VAM VCCCORE[5] 2 2 2
AF23 VCCCORE[6]
D 2 2 2 2 +3VS D
AG21 VCCCORE[7]
AG23 VCCCORE[8]
V5REF_Sus 5 0.001
AG24 VCCCORE[9] 1mAVCCALVDS AK36
AG26 VCCCORE[10]
AG27 AK37 +1.8VS Vcc3_3 3.3 0.228
VCCCORE[11] VSSALVDS
AG29 VCCCORE[12]
AJ23 Near AP43 L2
VCCCORE[13]

LVDS
AJ26 AM37 +VCCTX_LVDS 2 1 VccADAC 3.3 0.001
VCCCORE[14] VCCTX_LVDS[1]

22U_0805_6.3V6M
AJ27 C178 1 1 1 0.1UH_MLF1608DR10KT_10%_1608
+1.05VS VCCCORE[15] 0.01U_0402_16V7K C180
AJ29 AM38 0.1uH inductor, 200mA
VCCCORE[16] VCCTX_LVDS[2] C179
AJ31 VCCCORE[17]
VccADPLLA 1.05 0.075
40mAVCCTX_LVDS[3] AP36 0.01U_0402_16V7K
2 2 2

VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.075

AN19 VCCIO[28]
VccCore 1.05 1.3
BJ22 VCCAPLLEXP

VCC3_3[6] V33 +3VS VccDMI 1.05 0.042

HVCMOS
AN16 VCCIO[15]
1
AN17 VCCIO[16]
VccIO 1.05 3.709
+1.05VS V34 C182
VCC3_3[7]
0.1U_0402_16V7K
PR-7 2 VccASW 1.05 0.903
AN21 VCCIO[17]
AN26 +1.5VS
VCCIO[18]
1

VccSPI 3.3 0.01

R274 R275 AN27 3709mA AT16
0_0805_5% +1.05VS_VCC_EXP VCCIO[19] VCCVRM[3] PR-7
0_0805_5%
AP21 +VCCP_VCCDMI +VCCP VccDSW 3.3 0.001
C VCCIO[20] R276 C
2

+1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2

VCCIO[21] VCCDMI[1]
1 VccDFTERM 1.8 0.002

DMI
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 AP24 0_0805_5%
VCCIO[22]

VCCIO
R387 C183
C185

C186

C187

C188

C184 AP26 75mA VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI 1 2 +1.05VS 2 VccRTC 3.3 6 uA

10U_0805_6.3VAM VCCIO[23] 1U_0402_6.3V6K
2 2 2 2 2 1
AT24 0_0805_5%
VCCIO[24] C189 PR-7 VccSus3_3 3.3 0.065
1U_0402_6.3V6K
+3VS 2
AN33 VCCIO[25]
VccSusHDA 3.3 / 1.5 0.01
AN34 VCCIO[26] VCCDFTERM[1] AG16

VccVRM 1.8 / 1.5 0.167

BH29 VCC3_3[3] 2mA VCCDFTERM[2] AG17 +1.8VS

DFT / SPI
1

0.1U_0402_16V7K
C190 +1.5VS VccCLKDMI 1.05 0.075
VCCDFTERM[3] AJ16 1
0.1U_0402_16V7K
2

C191
AP16 VCCVRM[2]
VccSSC 1.05 0.095
VCCDFTERM[4] AJ17
2
BG6 VccAFDIPLL
VccDIFFCLKN 1.05 0.055

+1.05VS AP17 @ VccALVDS 3.3 0.001

VCCIO[27] +3V_VCCPSPI
10mA VCCSPI V1 2 1
FDI

+3V_PCH
R278 0_0603_5%
+VCCP_VCCDMI AU20 VCCDMI[2] 1 VccTX_LVDS 1.8 0.04
2 1 +3VS
C193 R279 0_0603_5%
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2
PR-7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 17 of 61
5 4 3 2 1
 5 4 3 2 1

+1.05VS

2 @ 1 +VCCACLK
+3V_PCH PR-7 R280 0_0603_5%
U3J POWER
1 2
R281 0_0603_5% 1 AD49 N26 +1.05VS
+3VALW VCCACLK VCCIO[29]
C194 P26 1
0.1U_0402_16V7K +VCCPDSW VCCIO[30]
1 2 T16 VCCDSW3_33mA
D R290 0_0603_5% 2 C195 D
VCCIO[31] P28
1U_0402_6.3V6K
@ 2
+PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
1
VCCIO[33] T29
@ C196 +3VS_VCC_CLKF33 T38
0.1U_0402_16V7K VCC3_3[5]
2
VCCSUS3_3[7] T23 +3V_PCH
+1.05VS 119mA

0.1U_0402_16V7K
BH23 VCCAPLLDMI2
VCCSUS3_3[8] T24 1 +3V_PCH +5V_PCH +3V_PCH

0.1U_0402_16V7K
AL29 VCCIO[14]

C198
VCCSUS3_3[9] V23 1

USB

2
2

C199
+VCCSUS1 AL24 V24 +VCCA_USBSUS
DCPSUS[3] VCCSUS3_3[10]

1U_0402_6.3V6K
1 R282 D3
@ 2
VCCSUS3_3[6] P24 1 10_0402_5% RB751V40_SC76-2

@ C201
C200
1U_0402_6.3V6K AA19

1
2 VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26 +1.05VS
903mA 2
AA21 VCCASW[2] 1

AA24 M26 +PCH_V5REF_SUS C202

VCCASW[3] 1mA V5REF_SUS 0.1U_0603_25V7K
1 1 +3V_PCH 2

0.1U_0402_16V7K
AA26

Clock and Miscellaneous

C203 C204 VCCASW[4] +VCCA_USBSUS
DCPSUS[4] AN23 1
22U_0805_6.3V6M 22U_0805_6.3V6M AA27
2 2 VCCASW[5]

C205
VCCSUS3_3[1] AN24
AA29 VCCASW[6] 2
+1.05VS +5VS +3VS
AA31 VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF

2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C C
1 1 1
AC27 R283 D4
VCCASW[9]
C206

C207

C208
VCCSUS3_3[2] N20 +3V_PCH 10_0402_5% RB751V40_SC76-2

PCI/GPIO/LPC
AC29 VCCASW[10] 1
2 2 2
N22

1
VCCSUS3_3[3] C209 +PCH_V5REF_RUN
AC31 VCCASW[11] 1U_0402_6.3V6K +3VS
VCCSUS3_3[4] P20 1
2
AD29 VCCASW[12]
P22 C210
VCCSUS3_3[5] 1U_0603_10V6K
AD31 VCCASW[13] 1 2
+3VS C211
W21 VCCASW[14] VCC3_3[1] AA16
0.1U_0402_16V7K
R289 2 +3VS
W23 VCCASW[15] VCC3_3[8] W16
1 2 +3VS_VCC_CLKF33
10U_0603_6.3V6M

1U_0402_6.3V6K

1 1 W24 VCCASW[16] VCC3_3[4] T34

0_0805_5% 1
C212

C213

W26 VCCASW[17]
@ C214
PR-7 2 2 +3VS 0.1U_0402_16V7K
W29 VCCASW[18] 2
W31 VCCASW[19] VCC3_3[2] AJ2
+1.05VS_SATA3 PR-7
1
W33 R284
VCCASW[20] C215
VCCIO[5] AF13 2 1 +1.05VS
0.1U_0402_16V7K 1
+1.05VS +VCCRTCEXT 2 0_0805_5%
N16 DCPRTC
1 +1.5VS AH13 C216
@ +1.05VM_VCCSUS VCCIO[12] 1U_0402_6.3V6K
2 1
R285 0_0603_5% C217 +1.05VS_SATA3 2
Y49 VCCVRM[4] VCCIO[13] AH14
0.1U_0402_16V7K
2
B +1.05VS AF14 B
+1.05VS_VCCA_A_DPL VCCIO[6]
BD47 VCCADPLLA75mA

SATA
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 +1.5VS
VCCADPLLB75mA
1
C218 AF11
VCCVRM[1] +1.05VS_VCC_SATA PR-7
AF17 VCCIO[7]
+1.05VS 1U_0402_6.3V6K +1.05VS_VCCDIFFCLKN AF33 R286
2 VCCDIFFCLKN[1] +1.05VS_VCC_SATA
18mil AF34 VCCDIFFCLKN[2]
55mA VCCIO[2] AC16 2 1 +1.05VS
2 1 +1.05VS_VCCDIFFCLKN AG34 0_0805_5%
VCCDIFFCLKN[3]

1U_0402_6.3V6K
R287 0_0603_5% 1 AC17 1
VCCIO[3]
18mil

C221
PR-7 C220 AG33 AD17
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
+1.05VS 2 2 +1.05VS
+VCCSST V16 DCPSST
1 1 +1.05VM_VCCSUS
C223 1 T17 T21
C222 0.1U_0402_16V7K @ DCPSUS[1] VCCASW[22]
V19 DCPSUS[2]
1U_0402_6.3V6K C224
MISC

+VCCP 2 2 1U_0402_6.3V6K
VCCASW[23] V21
2
CPU
0.1U_0402_16V7K

0.1U_0402_16V7K

BJ8 V_PROC_IO
1mA
1 1 1 VCCASW[21] T19
+RTCVCC
C226

C227

C225
4.7U_0603_6.3V6K PR-7
2 2 2 +VCCSUSHDA
A22 P32 1 2
RTC

VCCRTC 10mA VCCSUSHDA +3V_PCH

HDA
0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

0.1U_0402_16V7K R291 0_0402_5%

1 1 1 1

150_0402_1%
L8 PANTHER-POINT_FCBGA989 If it support 3.3V audio signals

1
C228

C229

C230

C231

A 10UH_LBR2012T100M_20%~D POP:RH12 (0ohm) A

1 2 +1.05VS_VCCA_A_DPL
+1.05VS 2 2 2 2
R292
@
If it support 1.5V audio signals
220U_B2_2.5VM_R35M

1 2 +1.05VS_VCCA_B_DPL POP:RH12 (180 ohm)/RH13 (150 ohm)

2
220U_B2_2.5VM_R35M

L9
1U_0402_6.3V6K

1U_0402_6.3V6K

10UH_LBR2012T100M_20%~D 1 1
1 1
+ Security Classification Compal Secret Data Compal Electronics, Inc.
C232

+
C233
C234

C235

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 18 of 61
5 4 3 2 1
 5 4 3 2 1

U3I

AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
U3H AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
D D
H5 VSS[0] B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7
AA17 VSS[1] VSS[80] AK38 B19 VSS[165] VSS[265] L18
AA2 VSS[2] VSS[81] AK4 B23 VSS[166] VSS[266] L2
AA3 VSS[3] VSS[82] AK42 B27 VSS[167] VSS[267] L20
AA33 VSS[4] VSS[83] AK46 B31 VSS[168] VSS[268] L26
AA34 VSS[5] VSS[84] AK8 B35 VSS[169] VSS[269] L28
AB11 VSS[6] VSS[85] AL16 B39 VSS[170] VSS[270] L36
AB14 VSS[7] VSS[86] AL17 B7 VSS[171] VSS[271] L48
AB39 VSS[8] VSS[87] AL19 F45 VSS[172] VSS[272] M12
AB4 VSS[9] VSS[88] AL2 BB12 VSS[173] VSS[273] P16
AB43 VSS[10] VSS[89] AL21 BB16 VSS[174] VSS[274] M18
AB5 VSS[11] VSS[90] AL23 BB20 VSS[175] VSS[275] M22
AB7 VSS[12] VSS[91] AL26 BB22 VSS[176] VSS[276] M24
AC19 VSS[13] VSS[92] AL27 BB24 VSS[177] VSS[277] M30
AC2 VSS[14] VSS[93] AL31 BB28 VSS[178] VSS[278] M32
AC21 VSS[15] VSS[94] AL33 BB30 VSS[179] VSS[279] M34
AC24 VSS[16] VSS[95] AL34 BB38 VSS[180] VSS[280] M38
AC33 VSS[17] VSS[96] AL48 BB4 VSS[181] VSS[281] M4
AC34 VSS[18] VSS[97] AM11 BB46 VSS[182] VSS[282] M42
AC48 VSS[19] VSS[98] AM14 BC14 VSS[183] VSS[283] M46
AD10 VSS[20] VSS[99] AM36 BC18 VSS[184] VSS[284] M8
AD11 VSS[21] VSS[100] AM39 BC2 VSS[185] VSS[285] N18
AD12 VSS[22] VSS[101] AM43 BC22 VSS[186] VSS[286] P30
AD13 VSS[23] VSS[102] AM45 BC26 VSS[187] VSS[287] N47
AD19 VSS[24] VSS[103] AM46 BC32 VSS[188] VSS[288] P11
AD24 VSS[25] VSS[104] AM7 BC34 VSS[189] VSS[289] P18
AD26 VSS[26] VSS[105] AN2 BC36 VSS[190] VSS[290] T33
AD27 VSS[27] VSS[106] AN29 BC40 VSS[191] VSS[291] P40
AD33 VSS[28] VSS[107] AN3 BC42 VSS[192] VSS[292] P43
AD34 VSS[29] VSS[108] AN31 BC48 VSS[193] VSS[293] P47
AD36 VSS[30] VSS[109] AP12 BD46 VSS[194] VSS[294] P7
C C
AD37 VSS[31] VSS[110] AP19 BD5 VSS[195] VSS[295] R2
AD38 VSS[32] VSS[111] AP28 BE22 VSS[196] VSS[296] R48
AD39 VSS[33] VSS[112] AP30 BE26 VSS[197] VSS[297] T12
AD4 VSS[34] VSS[113] AP32 BE40 VSS[198] VSS[298] T31
AD40 VSS[35] VSS[114] AP38 BF10 VSS[199] VSS[299] T37
AD42 VSS[36] VSS[115] AP4 BF12 VSS[200] VSS[300] T4
AD43 VSS[37] VSS[116] AP42 BF16 VSS[201] VSS[301] W34
AD45 VSS[38] VSS[117] AP46 BF20 VSS[202] VSS[302] T46
AD46 VSS[39] VSS[118] AP8 BF22 VSS[203] VSS[303] T47
AD8 VSS[40] VSS[119] AR2 BF24 VSS[204] VSS[304] T8
AE2 VSS[41] VSS[120] AR48 BF26 VSS[205] VSS[305] V11
AE3 VSS[42] VSS[121] AT11 BF28 VSS[206] VSS[306] V17
AF10 VSS[43] VSS[122] AT13 BD3 VSS[207] VSS[307] V26
AF12 VSS[44] VSS[123] AT18 BF30 VSS[208] VSS[308] V27
AD14 VSS[45] VSS[124] AT22 BF38 VSS[209] VSS[309] V29
AD16 VSS[46] VSS[125] AT26 BF40 VSS[210] VSS[310] V31
AF16 VSS[47] VSS[126] AT28 BF8 VSS[211] VSS[311] V36
AF19 VSS[48] VSS[127] AT30 BG17 VSS[212] VSS[312] V39
AF24 VSS[49] VSS[128] AT32 BG21 VSS[213] VSS[313] V43
AF26 VSS[50] VSS[129] AT34 BG33 VSS[214] VSS[314] V7
AF27 VSS[51] VSS[130] AT39 BG44 VSS[215] VSS[315] W17
AF29 VSS[52] VSS[131] AT42 BG8 VSS[216] VSS[316] W19
AF31 VSS[53] VSS[132] AT46 BH11 VSS[217] VSS[317] W2
AF38 VSS[54] VSS[133] AT7 BH15 VSS[218] VSS[318] W27
AF4 VSS[55] VSS[134] AU24 BH17 VSS[219] VSS[319] W48
AF42 VSS[56] VSS[135] AU30 BH19 VSS[220] VSS[320] Y12
AF46 VSS[57] VSS[136] AV16 H10 VSS[221] VSS[321] Y38
AF5 VSS[58] VSS[137] AV20 BH27 VSS[222] VSS[322] Y4
AF7 VSS[59] VSS[138] AV24 BH31 VSS[223] VSS[323] Y42
AF8 VSS[60] VSS[139] AV30 BH33 VSS[224] VSS[324] Y46
AG19 VSS[61] VSS[140] AV38 BH35 VSS[225] VSS[325] Y8
AG2 VSS[62] VSS[141] AV4 BH39 VSS[226] VSS[328] BG29
B B
AG31 VSS[63] VSS[142] AV43 BH43 VSS[227] VSS[329] N24
AG48 VSS[64] VSS[143] AV8 BH7 VSS[228] VSS[330] AJ3
AH11 VSS[65] VSS[144] AW14 D3 VSS[229] VSS[331] AD47
AH3 VSS[66] VSS[145] AW18 D12 VSS[230] VSS[333] B43
AH36 VSS[67] VSS[146] AW2 D16 VSS[231] VSS[334] BE10
AH39 VSS[68] VSS[147] AW22 D18 VSS[232] VSS[335] BG41
AH40 VSS[69] VSS[148] AW26 D22 VSS[233] VSS[337] G14
AH42 VSS[70] VSS[149] AW28 D24 VSS[234] VSS[338] H16
AH46 VSS[71] VSS[150] AW32 D26 VSS[235] VSS[340] T36
AH7 VSS[72] VSS[151] AW34 D30 VSS[236] VSS[342] BG22
AJ19 VSS[73] VSS[152] AW36 D32 VSS[237] VSS[343] BG24
AJ21 VSS[74] VSS[153] AW40 D34 VSS[238] VSS[344] C22
AJ24 VSS[75] VSS[154] AW48 D38 VSS[239] VSS[345] AP13
AJ33 VSS[76] VSS[155] AV11 D42 VSS[240] VSS[346] M14
AJ34 VSS[77] VSS[156] AY12 D8 VSS[241] VSS[347] AP3
AK12 VSS[78] VSS[157] AY22 E18 VSS[242] VSS[348] AP1
AK3 VSS[79] VSS[158] AY28 E26 VSS[243] VSS[349] BE16
G18 VSS[244] VSS[350] BC16
PANTHER-POINT_FCBGA989 G20 BG28
VSS[245] VSS[351]
G26 VSS[246] VSS[352] BJ28
G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 19 of 61
5 4 3 2 1
 A B C D E

The boot voltage is 1.0V +3VSG

U10A GPIO I/O USAGE
PCIE_CTX_C_GRX_P0 AN12 Part 1 of 7
PCIE_CTX_C_GRX_N0 PEX_RX0 VID_4
AM12 PEX_RX0_N GPIO0 P6 GPIO0 O GPU_VID4

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
PCIE_CTX_C_GRX_P1 AN14 M3 VID_3
PCIE_CTX_C_GRX_N1 PEX_RX1 GPIO1
AM14 PEX_RX1_N GPIO2 L6
PCIE_GTX_C_CRX_P[0..15] PCIE_CTX_C_GRX_P2
4 PCIE_GTX_C_CRX_P[0..15]
PCIE_CTX_C_GRX_N2
AP14 PEX_RX2 GPIO3 P5 GPIO1 O GPU_VID3
AP15 PEX_RX2_N GPIO4 P7

@ 1

@ 1

@ 1

2 DIS@ 1

@ 1

2 DIS@ 1
PCIE_CTX_C_GRX_P3 AN15 L7 VID_1
PCIE_GTX_C_CRX_N[0..15] PCIE_CTX_C_GRX_N3 PEX_RX3 GPIO5 VID_2
4 PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_P4
AM15 PEX_RX3_N GPIO6 M7
+3VSG GPIO2 O LCD_BL_PWM
AN17 PEX_RX4 GPIO7 N8
PCIE_CTX_C_GRX_N4 AM17 M1 R299 2 DIS@ 1 10K_0402_5%
PEX_RX4_N GPIO8

R293

R294

R295

R296

R297

R298
PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_P5 R300 2 DIS@ 1 10K_0402_5% GPU_GPIO16 R301 @ 2 0_0402_5%
4 PCIE_CTX_C_GRX_P[0..15] AP17 M2 1 GPIO3 O LCD_VCC

2
1 PCIE_CTX_C_GRX_N5 PEX_RX5 GPIO9 1
AP18 PEX_RX5_N GPIO10 L1
PCIE_CTX_C_GRX_P6 AN18 M5 VID_0

GPIO
PCIE_CTX_C_GRX_N[0..15] PCIE_CTX_C_GRX_N6 PEX_RX6 GPIO11 ACIN_BUF_VGA VID_0 R302 0_0402_5%
4 PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P7
AM18 PEX_RX6_N GPIO12 N3
VID_5 VID_1 R303
1 2
0_0402_5%
GPU_VID0 53 GPIO4 O LCD_BLEN
AN20 PEX_RX7 GPIO13 M4 1 2 GPU_VID1 53
PCIE_CTX_C_GRX_N7 AM20 N4 VID_2 R304 1 2 0_0402_5%
PEX_RX7_N GPIO14 GPU_VID2 53
PCIE_CTX_C_GRX_P8 AP20 P2 VID_3 R305 1 2 0_0402_5% GPIO5 O GPU_VID1
PEX_RX8 GPIO15 GPU_VID3 53
PCIE_CTX_C_GRX_N8 AP21 R8 GPU_GPIO16 VID_4 R306 1 2 0_0402_5%
PEX_RX8_N GPIO16 GPU_VID4 53
PCIE_CTX_C_GRX_P9 AN21 M6 VID_5 R307 1 2 0_0402_5%
PEX_RX9 GPIO17 GPU_VID5 53
PCIE_CTX_C_GRX_N9 AM21 R1 GPIO6 O GPU_VID2
PEX_RX9_N GPIO18

R308

R309

R310

R311

R312

R313
PCIE_CTX_C_GRX_P10 AN23 P3 PR-7
PEX_RX10 GPIO19

DIS@ 1

DIS@ 1

DIS@ 1

@ 1

DIS@ 1

@ 1
PCIE_CTX_C_GRX_N10 AM23 P4
PCIE_CTX_C_GRX_P11 PEX_RX10_N GPIO20
PCIE_CTX_C_GRX_N11
AP23 PEX_RX11 GPIO21 P1 GPIO7 O 3D Vision
AP24 PEX_RX11_N
PCIE_CTX_C_GRX_P12 AN24 PEX_RX12

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
PCIE_CTX_C_GRX_N12 AM24 GPIO8 I/O OVERT

2
PCIE_CTX_C_GRX_P13 PEX_RX12_N
AN26 PEX_RX13
PCIE_CTX_C_GRX_N13 AM26
PCIE_CTX_C_GRX_P14 PEX_RX13_N
PCIE_CTX_C_GRX_N14
AP26 PEX_RX14 GPIO9 I/O ALERT
AP27 PEX_RX14_N
PCIE_CTX_C_GRX_P15 AN27 AK9
PCIE_CTX_C_GRX_N15 PEX_RX15 DACA_RED
AM27 PEX_RX15_N DACA_GREEN AL10 GPIO10 O MEM_VREF_CTL
DACA_BLUE AL9

DACs
PCIE_GTX_C_CRX_P0 AK14 MEM_VDD_CTL(PES)
PCIE_GTX_C_CRX_N0 PEX_TX0
PCIE_GTX_C_CRX_P1
AJ14 PEX_TX0_N DACA_HSYNC AM9
+3VSG GPIO11 O
PCIE_GTX_C_CRX_N1
AH14 PEX_TX1 DACA_VSYNC AN9 GPU_VID0(Real N13P)
AG14 PEX_TX1_N
PCIE_GTX_C_CRX_P2 AK15 R314 DIS@
PCIE_GTX_C_CRX_N2 PEX_TX2
AJ15 PEX_TX2_N DACA_VDD AG10 2 1 10K_0402_5% GPIO12 I PWR_LEVEL

PCI EXPRESS
PCIE_GTX_C_CRX_P3 AL16 AP9
PEX_TX3 DACA_VREF

1
PCIE_GTX_C_CRX_N3 AK16 AP8
PCIE_GTX_C_CRX_P4 PEX_TX3_N DACA_RSET R315
AK17 PEX_TX4 GPIO13 O THERM_LOAD_STEP_DOWN
2 PCIE_GTX_C_CRX_N4 DIS@ 2
AJ17 PEX_TX4_N

5
PCIE_GTX_C_CRX_P5 AH17 10K_0402_5% U11
PCIE_GTX_C_CRX_N5 PEX_TX5
AG17 2 GPIO14 I HPD_AB

P
VGA_BUF# 40

2
PCIE_GTX_C_CRX_P6 PEX_TX5_N ACIN_BUF_VGA B
AK18 PEX_TX6 4 Y
PCIE_GTX_C_CRX_N6 AJ18 1 ACIN_BUF 53
PEX_TX6_N A

G
PCIE_GTX_C_CRX_P7 AL19 GPIO15 I HPD_C
PEX_TX7

2
PCIE_GTX_C_CRX_N7 AK19 R4 VGA_DDC_CLK @ NC7SZ08P5X_NL_SC70-5

3
PCIE_GTX_C_CRX_P8 PEX_TX7_N I2CA_SCL VGA_DDC_DATA R428
AK20 PEX_TX8 I2CA_SDA R5
PCIE_GTX_C_CRX_N8 AJ20 0_0402_5% GPIO16 O THERM_LOAD_STEP_UP
PCIE_GTX_C_CRX_P9 PEX_TX8_N I2CB_SCL
AH20 PEX_TX9 I2CB_SCL R7
PCIE_GTX_C_CRX_N9 AG20 R6 I2CB_SDA PR-7
PEX_TX9_N I2CB_SDA

1
PCIE_GTX_C_CRX_P10 GPIO17 I HPD_D

I2C
AK21 PEX_TX10 2 1
PCIE_GTX_C_CRX_N10 AJ21 R2 VGA_LCD_CLK DIS@ D5
PCIE_GTX_C_CRX_P11 PEX_TX10_N I2CC_SCL VGA_LCD_DATA CH751H-40PT_SOD323-2
AL22 PEX_TX11 I2CC_SDA R3
PCIE_GTX_C_CRX_N11 AK22 GPIO18 I HPD_E
PCIE_GTX_C_CRX_P12 PEX_TX11_N I2CS_SCL
AK23 PEX_TX12 I2CS_SCL T4
PCIE_GTX_C_CRX_N12 AJ23 T3 I2CS_SDA +3VSG
PCIE_GTX_C_CRX_P13 PEX_TX12_N I2CS_SDA
AH23 PEX_TX13 under GPU GPIO19 I HPD_F
PCIE_GTX_C_CRX_N13 AG23 VGA_DDC_CLK R316 1 DIS@ 2 2.2K_0402_5%
PCIE_GTX_C_CRX_P14 AK24
PEX_TX13_N close to ball : AD8 VGA_DDC_DATA R317 1 DIS@ 2 2.2K_0402_5%
PCIE_GTX_C_CRX_N14 PEX_TX14
PCIE_GTX_C_CRX_P15
AJ24 PEX_TX14_N C236 I2CB_SCL R318 1 DIS@
GPIO20 Reserved
AL25 PEX_TX15 1 2 2 2.2K_0402_5%
PCIE_GTX_C_CRX_N15 AK25 DIS@ 0.1U_0402_16V4Z I2CB_SDA R319 1 DIS@ 2 2.2K_0402_5%
PEX_TX15_N
GPIO21 Reserved
PLLVDD AD8 +PLLVDD VGA_LCD_CLK R320 1 DIS@ 2 2.2K_0402_5%
AJ11 VGA_LCD_DATA R321 1 DIS@ 2 2.2K_0402_5%
PEX_WAKE_N
SP_PLLVDD AE8 +GPU_PLLVDD 1 @ 2 GPIO22 I/O SLI_RASTER_SYNC
+3VSG 1 DIS@ 2 13 CLK_PCIE_VGA AL13 PEX_REFCLK
R322 0_0402_5% I2CS_SCL R324 1 DIS@ 2 2.2K_0402_5%
R323 10K_0402_5% AK13 AD7 I2CS_SDA R325 1 DIS@ 2 2.2K_0402_5%
13 CLK_PCIE_VGA# PEX_REFCLK_N VID_PLLVDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PEG_CLKREQ# GPIO23 O SLI_SWAPRDY
CLK

AK12 PEX_CLKREQ_N

DIS@ C237

DIS@ C238

DIS@ C239
1 1 1
PEX_TSTCLK_OUT+ AJ26 H3 XTALIN
3 PEX_TSTCLK_OUT- PEX_TSTCLK_OUT XTAL_IN XTALOUT 3
2
R326 @
1
200_0402_1%
AK26 PEX_TSTCLK_OUT_N XTAL_OUT H2 GPIO24
XTAL_OUTBUFF 2 2 2
15 DGPU_RST# AJ12 PEX_RST_N XTAL_OUTBUFF J4
2 1 PEX_TREMP AP29 H1 XTAL_SSIN
R327 DIS@ 2.49K_0402_1% PEX_TERMP XTAL_SSIN 1

1
+3VSG

R328 10K_0402_5%
R329
under GPU
close to ball : AE8,AD7

2
N13P-PES-A1_FCBGA908 10K_0402_5% DIS@ Q5A
XTALOUT @ XTALIN @ DIS@
2

R330 1M_0402_5% +1.05VSG I2CS_SCL 1 6 PCH_SMLCLK 13,40

60mA L10 DIS@
27MHZ_10PF_7V27000050 +PLLVDD 1 2 2N7002KDWH_SOT363-6

22U_0805_6.3V6M
3 1 BLM18PG300SN1D_2P GEL@
3 1

DIS@ C240
GND GND 1
1 1 SPEC: 30ohm (ESR:0.05) 1 2
12P_0402_50V8J Y3 12P_0402_50V8J L10= 30ohm R742 GS@ 0_0402_5%
C241 DIS@ 4 2 C242
DIS@ DIS@ 2
2 2

+3VSG

150mA L11 DIS@ Q5B

5
+3VSG +GPU_PLLVDD 1 2
+3V_PCH

22U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6K
0.1U_0402_16V4Z BLM18PG181SN1D_2P
DIS@ C243

DIS@ C244

DIS@ C245

DIS@ C246
1 1 1 1 I2CS_SDA 4 3 PCH_SMLDATA 13,40
1

SPEC: 180ohm (ESR:0.2)

1

DIS@ L11= 180ohm 2N7002KDWH_SOT363-6

R332 R331 GEL@
10K_0402_5% 10K_0402_5% 2 2 2 2
4 4
1 2
2

R741 GS@ 0_0402_5%

2

Q13
2

2N7002KW 1N SOT323-3 PR-7

G

DIS@
PEG_CLKREQ#_R 1 3 1 2 PEG_CLKREQ#
13 PEG_CLKREQ#_R
R333 0_0402_5%
D

S
1

@ @ Security Classification Compal Secret Data Compal Electronics, Inc.

for safe R334 R335 2011/08/23 2012/12/31 Title
2.2K_0402_5% 2.2K_0402_5%
Issued Date Deciphered Date
SCHEMATIC A8222
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 20 of 61
A B C D E
 A

VRAM Interface 25 MDA[15..0]

25 MDA[31..16]
MDA[15..0]

MDA[31..16] 27 MDC[15..0]
MDC[15..0]

MDC[31..16]
MDA[47..32] 27 MDC[31..16]
26 MDA[47..32] MDC[47..32]
MDA[63..48] 28 MDC[47..32]
26 MDA[63..48] MDC[63..48]
28 MDC[63..48]

U10B U10C
CMDA[30..0] 25,26 CMDC[30..0] 27,28
Part 2 of 7 Part 3 of 7
MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0
MDA1 FBA_D0 FBA_CMD0 CMDA1 MDC1 FBB_D0 FBB_CMD0 CMDC1
M29 FBA_D1 FBA_CMD1 T31 E9 FBB_D1 FBB_CMD1 E14
MDA2 L29 U29 CMDA2 MDC2 G8 F14 CMDC2
MDA3 FBA_D2 FBA_CMD2 CMDA3 MDC3 FBB_D2 FBB_CMD2 CMDC3
M28 FBA_D3 FBA_CMD3 R34 F9 FBB_D3 FBB_CMD3 A12
MDA4 N31 R33 CMDA4 MDC4 F11 B12 CMDC4
MDA5 FBA_D4 FBA_CMD4 CMDA5 MDC5 FBB_D4 FBB_CMD4 CMDC5
P29 FBA_D5 FBA_CMD5 U32 G11 FBB_D5 FBB_CMD5 C14
MDA6 R29 U33 CMDA6 MDC6 F12 B14 CMDC6
MDA7 FBA_D6 FBA_CMD6 CMDA7 MDC7 FBB_D6 FBB_CMD6 CMDC7
P28 FBA_D7 FBA_CMD7 U28 G12 FBB_D7 FBB_CMD7 G15
MDA8 J28 V28 CMDA8 MDC8 G6 F15 CMDC8
MDA9 FBA_D8 FBA_CMD8 CMDA9 MDC9 FBB_D8 FBB_CMD8 CMDC9
H29 FBA_D9 FBA_CMD9 V29 F5 FBB_D9 FBB_CMD9 E15
MDA10 J29 V30 CMDA10 MDC10 E6 D15 CMDC10
MDA11 FBA_D10 FBA_CMD10 CMDA11 MDC11 FBB_D10 FBB_CMD10 CMDC11
H28 FBA_D11 FBA_CMD11 U34 F6 FBB_D11 FBB_CMD11 A14
MDA12 G29 U31 CMDA12 MDC12 F4 D14 CMDC12
MDA13 FBA_D12 FBA_CMD12 CMDA13 MDC13 FBB_D12 FBB_CMD12 CMDC13
E31 FBA_D13 FBA_CMD13 V34 G4 FBB_D13 FBB_CMD13 A15
MDA14 E32 V33 CMDA14 MDC14 E2 B15 CMDC14
MDA15 FBA_D14 FBA_CMD14 CMDA15 MDC15 FBB_D14 FBB_CMD14 CMDC15
F30 FBA_D15 FBA_CMD15 Y32 F3 FBB_D15 FBB_CMD15 C17
MDA16 C34 AA31 CMDA16 MDC16 C2 D18 CMDC16
MDA17 FBA_D16 FBA_CMD16 CMDA17 MDC17 FBB_D16 FBB_CMD16 CMDC17
D32 FBA_D17 FBA_CMD17 AA29 D4 FBB_D17 FBB_CMD17 E18
MDA18 B33 AA28 CMDA18 MDC18 D3 F18 CMDC18
MDA19 FBA_D18 FBA_CMD18 CMDA19 MDC19 FBB_D18 FBB_CMD18 CMDC19
C33 FBA_D19 FBA_CMD19 AC34 C1 FBB_D19 FBB_CMD19 A20
MDA20 F33 AC33 CMDA20 MDC20 B3 B20 CMDC20
MDA21 FBA_D20 FBA_CMD20 CMDA21 MDC21 FBB_D20 FBB_CMD20 CMDC21
F32 FBA_D21 FBA_CMD21 AA32 C4 FBB_D21 FBB_CMD21 C18
MDA22 H33 AA33 CMDA22 MDC22 B5 B18 CMDC22
MDA23 FBA_D22 FBA_CMD22 CMDA23 MDC23 FBB_D22 FBB_CMD22 CMDC23
H32 FBA_D23 FBA_CMD23 Y28 C5 FBB_D23 FBB_CMD23 G18

MEMORY INTERFACE
MDA24 P34 Y29 CMDA24 MDC24 A11 G17 CMDC24
MDA25 FBA_D24 FBA_CMD24 CMDA25 MDC25 FBB_D24 FBB_CMD24 CMDC25
P32 W31 C11 F17

MEMORY INTERFACE B
MDA26 FBA_D25 FBA_CMD25 CMDA26 MDC26 FBB_D25 FBB_CMD25 CMDC26
P31 FBA_D26 FBA_CMD26 Y30 D11 FBB_D26 FBB_CMD26 D16
MDA27 P33 AA34 CMDA27 MDC27 B11 A18 CMDC27
MDA28 FBA_D27 FBA_CMD27 CMDA28 MDC28 FBB_D27 FBB_CMD27 CMDC28
L31 FBA_D28 FBA_CMD28 Y31 D8 FBB_D28 FBB_CMD28 D17
MDA29 L34 Y34 CMDA29 MDC29 A8 A17 CMDC29
MDA30 FBA_D29 FBA_CMD29 CMDA30 MDC30 FBB_D29 FBB_CMD29 CMDC30
L32 FBA_D30 FBA_CMD30 Y33 C8 FBB_D30 FBB_CMD30 B17
MDA31 L33 V31 MDC31 B8 E17
MDA32 FBA_D31 FBA_CMD31 MDC32 FBB_D31 FBB_CMD31
AG28 FBA_D32 F24 FBB_D32
MDA33 AF29 MDC33 G23
MDA34 FBA_D33 MDC34 FBB_D33
AG29 FBA_D34 E24 FBB_D34
MDA35 AF28 R32 MDC35 G24 C12
MDA36 FBA_D35 FBA_CMD_RFU0 MDC36 FBB_D35 FBB_CMD_RFU0
AD30 FBA_D36 FBA_CMD_RFU1 AC32 D21 FBB_D36 FBB_CMD_RFU1 C20
MDA37 AD29 MDC37 E21
MDA38 FBA_D37 +1.5VSG MDC38 FBB_D37 +1.5VSG
AC29 FBA_D38 G21 FBB_D38
MDA39 AD28 R336 60.4_0402_1% MDC39 F21 R337 60.4_0402_1%
FBA_D39 FBB_D39
A

MDA40 AJ29 R28 FBA_DEBUG0 2 @ 1 MDC40 G27 G14 FBB_DEBUG0 2 @ 1

MDA41 FBA_D40 FBA_DEBUG0 FBB_D40 FBB_DEBUG0
AK29 FBA_D41 FBA_DEBUG1 AC28 FBA_DEBUG1 2 @ 1 MDC41 D27 FBB_D41 FBB_DEBUG1 G20 FBB_DEBUG1 2 @ 1
MDA42 AJ30 R338 60.4_0402_1% MDC42 G26 R339 60.4_0402_1%
MDA43 FBA_D42 MDC43 FBB_D42
AK28 FBA_D43 E27 FBB_D43
1 MDA44 AM29 MDC44 E29 1

MDA45 FBA_D44 MDC45 FBB_D44

AM31 FBA_D45 FBA_CLK0 R30 CLKA0 25 F29 FBB_D45 FBB_CLK0 D12 CLKC0 27
MDA46 AN29 R31 CLKA0# 25 MDC46 E30 E12 CLKC0# 27
MDA47 FBA_D46 FBA_CLK0_N MDC47 FBB_D46 FBB_CLK0_N
AM30 FBA_D47 FBA_CLK1 AB31 CLKA1 26 D30 FBB_D47 FBB_CLK1 E20 CLKC1 28
MDA48 AN31 AC31 CLKA1# 26 MDC48 A32 F20 CLKC1# 28
MDA49 FBA_D48 FBA_CLK1_N MDC49 FBB_D48 FBB_CLK1_N
AN32 FBA_D49 C31 FBB_D49
MDA50 AP30 MDC50 C32
MDA51 FBA_D50 MDC51 FBB_D50
AP32 FBA_D51 B32 FBB_D51
MDA52 AM33 K31 MDC52 D29 F8
MDA53 FBA_D52 FBA_WCK01 MDC53 FBB_D52 FBB_WCK01
AL31 FBA_D53 FBA_WCK01_N L30 A29 FBB_D53 FBB_WCK01_N E8
MDA54 AK33 H34 MDC54 C29 A5
MDA55 FBA_D54 FBA_WCK23 MDC55 FBB_D54 FBB_WCK23
AK32 FBA_D55 FBA_WCK23_N J34 B29 FBB_D55 FBB_WCK23_N A6
MDA56 AD34 AG30 MDC56 B21 D24
MDA57 FBA_D56 FBA_WCK45 MDC57 FBB_D56 FBB_WCK45
AD32 FBA_D57 FBA_WCK45_N AG31 C23 FBB_D57 FBB_WCK45_N D25
MDA58 AC30 AJ34 MDC58 A21 B27
MDA59 FBA_D58 FBA_WCK67 MDC59 FBB_D58 FBB_WCK67 Or use same as L10 PN: SM01000FE00
AD33 FBA_D59 FBA_WCK67_N AK34 C21 FBB_D59 FBB_WCK67_N C27
MDA60 AF31 MDC60 B24
MDA61 FBA_D60 MDC61 FBB_D60 +FB_PLLAVDD DIS@ +1.05VSG
AG34 FBA_D61 C24 FBB_D61 300mA
MDA62 AG32 MDC62 B26 L12
MDA63 FBA_D62 MDC63 FBB_D62 +FB_PLLAVDD
AG33 FBA_D63 FBA_WCKB01 J30 C26 FBB_D63 FBB_WCKB01 D6 1 2

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
J31 D7 FBMA-L11-160808300LMA25T_2P
25 DQMA[3..0] FBA_WCKB01_N 27 DQMC[3..0] FBB_WCKB01_N

DIS@ C250

DIS@ C251

DIS@ C252
DQMA0 P30 J32 DQMC0 E11 C6 1 1 1
DQMA1 FBA_DQM0 FBA_WCKB23 DQMC1 FBB_DQM0 FBB_WCKB23
F31 FBA_DQM1 FBA_WCKB23_N J33 E3 FBB_DQM1 FBB_WCKB23_N B6
DQMA2 F34 AH31 DQMC2 A3 F26 SPEC: 30ohm (ESR:0.01)
DQMA3 FBA_DQM2 FBA_WCKB45 DQMC3 FBB_DQM2 FBB_WCKB45
26 DQMA[7..4] M32 FBA_DQM3 FBA_WCKB45_N AJ31 28 DQMC[7..4] C9 FBB_DQM3 FBB_WCKB45_N E26 L12= 30ohm
DQMA4 DQMC4 2 2 2
AD31 FBA_DQM4 FBA_WCKB67 AJ32 F23 FBB_DQM4 FBB_WCKB67 A26
DQMA5 AL29 AJ33 DQMC5 F27 A27
DQMA6 FBA_DQM5 FBA_WCKB67_N DQMC6 FBB_DQM5 FBB_WCKB67_N
AM32 FBA_DQM6 C30 FBB_DQM6
DQMA7 AF34 DQMC7 A24
FBA_DQM7 FBB_DQM7
25 DQSA[3..0] 27 DQSC[3..0]
DQSA0 M31 E1 FB_CLAMP DQSC0 D10
DQSA1 FBA_DQS_WP0 FB_CLAMP DQSC1 FBB_DQS_WP0
G31 FBA_DQS_WP1 D5 FBB_DQS_WP1
DQSA2 E33 Under GPU DQSC2 C3
DQSA3 FBA_DQS_WP2 DQSC3 FBB_DQS_WP2
M33 B9
26 DQSA[7..4]
DQSA4 AE31
FBA_DQS_WP3
K27
close to ball : K27 28 DQSC[7..4]
DQSC4 E23
FBB_DQS_WP3
H17 +FB_PLLAVDD
DQSA5 FBA_DQS_WP4 FB_DLL_AVDD C247 DIS@ DQSC5 FBB_DQS_WP4 FBB_PLL_AVDD
AK30 FBA_DQS_WP5 E28 FBB_DQS_WP5 100mA
DQSA6 AN33 100mA 1 2 DQSC6 B30
FBA_DQS_WP6 FBB_DQS_WP6

0.1U_0402_16V4Z
DQSA7 AF33 0.1U_0402_16V4Z DQSC7 A23
FBA_DQS_WP7 FBB_DQS_WP7

DIS@ C249
U27 +FB_PLLAVDD 1
25 DQSA#[3..0] FBA_PLL_AVDD 27 DQSC#[3..0]
DQSA#0 M30 DQSC#0 D9
DQSA#1 FBA_DQS_RN0 DQSC#1 FBB_DQS_RN0
H30 FBA_DQS_RN1 100mA 1 2 E4 FBB_DQS_RN1
DQSA#2 E34 C248 0.1U_0402_16V4Z DQSC#2 B2
DQSA#3 FBA_DQS_RN2 DIS@ DQSC#3 FBB_DQS_RN2 2
26 DQSA#[7..4] M34 FBA_DQS_RN3 FB_VREF H26 28 DQSC#[7..4] A9 FBB_DQS_RN3
DQSA#4 AF30 DQSC#4 D22
DQSA#5 FBA_DQS_RN4 DQSC#5 FBB_DQS_RN4
AK31 FBA_DQS_RN5 Under GPU D28 FBB_DQS_RN5
DQSA#6 AM34 DQSC#6 A30 Under GPU
DQSA#7 AF32
FBA_DQS_RN6 close to ball : U27 DQSC#7 B23
FBB_DQS_RN6
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17

N13P-PES-A1_FCBGA908 N13P-PES-A1_FCBGA908
@ @
FB_CLAMP 1 GS@
2
R726 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 21 of 61
A
 5 4 3 2 1

D U10D D

Part 4 of 7
AM6 IFPA_TXC
AN6 P8 PAD @
IFPA_TXC_N NC T31
AP3 IFPA_TXD0 NC AC6
AN3 IFPA_TXD0_N NC AJ28 MULTI LEVEL STRAPS
AN5 IFPA_TXD1 NC AJ4
+3VSG +3VSG
AM5 IFPA_TXD1_N NC AJ5 Straps
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15

NC
AJ6 IFPA_TXD3 NC D19

2 DIS@ 1

@ 1

@ 1

@ 1

@ 1

@ 1
10K_0402_1%

15K_0402_5%
45.3K_0402_1%

4.99K_0402_1%

34.8K_0402_1%

34.8K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
AH6 IFPA_TXD3_N NC D20

@
NC D23
NC D26
AJ9 IFPB_TXC NC H31

R340

R341

R342

R343

R344

R345

R346

R347
AH9 T8

2
IFPB_TXC_N NC
AP6 IFPB_TXD4 NC V32
AP5 STRAP0 ROM_SI
IFPB_TXD4_N STRAP1 STRAP3 ROM_SO
AM7 IFPB_TXD5
AL7 STRAP2 STRAP4 ROM_SCLK
IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N

@ 1

@ 1

@ 1

@ 1

@ 1

@ 1
10K_0402_1%

10K_0402_1%
4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

34.8K_0402_1%

34.8K_0402_1%
AK8 IFPB_TXD7

@
@
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA_R 1 DIS@ 2
VDD_SENSE R356 0_0402_5% VCCSENSE_VGA 53

R348

R349

R350

R351

R352

R353

R354

R355
AK1

2
IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA_R 1 DIS@ 2
IFPC_L1 GND_SENSE VSSSENSE_VGA 53
AJ2 R357 0_0402_5%
IFPC_L1_N PR-6
AH3 IFPC_L2
C C
AH4 IFPC_L2_N
AG5 IFPC_L3
AG4 IFPC_L3_N
TEST DIS@
AM1 AK11 R358 1 2 10K_0402_5%
IFPD_L0 TESTMODE
AM2 IFPD_L0_N @
AM3 AM10 JTAG_TCK R359 1 2 10K_0402_5% PR-6 PR-6
IFPD_L1 JTAG_TCK JTAG_TDI @
AM4
AL3
IFPD_L1_N JTAG_TDI AM11
AP12 JTAG_TDO
PAD T32
@
Need check with NVIDIA
IFPD_L2 JTAG_TDO PAD T33
AL4 AP11 JTAG_TMS @
AK4
IFPD_L2_N JTAG_TMS
AN11 JTAG_TRST
PAD T34
@
For N13P-GS strap table
IFPD_L3 JTAG_TRST_N PAD T35
AK5 IFPD_L3_N
LVDS/TMDS

1 DIS@ 2 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
R360 10K_0402_5%
AD2 N13P-GS 900 MHz 128M* 16* 8 Samsung R R R R R R R R
IFPE_L0 2GB SA000047QA0 PU 45K PD 5K PD 15K PD 25K PD 45K PD 45K PU 10K PU 5K
AD3 IFPE_L0_N N13P-GS 900 MHz 128M* 16* 8 Hynix B R R R R R R R R
AD1
AC1
IFPE_L1 SERIAL R361 10K_0402_5% 2GB SA00003YO30 PU 45K PD 5K PD 15K PD 25K PD 45K PD 35K PU 10K PU 5K
IFPE_L1_N ROM_CS# N13P-GS R R R
AC2 IFPE_L2 ROM_CS_N H6 1 DIS@ 2 +3VSG 900 MHz 64M* 16* 8 Samsung R R R R R
AC3 H4 ROM_SCLK 1GB SA00004GS30 PU 45K PD 5K PD 15K PD 25K PD 45K PD 20K PU 10K PU 5K
IFPE_L2_N ROM_SCLK ROM_SI N13P-GS 900 MHz 64M* 16* 8 Hynix R R R R R R R R
AC4 IFPE_L3 ROM_SI H5
AC5 H7 ROM_SO 1GB SA000041S60 PU 45K PD 5K PD 15K PD 25K PD 45K PD 15K PU 10K PU 5K
IFPE_L3_N ROM_SO N13P-GS 900 MHz 128M* 16* 8 Hynix D R
2GB SA00003YO30 PD 30K
AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5 IFPF_L1_N GENERAL R362 10K_0402_5%
AD4
AD5
IFPF_L2
L2 1 @ 2
For N13P-GL strap table
IFPF_L2_N BUFRST_N
AG1 IFPF_L3
B R363 1 DIS@ B
AF1 IFPF_L3_N CEC L3 2 10K_0402_5% +3VSG GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

J1 MULTI_STRAP_REF0_GND 1 DIS@ 2 900 MHz 128M* 16* 8 Samsung R R R R R R R R

MULTI_STRAP_REF0_GND R364 40.2K_0402_1% N13P-GL 2GB SA000047QA0 PU 45K PD 45K PU 10K PD 5K PD 10K PD 45K PU 10K PD 15K
AG3 900 MHz 128M* 16* 8 Hynix B R R R R R R R R
IFPC_AUX_I2CW_SCL N13P-GL 2GB SA00003YO30 PU 45K PD 45K PU 10K PD 5K PD 10K PD 35K PU 10K PD 15K
AG2 IFPC_AUX_I2CW_SDA_N
J2 STRAP0 900 MHz 64M* 16* 8 Samsung R R R R R R R R
STRAP0 STRAP1 N13P-GL 1GB SA00004GS30 PU 45K PD 45K PU 10K PD 5K PD 10K PD 20K PU 10K PD 15K
STRAP1 J7
AK3 J6 STRAP2 900 MHz 64M* 16* 8 Hynix R R R R R R R R
IFPD_AUX_I2CX_SCL STRAP2 STRAP3 N13P-GL 1GB SA000041S60 PU 45K PD 45K PU 10K PD 5K PD 10K PD 15K PU 10K PD 15K
AK2 IFPD_AUX_I2CX_SDA_N STRAP3 J5
J3 STRAP4 900 MHz 128M* 16* 8 Hynix D R
STRAP4 N13P-GL 2GB SA00003YO30 PD 30K
AB3 IFPE_AUX_I2CY_SCL
AB4 IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 IFPF_AUX_I2CZ_SCL For N13M-GE1 strap table
AF2 IFPF_AUX_I2CZ_SDA_N
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

900 MHz 128M* 16* 4 Samsung R R R R R R R R

N13M-GE1 1GB SA000047QA0 PU 45K PD 45K PU 5K PD 5K PD 10K PD 45K PU 10K PU 5K
N13P-PES-A1_FCBGA908 900 MHz 128M* 16* 4 Hynix R R R R R R R R
@ N13M-GE1 1GB SA00003YO30 PU 45K PD 45K PU 5K PD 5K PD 10K PD 35K PU 10K PU 5K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 22 of 61
5 4 3 2 1
 5 4 3 2 1

Under GPU Near GPU +1.05VSG

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
DIS@ C253

DIS@ C254

DIS@ C255

DIS@ C256

DIS@ C257

DIS@C258
C258

DIS@C259
C259
1 1 1 1 1 1 1

DIS@

DIS@
2 2 2 2 2 2 2
U10E

+1.5VSG Under GPU Part 5 of 7

D D
7200mA
AA27 AG19 Under GPU Near GPU +1.05VSG
FBVDDQ_0 PEX_IOVDD_0

1U_0402_6.3V6K
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C260 AA30 FBVDDQ_1 PEX_IOVDD_1 AG21

DIS@ C261

DIS@ C262

DIS@ C263

DIS@ C264

DIS@ C265
1 1 1 1 1 1 AB27 FBVDDQ_2 PEX_IOVDD_2 AG22

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
AB33 FBVDDQ_3 PEX_IOVDD_3 AG24

DIS@ C266

DIS@ C267

DIS@ C268

DIS@ C269

DIS@ C270

DIS@ C271

DIS@ C272
AC27 FBVDDQ_4 PEX_IOVDD_4 AH21 2700 mA 1 1 1 1 1 1 1
AD27 FBVDDQ_5 PEX_IOVDD_5 AH25
2 2 2 2 2 2
AE27 FBVDDQ_6
AF27 FBVDDQ_7 2 2 2 2 2 2 2
AG27 FBVDDQ_8 PEX_IOVDDQ_0 AG13
B13 FBVDDQ_9 PEX_IOVDDQ_1 AG15
Under GPU B16 AG16
FBVDDQ_10 PEX_IOVDDQ_2
B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18
E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25
1U_0402_6.3V6K
4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15
+3VSG
DIS@ C273

DIS@ C274

DIS@ C275

DIS@ C276

DIS@ C277

DIS@ C278
1 1 1 1 1 1 E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18
H10 AH26 Near GPU
FBVDDQ_15 PEX_IOVDDQ_7
H11 FBVDDQ_16 PEX_IOVDDQ_8 AH27

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
2 2 2 2 2 2

DIS@ C279

DIS@ C280

DIS@ C281
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27 1 1 1
H14 AL27

POWER
FBVDDQ_19 PEX_IOVDDQ_11 L13
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
Near GPU 2 2 2
H18 FBVDDQ_22
H19 GS@
FBVDDQ_23
H20 FBVDDQ_24 150mA 370mA
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

H21 FBVDDQ_25 PEX_PLL_HVDD AH12

DIS@ C283

DIS@ C284

DIS@ C285

DIS@ C286

1 1 1 1 H22 FBVDDQ_26 0_0603_5%

H23 @ 1 2
FBVDDQ_27 C282 0.1U_0402_16V4Z +1.05VSG
H24 FBVDDQ_28
H8 AG12 Under GPU Near GPU GEL@
2 2 2 2 FBVDDQ_29 PEX_SVDD_3V3
H9 FBVDDQ_30 2 1

1U_0402_6.3V6K
C C

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
L27 @ 1 2 L13
FBVDDQ_31

DIS@ C288

DIS@ C289

DIS@ C290
M27 C287 0.1U_0402_16V4Z 150mA 1 1 1 BLM18PG121SN1D_0603
FBVDDQ_32 +PEX_PLLVDD
N27 FBVDDQ_33 PEX_PLLVDD AG26
P27 FBVDDQ_34
SPEC: 120ohm ESR:0.18
R27 L13= 120ohm
FBVDDQ_35 2 2 2
T27 FBVDDQ_36
T30 J8 +3V3MISC
FBVDDQ_37 VDD33_0
T33 FBVDDQ_38 VDD33_1 K8
V27 120mA L8 +VDD33
FBVDDQ_39 VDD33_2
W27 FBVDDQ_40 VDD33_3 M8
W30 FBVDDQ_41
W33 FBVDDQ_42
Y27 FBVDDQ_43 29 DGPU_PWR_EN#
AH8 +IFPAB_PLLVDD R366 1 DIS@ 2 10K_0402_5%
IFPAB_PLLVDD IFPAB_RESET R367 1 @ 2 1K_0402_5%
IFPAB_RSET AJ8

+1.5VSG AG8 +IFPAB_IOVDD R368 1 DIS@ 2 10K_0402_5% +3VSG

IFPA_IOVDD

2
G
AG9 Under GPU (one per pin) Q62
FB_VDDQ_SENSE IFPB_IOVDD +3V3MISC AO3419L 1P SOT23-3
2 1 F1 FB_VDDQ_SENSE
R369 DIS@ 10_0402_5% +3V3MISC 3 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+IFPC_PLLVDD R370 1 DIS@ 2 10K_0402_5%

D
IFPC_PLLVDD AF7

DIS@ C291

DIS@ C292
2 1 FB_GND_SENSE F2 AF8 R372 1 @ 2 1K_0402_5% 1 1 GS@
+1.5VSG R371 DIS@ 10_0402_5% FB_GND_SENSE IFPC_RSET
AF6 +IFPC_IOVDD R373 1 DIS@ 2 10K_0402_5%
DIS@ 1 FB_CAL_PD_VDDQ J27 IFPC_IOVDD
2 FB_CAL_PD_VDDQ 1 2
R374 40.2_0402_1% 2 2 R737 GEL@ 0_0402_5%
AG7 +IFPD_PLLVDD R375 1 DIS@ 2 10K_0402_5%
DIS@ 2 FB_CAL_PU_GND H27 IFPD_PLLVDD IFPD_RESET R377 1 @ 2 1K_0402_5% +3VS
1 FB_CAL_PU_GND IFPD_RSET AN2
R376 42.2_0402_1% @
AG6 +IFPD_IOVDD R378 1 DIS@ 2 10K_0402_5% 1 2
DIS@ 1 FB_CAL_TERM_GND H25 IFPD_IOVDD R739 0_0402_5%
2 FB_CAL_TERM_GND
R379 51.1_0402_1%
B +IFPEF_PLLVDD R380 1 DIS@ 2 10K_0402_5% B
IFPEF_PLVDD AB8
AD6 IFPEF_RESET R381 1 @ 2 1K_0402_5%
IFPEF_RSET
AC7 +IFPEF_IOVDD R382 1 DIS@ 2 10K_0402_5% Under GPU (one per pin)
Place near balls IFPE_IOVDD
IFPF_IOVDD AC8
+VDD33 2 1

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
R365

DIS@ C293

DIS@ C294

DIS@ C295

DIS@ C296

DIS@ C297
1 1 1 1 1 0_0603_5%

N13P-PES-A1_FCBGA908 PR-7
@
2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 23 of 61
5 4 3 2 1
 5 4 3 2 1

U10F +VGA_CORE U10G +VGA_CORE

Part 6 of 7
A2 D2 50A Part 7 of 7 V17
D GND_0 GND_100 VDD_56 D
AA17 GND_1 GND_101 D31 AA12 VDD_0 VDD_57 V18
AA18 GND_2 GND_102 D33 AA14 VDD_1 VDD_58 V20
AA20 GND_3 GND_103 E10 AA16 VDD_2 VDD_59 V22
AA22 GND_4 GND_104 E22 AA19 VDD_3 VDD_60 W12
AB12 GND_5 GND_105 E25 AA21 VDD_4 VDD_61 W14
AB14 GND_6 GND_106 E5 AA23 VDD_5 VDD_62 W16
AB16 GND_7 GND_107 E7 AB13 VDD_6 VDD_63 W19
AB19 GND_8 GND_108 F28 AB15 VDD_7 VDD_64 W21
AB2 GND_9 GND_109 F7 AB17 VDD_8 VDD_65 W23
AB21 GND_10 GND_110 G10 AB18 VDD_9 VDD_66 Y13
A33 GND_11 GND_111 G13 AB20 VDD_10 VDD_67 Y15
AB23 GND_12 GND_112 G16 AB22 VDD_11 VDD_68 Y17
AB28 GND_13 GND_113 G19 AC12 VDD_12 VDD_69 Y18
AB30 GND_14 GND_114 G2 AC14 VDD_13 VDD_70 Y20
AB32 GND_15 GND_115 G22 AC16 VDD_14 VDD_71 Y22
AB5 GND_16 GND_116 G25 AC19 VDD_15
AB7 GND_17 GND_117 G28 AC21 VDD_16
AC13 GND_18 GND_118 G3 AC23 VDD_17 XVDD_1 U1
AC15 GND_19 GND_119 G30 M12 VDD_18 XVDD_2 U2
AC17 GND_20 GND_120 G32 M14 VDD_19 XVDD_3 U3

POWER
AC18 GND_21 GND_121 G33 M16 VDD_20 XVDD_4 U4
AA13 GND_22 GND_122 G5 M19 VDD_21 XVDD_5 U5
AC20 GND_23 GND_123 G7 M21 VDD_22 XVDD_6 U6
AC22 GND_24 GND_124 K2 M23 VDD_23 XVDD_7 U7
AE2 GND_25 GND_125 K28 N13 VDD_24 XVDD_8 U8
AE28 GND_26 GND_126 K30 N15 VDD_25
AE30 GND_27 GND_127 K32 N17 VDD_26
AE32 GND_28 GND_128 K33 N18 VDD_27 XVDD_9 V1
AE33 GND_29 GND_129 K5 N20 VDD_28 XVDD_10 V2
AE5 GND_30 GND_130 K7 N22 VDD_29 XVDD_11 V3
AE7 GND_31 GND_131 M13 P12 VDD_30 XVDD_12 V4
AH10 GND_32 GND_132 M15 P14 VDD_31 XVDD_13 V5
C C
AA15 GND_33 GND_133 M17 P16 VDD_32 XVDD_14 V6
AH13 GND_34 GND_134 M18 P19 VDD_33 XVDD_15 V7
AH16 GND_35 GND_135 M20 P21 VDD_34 XVDD_16 V8
AH19 GND_36 GND_136 M22 P23 VDD_35
AH2 GND_37 GND_137 N12 R13 VDD_36
AH22 GND_38 GND_138 N14 R15 VDD_37 XVDD_17 W2
AH24 GND_39 GND_139 N16 R17 VDD_38 XVDD_18 W3
AH28 GND_40 GND_140 N19 R18 VDD_39 XVDD_19 W4
AH29 GND_41 GND_141 N2 R20 VDD_40 XVDD_20 W5
AH30 GND_42 GND_142 N21 R22 VDD_41 XVDD_21 W7
GND

AH32 GND_43 GND_143 N23 T12 VDD_42 XVDD_22 W8

AH33 GND_44 GND_144 N28 T14 VDD_43
AH5 GND_45 GND_145 N30 T16 VDD_44
AH7 GND_46 GND_146 N32 T19 VDD_45 XVDD_23 Y1
AJ7 GND_47 GND_147 N33 T21 VDD_46 XVDD_24 Y2
AK10 GND_48 GND_148 N5 T23 VDD_47 XVDD_25 Y3
AK7 GND_49 GND_149 N7 U13 VDD_48 XVDD_26 Y4
AL12 GND_50 GND_150 P13 U15 VDD_49 XVDD_27 Y5
AL14 GND_51 GND_151 P15 U17 VDD_50 XVDD_28 Y6
AL15 GND_52 GND_152 P17 U18 VDD_51 XVDD_29 Y7
AL17 GND_53 GND_153 P18 U20 VDD_52 XVDD_30 Y8
AL18 GND_54 GND_154 P20 U22 VDD_53
AL2 GND_55 GND_155 P22 V13 VDD_54
AL20 GND_56 GND_156 R12 V15 VDD_55 XVDD_31 AA1
AL21 GND_57 GND_157 R14 XVDD_32 AA2
AL23 GND_58 GND_158 R16 XVDD_33 AA3
AL24 GND_59 GND_159 R19 XVDD_34 AA4
AL26 GND_60 GND_160 R21 XVDD_35 AA5
AL28 GND_61 GND_161 R23 XVDD_36 AA6
AL30 GND_62 GND_162 T13 XVDD_37 AA7
AL32 GND_63 GND_163 T15 XVDD_38 AA8
AL33 GND_64 GND_164 T17
B B
AL5 GND_65 GND_165 T18
AM13 GND_66 GND_166 T2
AM16 GND_67 GND_167 T20
AM19 T22 N13P-PES-A1_FCBGA908
GND_68 GND_168
AM22 GND_69 GND_169 AG11
AM25 GND_70 GND_170 T28
AN1 GND_71 GND_171 T32
AN10 GND_72 GND_172 T5
AN13 GND_73 GND_173 T7
AN16 GND_74 GND_174 U12
AN19 GND_75 GND_175 U14
AN22 GND_76 GND_176 U16
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
A A
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_OPT C16
GND_OPT W32

Security Classification Compal Secret Data Compal Electronics, Inc.

N13P-PES-A1_FCBGA908 2011/08/23 2012/12/31 Title
Issued Date Deciphered Date
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 24 of 61
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
CMD0 CS0_L#
D 64Mx16 DDR3 *8==>1GB CMD1 D

128Mx16 DDR3 *8==>2GB CMD2 ODT_L

CMD3 CKE
CMD4 A14 A14
DQSA[7..0] CMD5 RST RST
21,26 DQSA[7..0]
U12 @ U13 @
DQSA#[7..0] CMD6 A9 A9
21,26 DQSA#[7..0]
+MEM_VREF0 M8 E3 MDA11 +MEM_VREF1 M8 E3 MDA1
DQMA[7..0] VREFCA DQL0 MDA12 VREFCA DQL0 MDA5
21,26 DQMA[7..0] H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 CMD7 A7 A7
F2 MDA8 F2 MDA2
MDA[63..0] CMDA9 DQL2 MDA13 CMDA9 DQL2 MDA7
21,26 MDA[63..0] N3 A0 DQL3 F8 N3 A0 DQL3 F8 CMD8 A2 A2
CMDA11 P7 H3 MDA9 Group1 CMDA11 P7 H3 MDA0 Group0
CMDA[30..0] CMDA8 A1 DQL4 MDA14 CMDA8 A1 DQL4 MDA6
21,26 CMDA[30..0] P3 A2 DQL5 H8 P3 A2 DQL5 H8 CMD9 A0 A0
CMDA25 N2 G2 MDA10 CMDA25 N2 G2 MDA3
CMDA10 A3 DQL6 MDA15 CMDA10 A3 DQL6 MDA4
P8 A4 DQL7 H7 P8 A4 DQL7 H7 CMD10 A4 A4
CMDA24 P2 CMDA24 P2
CMDA22 A5 CMDA22 A5
R8 A6 R8 A6 CMD11 A1 A1
+1.5VSG CMDA7 R2 D7 MDA30 CMDA7 R2 D7 MDA21
CMDA21 A7 DQU0 MDA25 CMDA21 A7 DQU0 MDA19
T8 A8 DQU1 C3 T8 A8 DQU1 C3 CMD12 BA0 BA0
CMDA6 R3 C8 MDA31 CMDA6 R3 C8 MDA23
CMDA29 A9 DQU2 MDA27 CMDA29 A9 DQU2 MDA17
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 CMD13 WE* WE*
DIS@ CMDA23 R7 A7 MDA28 Group3 CMDA23 R7 A7 MDA20 Group2
R383 CMDA28 A11 DQU4 MDA26 CMDA28 A11 DQU4 MDA16
N7 A12 DQU5 A2 N7 A12 DQU5 A2 CMD14 A15 A15
240_0402_1% CMDA20 T3 B8 MDA29 CMDA20 T3 B8 MDA22
CMDA4 A13 DQU6 MDA24 CMDA4 A13 DQU6 MDA18
T7 A14 DQU7 A3 T7 A14 DQU7 A3 CMD15 CAS* CAS*
CMDA14 M7 CMDA14 M7
+MEM_VREF0 A15/BA3 +1.5VSG A15/BA3 +1.5VSG
CMD16 CS0_H#
DIS@

C C
0.1U_0402_16V4Z

1 CMDA12 M2 B2 CMDA12 M2 B2 CMD17

DIS@ CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
R384 CMDA26 M3 G7 CMDA26 M3 G7 CMD18 ODT_H
240_0402_1% BA2 VDD BA2 VDD
VDD K2 VDD K2
2
C298

VDD K8 VDD K8 CMD19 CKE_H

VDD N1 VDD N1
CLKA0 J7 N9 CLKA0 J7 N9 CMD20 A13 A13
CLKA0# CK VDD CLKA0# CK VDD
K7 CK VDD R1 K7 CK VDD R1
CMDA3 K9 R9 CMDA3 K9 R9 CMD21 A8 A8
CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
CMD22 A6 A6
+1.5VSG CMDA2 K1 A1 CMDA2 K1 A1
CMDA0 ODT/ODT0 VDDQ CMDA0 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD23 A11 A11
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD24 A5 A5
DIS@ CMDA13 L3 D2 CMDA13 L3 D2
R385 WE VDDQ WE VDDQ
310mA VDDQ E9 310mA VDDQ E9 CMD25 A3 A3
240_0402_1% F1 F1
DQSA1 VDDQ DQSA0 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD26 BA2 BA2
DQSA3 C7 H9 DQSA2 C7 H9
+MEM_VREF1 DQSU VDDQ DQSU VDDQ
CMD27 BA1 BA1
DIS@
0.1U_0402_16V4Z

1 DQMA1 E7 A9 DQMA0 E7 A9 CMD28 A12 A12

DIS@ DQMA3 DML VSS DQMA2 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
R386 E1 E1 CMD29 A10 A10
240_0402_1% VSS VSS
VSS G8 VSS G8
2
C299

DQSA#1 G3 J2 DQSA#0 G3 J2 CMD30 RAS* RAS*

DQSA#3 DQSL VSS DQSA#2 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 Not Available
VSS M9 VSS M9

CMDA5 VSS P1
CMDA5 VSS P1 LOW HIGH
T2 RESET VSS P9 T2 RESET VSS P9
B B
VSS T1 VSS T1
ZQ0 L8 T9 ZQ1 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
CLKA0
21 CLKA0
DIS@ J1 B1 DIS@ J1 B1 CMDA2 R390 1 DIS@ 2 10K_0402_5% Command Bit Default Pull-down
NC/ODT1 VSSQ NC/ODT1 VSSQ
1

R388 L1 B9 R389 L1 B9 CMDA3 R391 1 DIS@ 2 10K_0402_5%

DIS@ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ CMDA5 R393 DIS@ 10K_0402_5%
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 1 2 ODTx 10k
R392 L9 D8 L9 D8 CMDA18 R394 1 DIS@ 2 10K_0402_5%
2

2
160_0402_1% NCZQ1 VSSQ NCZQ1 VSSQ CMDA19 R395 DIS@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 1 2
E8 E8 RST 10k
2

CLKA0# VSSQ VSSQ

21 CLKA0# VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSG +1.5VSG
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C305

DIS@ C306

DIS@ C307

DIS@ C308

DIS@ C309

DIS@ C310

DIS@ C315

DIS@ C316

DIS@ C317

DIS@ C318

DIS@ C319
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AMD :SA00003PF10
DIS@ C301

DIS@ C302

DIS@ C303

DIS@ C304

DIS@ C311

DIS@ C312

DIS@ C313

DIS@ C314

(S IC D3 64M16/800 23EY2387MB-12 PG-TFBGA 96P 1.5V)

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 25 of 61
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD0 CS0_L#
CMD1
D
128Mx16 DDR3 *8==>2GB D
CMD2 ODT_L
U14 @ U15 @
CMD3 CKE
+MEM_VREF2 M8 E3 MDA41 +MEM_VREF3 M8 E3 MDA33
VREFCA DQL0 MDA47 VREFCA DQL0 MDA36
DQMA[7..0]
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 CMD4 A14 A14
F2 MDA43 F2 MDA34
21,25 DQMA[7..0] DQL2 DQL2
CMDA9 N3 F8 MDA45 CMDA9 N3 F8 MDA37 CMD5 RST RST
CMDA[30..0] CMDA11 A0 DQL3 MDA40 Group5 CMDA11 A0 DQL3 MDA35 Group4
21,25 CMDA[30..0] P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDA8 P3 H8 MDA46 CMDA8 P3 H8 MDA38 CMD6 A9 A9
DQSA#[7..0] CMDA25 A2 DQL5 MDA42 CMDA25 A2 DQL5 MDA32
21,25 DQSA#[7..0] N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA10 P8 H7 MDA44 CMDA10 P8 H7 MDA39 CMD7 A7 A7
DQSA[7..0] CMDA24 A4 DQL7 CMDA24 A4 DQL7
21,25 DQSA[7..0] P2 A5 P2 A5
CMDA22 R8 CMDA22 R8 CMD8 A2 A2
MDA[63..0] CMDA7 A6 MDA50 CMDA7 A6 MDA58
21,25 MDA[63..0] R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDA21 T8 C3 MDA53 CMDA21 T8 C3 MDA60 CMD9 A0 A0
CMDA6 A8 DQU1 MDA49 CMDA6 A8 DQU1 MDA56
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDA29 L7 C2 MDA52 CMDA29 L7 C2 MDA62 CMD10 A4 A4
CMDA23 A10/AP DQU3 MDA48 Group6 CMDA23 A10/AP DQU3 MDA57 Group7
R7 A11 DQU4 A7 R7 A11 DQU4 A7
CMDA28 N7 A2 MDA54 CMDA28 N7 A2 MDA63 CMD11 A1 A1
+1.5VSG CMDA20 A12 DQU5 MDA51 CMDA20 A12 DQU5 MDA59
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA4 T7 A3 MDA55 CMDA4 T7 A3 MDA61 CMD12 BA0 BA0
CMDA14 A14 DQU7 CMDA14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
DIS@ +1.5VSG +1.5VSG CMD13 WE* WE*
R397
240_0402_1% CMDA12 M2 B2 CMDA12 M2 B2 CMD14 A15 A15
CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CMDA26 M3 G7 CMDA26 M3 G7 CMD15 CAS* CAS*
BA2 VDD BA2 VDD
VDD K2 VDD K2
+MEM_VREF2 K8 K8 CMD16 CS0_H#
VDD VDD
VDD N1 VDD N1
DIS@
0.1U_0402_16V4Z

DIS@ 1 CLKA1 J7 N9 CLKA1 J7 N9 CMD17

R398 CLKA1# CK VDD CLKA1# CK VDD
K7 CK VDD R1 K7 CK VDD R1
C 240_0402_1% CMDA19 CMDA19 C
K9 CKE/CKE0 VDD R9
+1.5VSG
K9 CKE/CKE0 VDD R9
+1.5VSG
CMD18 ODT_H
2
C320

CMD19 CKE_H
CMDA18 K1 A1 CMDA18 K1 A1
CMDA16 ODT/ODT0 VDDQ CMDA16 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD20 A13 A13
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD21 A8 A8
CMDA13 L3 D2 CMDA13 L3 D2
WE VDDQ WE VDDQ
310mA VDDQ E9 310mA VDDQ E9 CMD22 A6 A6
+1.5VSG F1 F1
DQSA5 VDDQ DQSA4 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD23 A11 A11
DQSA6 C7 H9 DQSA7 C7 H9
DIS@ DQSU VDDQ DQSU VDDQ
CMD24 A5 A5
R399
240_0402_1% DQMA5 E7 A9 DQMA4 E7 A9 CMD25 A3 A3
DQMA6 DML VSS DQMA7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD26 BA2 BA2
VSS G8 VSS G8
+MEM_VREF3 DQSA#5 G3 J2 DQSA#4 G3 J2 CMD27 BA1 BA1
DQSA#6 DQSL VSS DQSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
DIS@
0.1U_0402_16V4Z

DIS@ 1 M1 M1 CMD28 A12 A12

R400 VSS VSS
VSS M9 VSS M9
240_0402_1% P1 P1 CMD29 A10 A10
CMDA5 VSS CMDA5 VSS
T2 RESET VSS P9 T2 RESET VSS P9
2
C321

VSS T1 VSS T1 CMD30 RAS* RAS*

ZQ2 L8 T9 ZQ3 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
Not Available
1

1
DIS@
DIS@ J1 B1 R402 J1 B1 LOW HIGH
R401 NC/ODT1 VSSQ 243_0402_1% NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
243_0402_1% J9 D1 J9 D1
CLKA1 NC/CE1 VSSQ NC/CE1 VSSQ
21 CLKA1 L9 D8 L9 D8
2

2
B NCZQ1 VSSQ NCZQ1 VSSQ B
VSSQ E2 VSSQ E2
1

VSSQ E8 VSSQ E8
DIS@ F9 F9
R404 VSSQ VSSQ
VSSQ G1 VSSQ G1
160_0402_1% G9 G9
VSSQ VSSQ
2

CLKA1# 96-BALL 96-BALL

21 CLKA1#
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSG +1.5VSG
C327

C328

C329

C330

C331

C332
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C337

DIS@ C338

DIS@ C339

DIS@ C340

DIS@ C341
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2
DIS@ C323

DIS@ C324

DIS@ C325

DIS@ C326

DIS@ C333

DIS@ C334

DIS@ C335

DIS@ C336
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 26 of 61
5 4 3 2 1
 5 4 3 2 1

Mode D
Address 0..31 32..63
VRAM DDR3 chips (1GB) CMD0 CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB CMD2 ODT_L
D D
CMD3 CKE
128Mx16 DDR3 *8==>2GB
CMD4 A14 A14

DQSC[7..0]
CMD5 RST RST
21,28 DQSC[7..0]
CMD6 A9 A9
DQSC#[7..0] U16 @ U17 @
21,28 DQSC#[7..0]
CMD7 A7 A7
DQMC[7..0] +MEM_VREF4 M8 E3 MDC8 +MEM_VREF5 M8 E3 MDC1
21,28 DQMC[7..0] VREFCA DQL0 VREFCA DQL0
H1 F7 MDC12 H1 F7 MDC4 CMD8 A2 A2
MDC[63..0] VREFDQ DQL1 MDC10 VREFDQ DQL1 MDC3
21,28 MDC[63..0] DQL2 F2 DQL2 F2
CMDC9 N3 F8 MDC13 CMDC9 N3 F8 MDC5 CMD9 A0 A0
CMDC[30..0] CMDC11 A0 DQL3 MDC9 Group1 CMDC11 A0 DQL3 MDC2 Group0
21,28 CMDC[30..0] P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDC8 P3 H8 MDC14 CMDC8 P3 H8 MDC6 CMD10 A4 A4
CMDC25 A2 DQL5 MDC11 CMDC25 A2 DQL5 MDC0
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC10 P8 H7 MDC15 CMDC10 P8 H7 MDC7 CMD11 A1 A1
CMDC24 A4 DQL7 CMDC24 A4 DQL7
P2 A5 P2 A5
CMDC22 R8 CMDC22 R8 CMD12 BA0 BA0
+1.5VSG CMDC7 A6 MDC30 CMDC7 A6 MDC23
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC21 T8 C3 MDC25 CMDC21 T8 C3 MDC17 CMD13 WE* WE*
CMDC6 A8 DQU1 MDC31 CMDC6 A8 DQU1 MDC22
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDC29 L7 C2 MDC27 CMDC29 L7 C2 MDC19 CMD14 A15 A15
DIS@ CMDC23 A10/AP DQU3 MDC28 Group3 CMDC23 A10/AP DQU3 MDC20 Group2
R7 A11 DQU4 A7 R7 A11 DQU4 A7
R406 CMDC28 N7 A2 MDC26 CMDC28 N7 A2 MDC18 CMD15 CAS* CAS*
240_0402_1% CMDC20 A12 DQU5 MDC29 CMDC20 A12 DQU5 MDC21
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDC4 T7 A3 MDC24 CMDC4 T7 A3 MDC16 CMD16 CS0_H#
CMDC14 A14 DQU7 CMDC14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+MEM_VREF4 +1.5VSG +1.5VSG CMD17
DIS@
0.1U_0402_16V4Z

1 CMDC12 M2 B2 CMDC12 M2 B2 CMD18 ODT_H

DIS@ CMDC27 BA0 VDD CMDC27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
C R407 CMDC26 CMDC26 C
M3 BA2 VDD G7 M3 BA2 VDD G7 CMD19 CKE_H
240_0402_1% K2 K2
2 VDD VDD
C342

VDD K8 VDD K8 CMD20 A13 A13

VDD N1 VDD N1
CLKC0 J7 N9 CLKC0 J7 N9 CMD21 A8 A8
CLKC0# CK VDD CLKC0# CK VDD
K7 CK VDD R1 K7 CK VDD R1
CMDC3 K9 R9 CMDC3 K9 R9 CMD22 A6 A6
CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
CMD23 A11 A11
CMDC2 K1 A1 CMDC2 K1 A1
CMDC0 ODT/ODT0 VDDQ CMDC0 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD24 A5 A5
CMDC30 J3 C1 CMDC30 J3 C1
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD25 A3 A3
+1.5VSG CMDC13 L3 D2 CMDC13 L3 D2
WE VDDQ WE VDDQ
310mA VDDQ E9 VDDQ E9 CMD26 BA2 BA2
DQSC1 VDDQ F1
DQSC0
310mA VDDQ F1
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD27 BA1 BA1
DIS@ DQSC3 C7 H9 DQSC2 C7 H9
R408 DQSU VDDQ DQSU VDDQ
CMD28 A12 A12
240_0402_1%
DQMC1 E7 A9 DQMC0 E7 A9 CMD29 A10 A10
DQMC3 DML VSS DQMC2 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
+MEM_VREF5 E1 E1 CMD30 RAS* RAS*
VSS VSS
VSS G8 VSS G8
DIS@
0.1U_0402_16V4Z

1 DQSC#1 G3 J2 DQSC#0 G3 J2 Not Available

DIS@ DQSC#3 DQSL VSS DQSC#2 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
R409 M1 M1 LOW HIGH
240_0402_1% VSS VSS
VSS M9 VSS M9
2
C343

VSS P1 VSS P1
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1
ZQ4 L8 T9 ZQ5 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
1

1
DIS@ J1 B1 DIS@ J1 B1 Command Bit Default Pull-down
R410 NC/ODT1 VSSQ R411 NC/ODT1 VSSQ CMDC2 R412 DIS@ 10K_0402_5%
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 1 2
243_0402_1% J9 D1 243_0402_1% J9 D1 CMDC3 R413 1 DIS@ 2 10K_0402_5% ODTx 10k
NC/CE1 VSSQ NC/CE1 VSSQ CMDC5 R414 DIS@ 10K_0402_5%
L9 D8 L9 D8 1 2
2

2
NCZQ1 VSSQ NCZQ1 VSSQ CMDC18 R415 DIS@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 1 2
E8 E8 CMDC19 R416 1 DIS@ 2 10K_0402_5% RST 10k
VSSQ VSSQ
VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
CLKC0 G9 G9
21 CLKC0 VSSQ VSSQ
1

96-BALL 96-BALL
DIS@ SDRAM DDR3 SDRAM DDR3
R418 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
160_0402_1%
2

CLKC0#
21 CLKC0# +1.5VSG
+1.5VSG
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C349

DIS@ C350

DIS@ C351

DIS@ C352

DIS@ C353

DIS@ C354

DIS@ C359

DIS@ C360

DIS@ C361

DIS@ C362

DIS@ C363
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1U_0402_6.3V6K 1 1 1 1 1
DIS@ C345

DIS@ C346

DIS@ C347

DIS@ C348

DIS@ C355

DIS@ C356

DIS@ C357

DIS@ C358

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 27 of 61
5 4 3 2 1
 5 4 3 2 1

VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB
D 128Mx16 DDR3 *8==>2GB D

DQMC[7..0]
21,27 DQMC[7..0]
CMDC[30..0] Mode D
21,27 CMDC[30..0]
DQSC#[7..0]
Address 0..31 32..63
U18 @ U19 @
21,27 DQSC#[7..0]
CMD0 CS0_L#
DQSC[7..0] +MEM_VREF6 M8 E3 MDC36 +MEM_VREF7 M8 E3 MDC44
21,27 DQSC[7..0] VREFCA DQL0 VREFCA DQL0
H1 F7 MDC33 H1 F7 MDC41 CMD1
MDC[63..0] VREFDQ DQL1 MDC37 VREFDQ DQL1 MDC47
21,27 MDC[63..0] DQL2 F2 DQL2 F2
CMDC9 N3 F8 MDC32 CMDC9 N3 F8 MDC43 CMD2 ODT_L
CMDC11 A0 DQL3 MDC38 Group4 CMDC11 A0 DQL3 MDC45 Group5
P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDC8 P3 H8 MDC35 CMDC8 P3 H8 MDC42 CMD3 CKE
CMDC25 A2 DQL5 MDC39 CMDC25 A2 DQL5 MDC46
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC10 P8 H7 MDC34 CMDC10 P8 H7 MDC40 CMD4 A14 A14
CMDC24 A4 DQL7 CMDC24 A4 DQL7
P2 A5 P2 A5
CMDC22 R8 CMDC22 R8 CMD5 RST RST
+1.5VSG CMDC7 A6 MDC49 CMDC7 A6 MDC56
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC21 T8 C3 MDC52 CMDC21 T8 C3 MDC60 CMD6 A9 A9
CMDC6 A8 DQU1 MDC51 CMDC6 A8 DQU1 MDC58
R3 A9 DQU2 C8 R3 A9 DQU2 C8
DIS@ CMDC29 L7 C2 MDC53 CMDC29 L7 C2 MDC62 CMD7 A7 A7
R420 CMDC23 A10/AP DQU3 MDC50 Group6 CMDC23 A10/AP DQU3 MDC57 Group7
R7 A11 DQU4 A7 R7 A11 DQU4 A7
240_0402_1% CMDC28 N7 A2 MDC54 CMDC28 N7 A2 MDC63 CMD8 A2 A2
CMDC20 A12 DQU5 MDC48 CMDC20 A12 DQU5 MDC59
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDC4 T7 A3 MDC55 CMDC4 T7 A3 MDC61 CMD9 A0 A0
CMDC14 A14 DQU7 CMDC14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+MEM_VREF6 +1.5VSG +1.5VSG CMD10 A4 A4
DIS@
0.1U_0402_16V4Z

DIS@ 1 CMDC12 M2 B2 CMDC12 M2 B2 CMD11 A1 A1

R421 CMDC27 BA0 VDD CMDC27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
C 240_0402_1% CMDC26 CMDC26 C
M3 BA2 VDD G7 M3 BA2 VDD G7 CMD12 BA0 BA0
VDD K2 VDD K2
2
C364

VDD K8 VDD K8 CMD13 WE* WE*

VDD N1 VDD N1
CLKC1 J7 N9 CLKC1 J7 N9 CMD14 A15 A15
CLKC1# CK VDD CLKC1# CK VDD
K7 CK VDD R1 K7 CK VDD R1
CMDC19 K9 R9 CMDC19 K9 R9 CMD15 CAS* CAS*
CKE/CKE0 VDD +1.5VSG CKE/CKE0 VDD +1.5VSG
CMD16 CS0_H#
CMDC18 K1 A1 CMDC18 K1 A1
+1.5VSG CMDC16 ODT/ODT0 VDDQ CMDC16 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD17
CMDC30 J3 C1 CMDC30 J3 C1
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD18 ODT_H
DIS@ CMDC13 L3 D2 CMDC13 L3 D2
R422 WE VDDQ WE VDDQ
310mA VDDQ E9 310mA VDDQ E9 CMD19 CKE_H
240_0402_1% F1 F1
DQSC4 VDDQ DQSC5 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD20 A13 A13
DQSC6 C7 H9 DQSC7 C7 H9
DQSU VDDQ DQSU VDDQ
CMD21 A8 A8
+MEM_VREF7
DQMC4 E7 A9 DQMC5 E7 A9 CMD22 A6 A6
DML VSS DML VSS
DIS@
0.1U_0402_16V4Z

DIS@ 1 DQMC6 D3 B3 DQMC7 D3 B3

R423 DMU VSS DMU VSS
VSS E1 VSS E1 CMD23 A11 A11
240_0402_1% G8 G8
DQSC#4 VSS DQSC#5 VSS
2
G3 DQSL VSS J2 G3 DQSL VSS J2 CMD24 A5 A5
C365

DQSC#6 B7 J8 DQSC#7 B7 J8
DQSU VSS DQSU VSS
VSS M1 VSS M1 CMD25 A3 A3
VSS M9 VSS M9
VSS P1 VSS P1 CMD26 BA2 BA2
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1 CMD27 BA1 BA1
ZQ6 L8 T9 ZQ7 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
CMD28 A12 A12

1
1

J1 B1 DIS@ J1 B1 CMD29 A10 A10

DIS@ NC/ODT1 VSSQ R424 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
R425 J9 D1 243_0402_1% J9 D1 CMD30 RAS* RAS*
CLKC1 243_0402_1% NC/CE1 VSSQ NC/CE1 VSSQ
21 CLKC1 L9 D8 L9 D8

2
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 Not Available
2

VSSQ VSSQ
1

VSSQ E8 VSSQ E8
DIS@ F9 F9 LOW HIGH
R427 VSSQ VSSQ
VSSQ G1 VSSQ G1
160_0402_1% G9 G9
VSSQ VSSQ
2

CLKC1# 96-BALL 96-BALL

21 CLKC1#
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSG
+1.5VSG
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C371

C372

C373

C374

C375

C376

DIS@ C381

DIS@ C382

DIS@ C383

DIS@ C384

DIS@ C385
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@ C367

DIS@ C368

DIS@ C369

DIS@ C370

DIS@ C377

DIS@ C378

DIS@ C379

DIS@ C380
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019G8
Date: Monday, February 13, 2012 Sheet 28 of 61
5 4 3 2 1
 5 4 3 2 1

+VCCP to +1.05VSG
+1.5V to +1.5VSG +VCCP +1.05VSG
+1.5V +1.5VSG U20
U21 AO4304L_SO8
AO4304L_SO8 8 1
8 1 7 2

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
7 2 6 3 1 1

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
6 3 1 1 1 1 5 C386 C387
D 1 1 5 C388 C389 R430 R429 D

C390

C391
10_0603_5% DIS@ ER1019 DIS@ DIS@ 10_0603_5%

4
2 2

C392

C393
DIS@ DIS@ DIS@ DIS@ DIS@

1
2 2 2 2

1
2 2 DIS@ DIS@

1
DIS@ DIS@ D Q14

3
2 VGA_PWROK#
G DIS@
DIS@ +VSBP 1 2 1.05VSG_GATE S

3
+VSBP 1 2 1.5VSG_GATE Q80B 5 VGA_PWROK# R431 100K_0402_5% 2N7002KW 1N SOT323-3

470K_0402_5%
R432 DIS@ 2N7002KDWH_SOT363-6 DIS@

1
470K_0402_5%
100K_0402_5% 1

4
1

6
PR-3 1 C394

6
PR-7 R831 DIS@
R830 C395 R433 0.1U_0402_25V6
R434 0.01U_0402_25V7K VGA_PWROK# Q79A 2
2 1 2

2
VGA_PWROK# 2 DIS@ 0_0402_5% DIS@
2 1 2

2
DIS@

1
PR-7 0_0402_5% Q80A 1 2N7002KDWH_SOT363-6

1
1 2N7002KDWH_SOT363-6 PR-3
C396
C397 0.1U_0402_16V7K
0.1U_0402_16V7K @ 2 PR-9
@ 2

PR-9

+3VALW +3VALW
+3VS to +3VSG
+3VS Q3 +3VSG
AO3404AL_SOT23

1
C C

S
1 3
R665 R711

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
DIS@ 1 1 100K_0402_5% 100K_0402_5%
1 1 C398 C399 R435 DIS@ DIS@
G
2

2
DIS@ DIS@ DIS@ VGA_PWROK# DGPU_PWR_EN#
23 DGPU_PWR_EN#
C400

C401

200_0603_5%

1
2 2 D

1
2 2 DGPU_PWR_EN Q59
15,53 DGPU_PWR_EN 2
DIS@ DIS@ Q79B G DIS@

3
VGA_PWROK 5 DIS@ S
40,53 VGA_PWROK

3
1
2N7002KW 1N SOT323-3
DIS@ Q78B 2N7002KDWH_SOT363-6 R712

4
1
+VSBP 1 2 3VSG_GATE DIS@ 5 DGPU_PWR_EN# DIS@
R436 100K_0402_5% 2N7002KDWH_SOT363-6 R666 10K_0402_5%
470K_0402_5%

DIS@

2
1

1 10K_0402_5%
6

C402

2
PR-7 R119 DIS@
R437 0.1U_0402_25V6
DGPU_PWR_EN# Q78A 2
2 1 2
2

DIS@
0_0402_5% 2N7002KDWH_SOT363-6
1

1
C403
0.1U_0402_16V7K @
2

B B

For EMI

+1.5VSG +1.5VSG
+VCC_CORE +VCC_CORE

1 C712
2 1 C719 2
@ @
100P_0402_50V8J 100P_0402_50V8J
+5VALW +5VALW

1 C713
2 2 1 C720
@ @
100P_0402_50V8J 100P_0402_50V8J
+3VALW +3VALW

2 1 C714 2 1 C721
@ @
100P_0402_50V8J 100P_0402_50V8J

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/12/05 Deciphered Date 2012/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 29 of 61
5 4 3 2 1
 5 4 3 2 1

D6
BLUE 2
1
CRT GREEN 3

YSDA0502C 3P C/A SOT-23

D7
L15
PCH_CRT_RED RED RED +CRT_VCC
14 PCH_CRT_RED 1 2
CHILISIN NBQ160808T-800Y-N 0603
2 +5VS W=40mils
1
+CRT_VCC 3 L14 @ W=40mils
L16 2 1+5VS_CRTVCC 1 2
PCH_CRT_GRN 1 2 GREEN
14 PCH_CRT_GRN YSDA0502C 3P C/A SOT-23
CHILISIN NBQ160808T-800Y-N 0603 D8 SMD1812P075TF .75A 13.2V

0.1U_0402_16V4Z
RB491D_SOT23-3

0.1U_0402_16V4Z
D 1 1 D
L17 C404 C405
D9
PCH_CRT_BLU 1 2 BLUE @ @
14 PCH_CRT_BLU
CHILISIN NBQ160808T-800Y-N 0603 HSYNC_L 2
2 2
1

150_0402_1%

150_0402_1%

150_0402_1%
VSYNC_L

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
3

1
1 1 1 1 1 1
R438 R439 R440 C406 C407 C408 C409 C410 C411
YSDA0502C 3P C/A SOT-23

2 2 2 2 2 2
D10

2
VGA_DDC_DATA_C 2
1
VGA_DDC_CLK_C 3

YSDA0502C 3P C/A SOT-23

+CRT_VCC
+5VS

PR-7
ESD T36 CRTTEST
6
11
JCRT1
2

RED 1
R731 7
0_0402_5% VGA_DDC_DATA_C 12
+3VS GREEN 2
+5VS_CRTVCC +5VS_CRTVCC
8 G 16
1

HSYNC_L 13 17
G
R441 10K_0402_5% BLUE 3
1 2 2 1 9
C412 VSYNC_L 14
5
1

0.1U_0402_16V4Z 4
10
P
OE#

2
4.7K_0402_5%

4.7K_0402_5%
PCH_CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC_L VGA_DDC_CLK_C 15
14 PCH_CRT_HSYNC A Y R442 10_0402_5% 5
16 CRT_DET#
G

U23 R733 R732

SN74AHCT1G125GW_SOT353-5 SUYIN_070546FR015S251ZR
3

100P_0402_50V8J
CONN@

1
2
G
C 1 C
R734 C414
1 2 14 PCH_CRT_DDC_DAT PCH_CRT_DDC_DAT 3 1 VGA_DDC_DATA_C 100K_0402_5%
C413

1
5
1

2
2

G
0.1U_0402_16V4Z BSS138_SOT23
P
OE#

PCH_CRT_VSYNC D_CRT_VSYNC 1 VSYNC_L PCH_CRT_DDC_CLK Q21 VGA_DDC_CLK_C

14 PCH_CRT_VSYNC 2 A Y 4 2 14 PCH_CRT_DDC_CLK 3 1
R446 10_0402_5%

D
1 1 +5VS
G

U24 1 1 BSS138_SOT23

10P_0402_50V8J

10P_0402_50V8J
SN74AHCT1G125GW_SOT353-5 @ C417 @ C418
3

@ C419 @ C420 Q22 470P_0402_50V8J 470P_0402_50V8J

1 1 2 2
33P_0402_50V8K 33P_0402_50V8K
@ C415 @ C416 2 2

2 2

680P_0402_50V7K
LCD POWER CIRCUIT

C421
+LCDVDD +LCDVDD +3VS
+5VALW Q23
SI2301BDS-T1-E3_SOT23-3

2
PR-13 @
1

+LCDVDD
S

1 3
D

R448
4.7U_0603_10V4Z

1
R447 47K_0402_5% W=60mils JLVDS1
100_0805_5% C422 1 W=80mils 41 42 W=80mils
G
2

4.7U_0603_10V4Z L18 B+_L GMD GND

B+ 1 2 39 40 +LCDVDD
6 2

2 C423 FBMA-L11-201209-221LMA30T_0805 39 40
1 1 37 37 38 38
C424 C425 35 36
2 35 36
+3VS 33 33 34 34
0.1U_0402_16V4Z 0.1U_0402_16V4Z R449 +3VS 31 32
2 2 0.047U_0402_16V7K PR-13 31 32 PCH_TZOUT1-
0.1U_0402_16V4Z

B
2 2 1 29 29 30 30 PCH_TZOUT1- 14 B
220K_0402_1% @ 1 PCH_TXOUT0+ 27 28 PCH_TZOUT1+
2N7002KDWH_SOT363-6 14 PCH_TXOUT0+ 27 28 PCH_TZOUT1+ 14
C427 C426 PCH_TXOUT0- 25 26
14 PCH_TXOUT0-
1

25 26
3

Q1A 23 24 PCH_TZOUT2+
23 24 PCH_TZOUT2+ 14
PCH_TXOUT1+ 21 22 PCH_TZOUT2-
2 14 PCH_TXOUT1+ 21 22 PCH_TZOUT2- 14
PCH_TXOUT1- 19 20
14 PCH_TXOUT1- 19 20
14 PCH_ENVDD 1 2 5 17 18 PCH_TZOUT0-
17 18 PCH_TZOUT0- 14
R450 0_0402_5% PCH_TXOUT2+ 15 16 PCH_TZOUT0+
14 PCH_TXOUT2+ 15 16 PCH_TZOUT0+ 14
2N7002KDWH_SOT363-6 PCH_TXOUT2- 13 14
14 PCH_TXOUT2-
4

13 14
1

PR-7 Q1B 11 12 PCH_TZCLK-

11 12 PCH_TZCLK- 14
R451 PCH_TXCLK- 9 10 PCH_TZCLK+
14 PCH_TXCLK- 9 10 PCH_TZCLK+ 14
PCH_TXCLK+ 7 8
14 PCH_TXCLK+ 7 8
100K_0402_5% 5 6 PCH_LCD_CLK PCH_LCD_CLK 14
INVTPWM 5 6 PCH_LCD_DATA
3 4 PCH_LCD_DATA 14
2

DISPOFF# 3 4 CABC_SAVING
1 1 2 2 CABC_SAVING 16
ACES_87242-4001-09
CONN@

+3VS
Camera
60mil Q54
Panel PWM Control JCM1
1

1
B+ SI3457BDV-T1-E3_TSOP6~D 60mil R454 USB20_N3_L
+3VS
2
1
2
+B+_Q R729 1 @ 2 0_0805_5% B+_L 4.7K_0402_5% USB20_P3_L 3
D

@ DMIC_CLK 3
6 4
S

@ 33 DMIC_CLK 4
4 5 IRT-1 DMIC_DATA 5 7
33 DMIC_DATA
2

5 G1
2 6 6 G2 8

2
1000P_0402_50V7K~D
C613

100K_0402_5%~D
R728

1 0_0402_5% R457 1
1

1 1 1 2 INVTPWM 2 R820 1 0_0402_5% R452 R453 ACES_87213-0600G

40 EC_INV_PWM
@ C544 @ 33_0402_5% 33_0402_5% CONN@
3

@ @ @ C654 22P_0402_50V8J @ @
0.1U_0603_50V_X7R 2 WCM-2012HS-900T
14 PCH_INV_PWM 2 1 @

1
2 2 R458 0_0402_5% USB20_N3_L
15 USB20_N3 4 3
2

4 3
PWR_SRC_ON PR-7 1 1
A 15 USB20_P3 1 2 USB20_P3_L A
1 2
1

C428 C429
R28 L40 22P_0402_50V8J 22P_0402_50V8J
1 2 2
@ 100K_0402_5%
Panel Backlight Control IRT-1 C545 2 R821 1 0_0402_5%
@ @
22P_0402_50V8J @
2

2
@
R727
1

0_0402_5% @ D R455 33_0402_5%

+LCDVDD 2 1 2 Q31 BKOFF# 1 2 DISPOFF#
40 BKOFF#
@ G 2N7002KW 1N SOT323-3
Security Classification Compal Secret Data Compal Electronics, Inc.
1

S
3

R456 2011/08/23 2012/12/31 Title

10K_0402_5%
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 30 of 61
5 4 3 2 1
 A B C D E F G H

+3VS ASM1466 +3VS +3VS

70mA 0_0402_5% 1 @ 2R426
HDD-SATA Redriver R459 1
@
2 4.7K_0402_5% 7
U41
EN
@
VDD 6
0_0402_5%
VDD 16 1 @ 2R405 Place caps. Place caps.
SATA_PTX_DRX_P00.01U_0402_16V7K 1 2 C430 SATA_PTX_DRX_P0_R 1 +3VS
12 SATA_PTX_DRX_P0 A_INp near U41 near U42
SATA_PTX_DRX_N0 0.01U_0402_16V7K 1 2 C433 SATA_PTX_DRX_N0_R 2 10
12 SATA_PTX_DRX_N0 A_INn NC
REXT 20 1 R668 2 @
SATA_PRX_DTX_P00.01U_0402_16V7K 1 2 C432 SATA_PRX_DTX_P0_R 5 2K +-1% 0402 ASM1466
12 SATA_PRX_DTX_P0 B_OUTp
SATA_PRX_DTX_N0 0.01U_0402_16V7K 1 2 C431 SATA_PRX_DTX_N0_R 4 9 SATA0_A_PRE0
12 SATA_PRX_DTX_N0 B_OUTn A_PRE0

0.1U_0402_16V7K
C639

0.01U_0402_16V7K
C638

1U_0603_10V6K
C643

0.1U_0402_16V7K
C642

0.01U_0402_16V7K
C641
8 SATA0_B_PRE0 PS8520 1 1 1 1 1
+3VS SATA0_B_PRE1 B_PRE0
17 B_PRE1
SATA0_A_PRE1 19 15 SATA_PTX_C_DRX_P0_R
PIN7 & PIN18 have internal PD A_PRE1 A_OUTp SATA_PTX_C_DRX_N0_R
A_OUTn 14
R736 1 @ 2 2 2 2 2
2 18 TEST
1 4.7K_0402_5% SATA_PRX_C_DTX_P0_R 1
3 GND B_INp 11

2
13 12 SATA_PRX_C_DTX_N0_R
R667 GND B_INn
21 EPAD
@ 0_0402_5%
PS8520BTQFN20GTR2_TQFN20_4X4 +3VS

1
+3VS ASM1466 +3VS 0_0402_5% 1 @ 2 R419
HDD-SATA Redriver @ U42 @
70mA
SATA HDD BTB Conn.
R669 1 2 4.7K_0402_5% 7 EN VDD 6 0_0402_5% 1 @ 2 R403 ASM1466
VDD 16
SATA_PTX_DRX_P10.01U_0402_16V7K 1 2 C434 SATA_PTX_DRX_P1_R 1
12 SATA_PTX_DRX_P1 A_INp
SATA_PTX_DRX_N1 0.01U_0402_16V7K 1 2 C437 SATA_PTX_DRX_N1_R 2 10
12 SATA_PTX_DRX_N1 A_INn NC
REXT 20 1 R671 2 @ JHDD1
SATA_PRX_DTX_P10.01U_0402_16V7K 1 2 C436 SATA_PRX_DTX_P1_R 5 2K +-1% 0402 SATA_PTX_DRX_P00_0402_5% 1 @ 2 R699 SATA_PTX_C_DRX_P0_R 1 2
12 SATA_PRX_DTX_P1 B_OUTp 1 2 +5VS
SATA_PRX_DTX_N1 0.01U_0402_16V7K 1 2 C435 SATA_PRX_DTX_N1_R 4 9 SATA1_A_PRE0 PS8520 SATA_PTX_DRX_N0 0_0402_5% 1 @ 2 R700 SATA_PTX_C_DRX_N0_R 3 4
12 SATA_PRX_DTX_N1 B_OUTn A_PRE0 3 4
8 SATA1_B_PRE0 5 6
+3VS SATA1_B_PRE1 B_PRE0 SATA_PRX_DTX_N0 0_0402_5% SATA_PRX_C_DTX_N0_R 5 6
17 B_PRE1 1 @ 2 R701 7 7 8 8
SATA1_A_PRE1 19 15 SATA_PTX_C_DRX_P1_R SATA_PRX_DTX_P00_0402_5% 1 @ 2 R702 SATA_PRX_C_DTX_P0_R 9 10
PIN7 & PIN18 have internal PD A_PRE1 A_OUTp SATA_PTX_C_DRX_N1_R 9 10
A_OUTn 14 11 11 12 12
R738 1 @ 2 18 SATA_PTX_DRX_P10_0402_5% 1 @ 2 R703 SATA_PTX_C_DRX_P1_R 13 14
TEST 13 14 +3VS
4.7K_0402_5% 3 11 SATA_PRX_C_DTX_P1_R SATA_PTX_DRX_N1 0_0402_5% 1 @ 2 R704 SATA_PTX_C_DRX_N1_R 15 16
GND B_INp 15 16
2

13 12 SATA_PRX_C_DTX_N1_R 17 18
GND B_INn SATA_PRX_DTX_N1 0_0402_5% 17 18
21 EPAD 1 @ 2 R705 SATA_PRX_C_DTX_N1_R 19 19 20 20
@ R670 SATA_PRX_DTX_P10_0402_5% 1 @ 2 R706 SATA_PRX_C_DTX_P1_R 21 22
0_0402_5% PS8520BTQFN20GTR2_TQFN20_4X4 21 22
23 23 24 24
25 26
1

25 26
27 27 28 28
29 30

GND
GND
GND
GND
GND
GND
29 30
Co-lay with redriver
ACES_88018-304G

31
32
33
34
35
36
2 CONN@ 2

Add EQ pin for PS8520BTQFN20GTR2 FOR SATA0 Add EQ pin for PS8520BTQFN20GTR2 FOR SATA1
+3VS +3VS
SATA0_B_PRE11@ R676 2 SATA1_B_PRE11@ R684 2
0_0402_5% 0_0402_5%
SATA0_A_PRE11@ R679 2 SATA0_B_PRE1 1@ R680 2 4.7K_0402_5% SATA1_A_PRE11@ R687 2 SATA1_B_PRE1 1@ R688 2 4.7K_0402_5%
0_0402_5% 0_0402_5%
ASM1466 SATA0_A_PRE1 1@ R677 2 4.7K_0402_5% SATA1_A_PRE1 1@ R685 2 4.7K_0402_5%
+5VS Q24
SATA0_A_PRE01 R682 2 SATA0_A_PRE0 1@ R675 2 4.7K_0402_5% SATA1_A_PRE01 R690 2 SATA1_A_PRE0 1@ R683 2 4.7K_0402_5% SI3456DDV-T1-GE3_TSOP6
@ 2K_0402_1% PS8520 @ 1.5K_0402_5% R460

D
SATA0_B_PRE0 1@ R681 2 4.7K_0402_5% PR-10 ASM1466 SATA1_B_PRE0 1@ R689 2 4.7K_0402_5% 6

S
PS8520 1 5 4 +5VS_ODD_R 1 2 +5VS_ODD
SATA0_B_PRE01@ R678 2 SATA1_B_PRE01@ R686 2 C439 2
0_0402_5% 0_0402_5% 1U_0402_6.3V6K 1 0_1206_5%

G
2
Placea caps. near ODD CONN.

3
+5VS_ODD 0.1U_0402_16V4Z
+VSBP
+3VS
1 1 1 C447 1
ODD-SATA Redriver C445 C446 C448

1
+3VS +3VS 0_0402_5%

10U_0805_10V6K
ASM1466 1 @ 2 R396

1U_0402_6.3V6K
70mA R461
@ U43 @ 2 2 2 2
330K_0402_5%
R672 1 2 4.7K_0402_5% 7 6 0_0402_5% 1 @ 2 R417
EN VDD 1000P_0402_50V7K
16

2
SATA_PTX_DRX_P20.01U_0402_16V7K @1 VDD
12 SATA_PTX_DRX_P2 2 C438 SATA_PTX_DRX_P2_R 1 A_INp
ODD_EN
3 SATA_PTX_DRX_N2 0.01U_0402_16V7K @1 3
12 SATA_PTX_DRX_N2 2 C637 SATA_PTX_DRX_N2_R 2 A_INn NC 10

2
D

1.5M_0402_5%

0.1U_0402_25V6
20 1 R674 2 @ ASM1466 1
SATA_PRX_DTX_P20.01U_0402_16V7K @1 REXT
12 SATA_PRX_DTX_P2 2 C636 SATA_PRX_DTX_P2_R 5 B_OUTp
4.99K_0402_1%
16 ODD_EN# 2 Q25
SATA_PRX_DTX_N2 0.01U_0402_16V7K @1 2 C635 SATA_PRX_DTX_N2_R 4 9 SATA2_A_PRE0 G 2N7002KW 1N SOT323-3 R462 C444
12 SATA_PRX_DTX_N2 B_OUTn A_PRE0
8 SATA2_B_PRE0 S

3
+3VS SATA2_B_PRE1 B_PRE0 2
17

1
SATA2_A_PRE1 B_PRE1 SATA_PTX_C_DRX_P2_R
19 A_PRE1 A_OUTp 15
PIN7 & PIN18 have internal PD 14 SATA_PTX_C_DRX_N2_R
R740 1 @ A_OUTn
2 18 TEST
4.7K_0402_5% 3 11 SATA_PRX_C_DTX_P2_R
GND B_INp
2

13 12 SATA_PRX_C_DTX_N2_R
GND B_INn
21 EPAD
@ R673
0_0402_5% PS8520BTQFN20GTR2_TQFN20_4X4
SATA ODD Conn.
1

JODD1

SATA_PTX_DRX_P2 0_0402_5% 1 2 R707 SATA_PTX_C_DRX_P2_R 13

SATA_PTX_DRX_N2 0_0402_5% SATA_PTX_C_DRX_N2_R SATA_PTX_C_DRX_P2_R SATA_PTX_DRX_P2_C GND
1 2 R708 C440 1 2 0.01U_0402_16V7K 12 A+
SATA_PTX_C_DRX_N2_R C441 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N2_C 11
SATA_PRX_DTX_P2 0_0402_5% A-
1 2 R709 SATA_PRX_C_DTX_P2_R 10 GND
SATA_PRX_DTX_N2 0_0402_5% 1 2 R710 SATA_PRX_C_DTX_N2_R SATA_PRX_C_DTX_N2_R C442 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N2_C 9
SATA_PRX_C_DTX_P2_R C443 1 B-
2 0.01U_0402_16V7K SATA_PRX_DTX_P2_C 8 B+
Co-lay with redriver 7 GND
PR-7
1 2 ODD_DETECT#_R 6
16 ODD_DETECT# DP
R463 0_0402_5% 5
+5VS_ODD V5
80mils ODD_DA#_R
4 V5
Add EQ pin for PS8520BTQFN20GTR2 FOR SATA2 15 ODD_DA# 1 2 3 MD
Place caps. R464 0_0402_5% 2
+3VS GND
1 GND
4 +3VS near U43 4
SATA2_B_PRE11@ R692 2 PR-7
0_0402_5% SUYIN_127382FR013G109ZR_RV
SATA2_A_PRE11@ R695 2 SATA2_B_PRE1 1@ R696 2 4.7K_0402_5% CONN@
1U_0603_10V6K
C646

0.1U_0402_16V7K
C645

0.01U_0402_16V7K
C644

0_0402_5% 1 1 1
ASM1466 SATA2_A_PRE1 1@ R693 2 4.7K_0402_5%
@ @ @
SATA2_A_PRE01 R698 2 SATA2_A_PRE0 1@ R691 2 4.7K_0402_5%
@ 2K_0402_1%
SATA2_B_PRE0 1@ R697
2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2 4.7K_0402_5% Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title

SATA2_B_PRE01@ R694 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 31 of 61
A B C D E F G H
 5 4 3 2 1

+LAN_IO
W=60mils W=60mils +LAN_VDD

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
+3VALW R465
+LAN_IO 1.5A 470_0603_5% 1 1 1 1 1 1 1
Q26

D
3 1 W=20mils C449 C450 C451 C452 C453 C454 C455

1
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1 +LAN_IO_DISC
C456 2 2 2 2 2 2 2
1 1 1 1 1 1

3
1U_0402_6.3V6K AO3419L 1P SOT23-3

G
2
C457 C458 C459 C460 C461 C462
+5VALW 2
D 2 2 2 2 2 2 EN_WOL# D
5
Q81B These caps close to Pin 3,6,9,13,29,41,45

2
2N7002KDWH_SOT363-6

4
R466
100K_0402_5%

R467 These caps close to Pin 12,27,39,42,47,48

1

1 2 EN_WOL#
220K_0402_5%~N +LAN_IO W=40mils W=20mils
6

1 R468 +LAN_VDD
C463 +LAN_IO 1 2 +LAN_VDDREG R469

0.1U_0402_16V7K
4.7U_0603_6.3V6K
Q81A 0.1U_0603_25V7K 1 2 +LAN_EVDD10

0.1U_0402_16V7K

1U_0402_6.3V6K
2 0_0603_5% 1 1
40 EN_WOL 2
2N7002KDWH_SOT363-6 0_0603_5%

2
PR-7 C464 C465 1 1
1
2

R471 PR-7
R470 10K_0402_5% 2 2 C466 C467
10K_0402_5%

2
2 2

1
1

14,36,41 PCIE_WAKE# 1 3 LAN_WAKE#

S
U25 2N7002KW 1N SOT323-3
Q29
C468 1 20.1U_0402_16V7K PCIE_PRX_C_GLANTX_P1 22 31 R472
13 PCIE_PRX_GLANTX_P1 HSOP LED3/EEDO
37 1 2 1 2 XTLI
C470 1 PCIE_PRX_C_GLANTX_N1 LED1/EESK
13 PCIE_PRX_GLANTX_N1 20.1U_0402_16V7K 23 HSON LED0 40 3
C469 0_0402_5%
17 30 R473 1 2 10K_0402_5% 12P_0402_50V8J PR-7
13 PCIE_PTX_GLANRX_P1 HSIP EECS/SCL 3
13 PCIE_PTX_GLANRX_N1 18 HSIN EEDI/SDA 32 R474 1 2 10K_0402_5% L19
+LAN_VDD
GND 4
C +LAN_SROUT1.05 C
W=60mils 1 2 W=60mils

0.1U_0402_16V7K

4.7U_0603_6.3V6K
16 1 LAN_MDIP0 Y4
13 LANCLK_REQ# CLKREQB MDIP0
2 LAN_MDIN0 2.2UH +-5% NLC252018T-2R2J-N 1 1
MDIN0 LAN_MDIP1
5,15,36,40,41 PLT_RST# 25 PERSTB MDIP1 4 GND 2
5 LAN_MDIN1 C471 C472
MDIN1 LAN_MDIP2 25MHZ_20PF_7V25000016
13 CLK_PCIE_LAN 19 REFCLK_P NC/MDIP2 7
LAN_MDIN2 2 2 1
13 CLK_PCIE_LAN# 20 REFCLK_N NC/MDIN2 8
10 LAN_MDIP3
NC/MDIP3 LAN_MDIN3 1
NC/MDIN3 11
XTLO 43 1 2 XTLO
CKXTAL1 C473
XTLI 44 13 +LAN_VDD These components close to Pin 36 12P_0402_50V8J
CKXTAL2 DVDD10
DVDD10 29 ( Should be place within 200 mils )
DVDD10 41
LAN_WAKE# 28
R475 LANWAKEB

+3VS 1 2 ISOLATEB 26 27
ISOLATEB DVDD33
DVDD33 39
1K_0402_5%
14 NC/SMBCLK AVDD33 12 +LAN_IO
2

R476 1 2 10K_0402_5% 15 42
R477 R478 1 NC/SMBDATA AVDD33
+LAN_IO 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47
15K_0402_5% 48
PR-7 AVDD33 JLAN1
+LAN_IO R479 1 2 0_0402_5% 33
1

ENSWREG +LAN_EVDD10
EVDD10 21 SHLD1 9
3.3V : Enable switching regulator 34 RJ45_TX3- 8
0V : Disable switching regulator +LAN_VDDREG VDDREG PR4-
35 VDDREG AVDD10 3 +LAN_VDD
6 RJ45_TX3+ 7
AVDD10 PR4+
AVDD10 9
R480 1 2 2.49K_0402_1% 46 45 RJ45_RX1- 6
RSET AVDD10 PR2-
B +LAN_SROUT1.05 RJ45_TX2- B
24 GND REGOUT 36 5 PR3-
49 PGND RJ45_TX2+ 4 PR3+
RTL8111F-CGT QFN 48P RJ45_RX1+ 3 PR2+
TS1 RJ45_TX0- 2 PR1-
+V_DAC 1 24 R481 1 2 75_0603_1% RJ45_TX0+ 1 10
LAN_MDIP0 TCT1 MCT1 RJ45_TX0+ R482 75_0603_1% PR1+ SHLD2
2 TD1+ MX1+ 23 1 2

2
LAN_MDIN0 3 22 RJ45_TX0- R483 1 2 75_0603_1%
TD1- MX1- R484 75_0603_1% D15
1 2

2
+V_DAC 4 21 SANTA_130452-07
LAN_MDIP1 TCT2 MCT2 RJ45_RX1+ PR-17
5 TD2+ MX2+ 20 CONN@ @

1
C474 1 2 LAN_MDIN1 6 19 RJ45_RX1- 2
TD2- MX2-

1
0.01U_0402_16V7K +V_DAC 7 18 C475
LAN_MDIP2 TCT3 MCT3 RJ45_TX2+ AZC199-02SPR7G_SOT23-3
8 TD3+ MX3+ 17 10P_1206_2KV8J
LAN_MDIN2 RJ45_TX2- 1
9 TD3- MX3- 16

+V_DAC
LAN_MDIP3
LAN_MDIN3
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
RJ45_TX3+
RJ45_TX3- LAN_MDIP1 6
D16
I/O4 I/O2 3 LAN_MDIP0
ESD LAN_MDIP3 6
D17
I/O4 I/O2 3 LAN_MDIP2

10/01 EMI Request

SP050007G00
FORM_ NS892409 D18 @ LSE-200NX3216TRLF_1206-2 +LAN_IO 5 2 +LAN_IO 5 2
VDD GND VDD GND
1 2

D19 @ LSE-200NX3216TRLF_1206-2
1 2 LAN_MDIN1 4 1 LAN_MDIN0 LAN_MDIN3 4 1 LAN_MDIN2
I/O3 I/O1 I/O3 I/O1
A D20 @ LSE-200NX3216TRLF_1206-2 AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6 A
2 1 LANGND 1 2
C219 0.1U_0603_25V7K
D21 @ LSE-200NX3216TRLF_1206-2
1 2

2 1 LANGND
C300 0.1U_0603_25V7K Security Classification Compal Secret Data Compal Electronics, Inc.
ESD Issued Date 2011/1212 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
2012/11/22 Title
SCHEMATIC A8222
Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 32 of 61
5 4 3 2 1
 A B C D E F G H

+5VS_PVDD
EMI SPKOUT_L1
close to JSPK1

R487 1 SPK_L1
2 0_0603_5% 1 2
R488 1 C476 0.22U_0603_16V7K
+5VS 2 1 @

10U_0805_10V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
@ C477 1U_0603_10V6K
0_0805_5% 1 1 1
SPKOUT_L2 R489 1 SPK_L2 2
2 0_0603_5% 1 2
PR-7 C479 C480 C481 C478 0.22U_0603_16V7K
@
PR-7 2 2 2 JSPK1
SPK_R1 1
1 R491 SPKOUT_R1 R490 1 SPK_R1 SPK_R2 1 1
2 0_0603_5% 1 2 2 2
+3VS_DVDD 2 1 +3VS_DVDD_R 1 C482 0.22U_0603_16V7K SPK_L1 3 5
3 G1

10U_0603_6.3V6M
@ SPK_L2 4 6
4 G2

0.1U_0402_16V7K
0_0603_5% 1 1 @ C483 1U_0603_10V6K
ACES_88266-04001
C484 C485 SPKOUT_R2 R492 1 SPK_R2 2
2 0_0603_5% 1 2 CONN@
C486 0.22U_0603_16V7K
DMIC_DATA 2 2
@
+5VS_PVDD +VDDA
1 L20
+3VS_DVDD
2 1 +5VS

2
10U_0805_10V6K
0.1U_0402_16V7K

0.1U_0402_16V7K
C487 R493 1 1 1 MBK1608800YZF 0603
22P_0402_50V8J +3VS 2 1 D22 D23
2 10U_0603_6.3V6M

0.1U_0402_16V7K
@ C488 C489 C490
0_0603_5% 1 1 2 2 2
EMI PR-7 C491 C492

1
YSDA0502C 3P C/A SOT-23 YSDA0502C 3P C/A SOT-23
2 2

10P_0402_50V8J
DMIC_CLK

39

46

25

38
1

9
U26 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO
1 2
ESD @ @

DVDD

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2

0_0402_5%
C493 C494

1
22P_0402_50V8J
2 @ 1 R494
@
23 40 SPKOUT_L1 @
LINE1_L SPK_OUT_L+ SPKOUT_L2
24 LINE1_R SPK_OUT_L- 41 EMI

22P_0402_50V8J
14 45 SPKOUT_R1
LINE2_L SPK_OUT_R+

10P_0402_50V8J
15 44 SPKOUT_R2 1 2.2K_0402_1%
LINE2_R SPK_OUT_R- HDA_SYNC_AUDIO R497 1 2 +MIC1_VREFO_R
MIC1 1 R495 2 MIC1_R 1 2 C495 4.7U_0603_6.3V6K MIC1_C 21 32 HP_OUTL 2 C496 R498 1 2
2 MIC1_L HP_OUT_L +MIC1_VREFO_L 2
1K_0402_5% MIC2_C 22 33 HP_OUTR 2.2K_0402_1% JAU1
MIC2 MIC1_R HP_OUT_R 2
1 R496 2 MIC2_R 1 2 C497 4.7U_0603_6.3V6K C498 @ 26 GND2
1K_0402_5% 16 25
MIC2_L @ 1 GND1
17 MIC2_R
10 HDA_SYNC_AUDIO MIC_JD 24
SYNC HDA_SYNC_AUDIO 12 24
MIC2 23
DMIC_DATA R499 1 23
30 DMIC_DATA 2 0_0402_5% DMIC_DATA_CODEC 2 GPIO0/DMIC_DATA BCLK 6 HDA_BITCLK_AUDIO
HDA_BITCLK_AUDIO 12 22 22
MIC1 HP_JD 21
DMIC_CLK DMIC_CLK_CODEC HP_OUTR 21
30 DMIC_CLK 1 2 3 GPIO1/DMIC_CLK 20 20
L21 FBMA-L10-160808-301LMT_2P 5 HDA_SDOUT_AUDIO HP_OUTL 19
SDATA_OUT HDA_SDOUT_AUDIO 12 19
18 18
EC_MUTE# R500 1 2 0_0402_5% PD# 4 8 HDA_SDIN_AUDIO1 R501 2 HDA_SDIN0 12 2 R556 1 0_0402_5% 17
40 EC_MUTE# PR-7 PD# SDATA_IN 17
33_0402_5% @ 16 16
15 15
HDA_RST_AUDIO# 11 47 0_0402_5%1 2 R502 L34 (For USB Port5) 14
12 HDA_RST_AUDIO# RESET# EAPD EAPD 40 14
15 USB20_N5 1 1 2 2 13 13
48 USB20_N5_R 12
SPDIFO PR-7 USB20_P5_R 12
12 PCBEEP 11 11
MIC_JD 1 R503 2 20 15 USB20_P5 4 3 10
20K_0402_1% MONO_OUT 4 3 10
1 1 +USB_VCCC 9 9

1.8P_0402_50V8

1.8P_0402_50V8
HP_JD 2 R504 1 SENSE_A 13 WCM-2012HS-900T 8
39.2K_0402_1% SENSE A C726 C723 8
MIC2_VREFO 29 7 7
18 SENSE B 2 R552 1 @ @ +USB_VCCD 6 6
@ 0_0402_5% 2 2
MIC1_VREFO_R 30 +MIC1_VREFO_R 5 5
36 CBP LDO_CAP 28 4 4
PR-12 USB20_P2_R 3 3

10U_0805_10V6K
1 2 35 27 AC97_VREF (For USB Port2) USB20_N2_R 2
CBN VREF 2

10U_0805_10V6K

0.1U_0402_16V7K
C499 2.2U_0603_16V6K 1 EMI close to JAU1 1
AC_JDREF 1
+MIC1_VREFO_L 31 MIC1_VREFO_L JDREF 19 1 R505 2 1 1
20K_0402_1% C500 ACES_88514-02401-071
43 34 1 2 C502 C503 2 R749 1 0_0402_5% CONN@
PVSS2 CPVEE C501 2 @
42 PVSS1
3 2.2U_0603_16V6K @ 2 2 3
49 DVSS2 AVSS1 26
+3VS 7 37 L35
DVSS1 AVSS2 USB20_P2_R
15 USB20_P2 1 1 2 2
ALC269Q-VB5-GR_QFN48_7X7
1

15 USB20_N2 4 3 USB20_N2_R
4 3
@ 4.7K_0402_5% WCM-2012HS-900T
R506
1 1

1.8P_0402_50V8

1.8P_0402_50V8
2 R748 1 0_0402_5%
2

@ C724 C725
HDA_RST_AUDIO# R507 1 2 0_0402_5% 1 2 @ @ @
2 2
@1 R508 1 2 0_0402_5% C504 0.1U_0402_16V7K
0.1U_0402_16V7K
C508 R509 1 2 0_0402_5% 1 2 @
PR-12
2 R510 1 2 0_0402_5% C505 0.1U_0402_16V7K

1 2 @

C506 0.1U_0402_16V7K
1 2 @ EMI close to JAU1

C507 0.1U_0402_16V7K

For EMI (on MIC and Headphone AGND to connected with

DGND)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 33 of 61
A B C D E F G H
 5 4 3 2 1

Card Reader RTS5137 Card Reader Connector

(only SD/MMC/MS function)
D D
+3VS +3VS_CR +CARDPWR

30mil JCR1
R633 2 1 0_0603_5%
PR-7 5
@ SDCMD VDD
3 CMD
2 1 12mil SDCLK 6
C615 100P_0402_50V8J U40 CLK
4 VSS
R723 1 2 +RREF 1 7
6.2K_0603_1% REFE @ VSS
GPIO0 17 1 2 1 2
USB20_N4_L 2 R636 10_0402_5% @ C614 10P_0402_50V8J SDD0 8
USB20_P4_L DM CLK_SD_48M SDD1 DAT0
3 DP CLK_IN 24 CLK_SD_48M 13 9 DAT1
SDD2 1
+3VS_CR SDD3 DAT2
4 3V3_IN NC 23 2 CD/DAT3
PR-13 +CARDPWR
30mil 5 CARD_3V3
1U_0402_6.3V6K
4.7U_0603_10V4Z

0.1U_0402_16V4Z

1 2 +VREG 6 22 12
V18 SP14 SDD2 SDWP# GND SW
1 12mil SP13 21 10 WP SW GND SW 13
C619

7 20 SDD3 SDCD 11
NC SP12 CD SW
C623

C616

SP11 19
2 1 SDWP SDCMD
8 SP1 SP10 18
2 T-SOL_156-2000302604
9 SP2 SP9 16
SDD1 10 15 SDCLK_R 1 2 SDCLK
SP3 SP8

EPAD
SDD0 11 14 0_0402_5% R634 EMI
SP4 SP7 SDCD#
12 SP5 SP6 13

RTS5137-GR_QFN24_4X4

25
+3VS_CR +3VS_CR

C C
2 R822 1 0_0402_5%

1
+CARDPWR @ @

L41 R774 100K_0402_5%

30mil

1
1 2 USB20_N4_L 100K_0402_5% R768
15 USB20_N4 1 2

2
@ R775 SDWP R773 SDCD#

2
4 3 USB20_P4_L @ 1 1 1 100K_0402_5% 100K_0402_5%
15 USB20_P4 4 3

6
2

2
WCM-2012HS-900T R635 C617 C618 C622
100K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2
2 R823 1 0_0402_5% SDWP# 5 SDCD 2
1 Close to connector
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

1
Q20B Q20A

SDCLK C612 R632

2 1 1 2SDCLK
@ 33_0402_5% @
B 22P_0402_50V8J B

close JCR1
EMI EMI
22P_0402_50V8J

close U51
1
C621

@ 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 34 of 61
5 4 3 2 1
 5 4 3 2 1

D24 D25
HDMI_R_D1- 1 1 109 HDMI_R_D1- HDMI_R_D0+ 1 1 109 HDMI_R_D0+

HDMI_R_D1+ 2 2 98 HDMI_R_D1+ HDMI_R_D0- 2 2 98 HDMI_R_D0- +3VS

HDMI_R_D2- 4 4 77 HDMI_R_D2- HDMI_R_CK+ 4 4 77 HDMI_R_CK+

HDMI_R_D2+ 5 5 66 HDMI_R_D2+ HDMI_R_CK- 5 5 66 HDMI_R_CK-

1
D D
3 3 3 3 R663
1M_0402_5%
8 8

2
G
2
L15ESDL5V0NA-4 SLP2510P8 L15ESDL5V0NA-4 SLP2510P8 14 TMDS_B_HPD TMDS_B_HPD 3 1 HDMI_DETECT

D
For ESD request.

1
Q57 R638
2N7002KW 1N SOT323-3 20K_0402_5%

2
D26
HDMI_DETECT 6 3 HDMI_SDATA
I/O4 I/O2 U44

GND 2
+5VS 5 VDD GND 2
HDMI 46@ 1 IN

0.1U_0402_16V7K
1 OUT 3
+HDMI_5V_OUT 4 1 HDMI_SCLK C652
I/O3 I/O1

0.1U_0402_16V7K
1
AZC099-04S.R7G_SOT23-6 AP2330W-7_SC59-3 C653
2
HDMI ROYALTY For ESD request.
2
+5VS Q53

D
+HDMI_5V_OUT

S
6
4 5 F1
@ 1 2 +HDMI_5V 1 2
C626

1U_0603_10V6K

1U_0603_10V6K
@ 1 W=40mils0.5A 15VDC_FUSE

G
1
C628

3
C
2 SI3456BDV-T1-E3 1N TSOP6 C
@
+VSBP @
2

470K_0402_5%
1
R664
@

2
R645 604_0402_1% EN_HDMI
TMDS_GND 1 2 HDMI_R_D2-

1
D

1.5M_0402_5%
R649 604_0402_1% R643

0.1U_0402_16V7K
1
1 2 HDMI_R_D2+ 2 Q56 C634
36,41,42 SUSP
R646 604_0402_1% G 2N7002KW 1N SOT323-3
1 2 HDMI_R_D1- S @ @

3
R653 604_0402_1% @ 2

2
TMDS_B_CLK 2 1 HDMI_CK+ 1 2 HDMI_R_D1+
14 TMDS_B_CLK
TMDS_B_CLK# 0.1U_0402_16V7K 2 1 C625 HDMI_CK- R659 604_0402_1%
14 TMDS_B_CLK#
0.1U_0402_16V7K C624 1 2 HDMI_R_D0-
TMDS_B_DATA0 2 1 HDMI_D0+ R647 604_0402_1%
14 TMDS_B_DATA0
TMDS_B_DATA0# 0.1U_0402_16V7K 2 1 C630 HDMI_D0- 1 2 HDMI_R_D0+
14 TMDS_B_DATA0#
0.1U_0402_16V7K C631 R651 604_0402_1%
TMDS_B_DATA1 2 1 HDMI_D1+ 1 2 HDMI_R_CK- @
14 TMDS_B_DATA1
TMDS_B_DATA1# 0.1U_0402_16V7K 2 1 C633 HDMI_D1- R652 604_0402_1% HDMI_CK+ 1 2 HDMI_R_CK+
14 TMDS_B_DATA1#
0.1U_0402_16V7K C627 1 2 HDMI_R_CK+ R644 0_0402_5%
TMDS_B_DATA2 2 1 HDMI_D2+
14 TMDS_B_DATA2
TMDS_B_DATA2# 0.1U_0402_16V7K 2 1 C629 HDMI_D2-
14 TMDS_B_DATA2# For EMI
0.1U_0402_16V7K C632 4 3
4 3 +HDMI_5V_OUT
1

D R656
2 1 2 1 2 (pin 19) plug in 5V
+5VS 1 2
G Q55 10K_0402_5%
S L32 WCM-2012-121T_0805 JHDMI1
3

2N7002KW 1N SOT323-3 HDMI_DETECT 19

HDMI_CK- HDMI_R_CK- HP_DET
1 2 18 +5V
R648 @ 0_0402_5% 17
HDMI_SDATA DDC/CEC_GND
16 SDA
HDMI_SCLK 15
B
HDMI_D0- @ HDMI_R_D0- SCL B
1 2 14 Reserved
R658 0_0402_5% 13
HDMI_R_CK- CEC
12 CK- GND 20
11 CK_shield GND 21
1 2 HDMI_R_CK+ 10 22
1 2 HDMI_R_D0- CK+ GND
9 D0- GND 23
8 D0_shield
4 3 HDMI_R_D0+ 7
4 3 HDMI_R_D1- D0+
6 D1-
L31 WCM-2012-121T_0805
HDMI HDMI_R_D1+
5
4
D1_shield
HDMI_D0+ HDMI_R_D0+ HDMI_R_D2- D1+
1 2 3 D2-
R657 @ 0_0402_5% 2
+3VS +3VS +HDMI_5V_OUT HDMI_R_D2+ D2_shield
1 D2+
2.2K_0402_5%
R650
HDMI_D1+ 1 2 HDMI_R_D1+ SUYIN_100042GR019M26DZL
1 2 R660 R641 R639 @ 0_0402_5% CONN@
2
1
2.2K_0402_5%

2.2K_0402_5%

4 4 3 3
C707 2 1 2.2P_0402_50V8C HDMI_R_D2-
1
2

1 2 C706 2 1 2.2P_0402_50V8C HDMI_R_D2+

1 2
5

Q52B L33 WCM-2012-121T_0805 C705 2 1 2.2P_0402_50V8C HDMI_R_D1-

HDMICLK_NB 1 2 HDMI_L_SCLK 4 3 HDMI_SCLK RV91, RV92 place near JHDMI connect
14 HDMICLK_NB
R654 0_0402_5% HDMI_D1- 1 2 HDMI_R_D1- C704 2 1 2.2P_0402_50V8C HDMI_R_D1+
2N7002KDWH_SOT363-6 R662 @ 0_0402_5%
1 2 C703 2 1 2.2P_0402_50V8C HDMI_R_D0-

R640 HDMI_D2+ 1 2 HDMI_R_D2+ C702 2 1 2.2P_0402_50V8C HDMI_R_D0+

2.2K_0402_5% R661 @ 0_0402_5%
C700 2 1 2.2P_0402_50V8C HDMI_R_CK-
2

4 3 C701 2 1 2.2P_0402_50V8C HDMI_R_CK+

Q52A 4 3

14 HDMIDAT_NB HDMIDAT_NB R642 1 2 0_0402_5% HDMI_L_SDATA 1 6 HDMI_SDATA

A 1 1 2 2 A
2N7002KDWH_SOT363-6
L30 WCM-2012-121T_0805
5V PULL UP IN CONNECTER SIDE For EMI
HDMI_D2- 1 2 HDMI_R_D2-
PR-7 R655 @ 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 35 of 61
5 4 3 2 1
 5 4 3 2 1

S3 S4/S5
+3VUSB 7~10mil
+3V_PCH V X For WAKE Function USB_PE_REXT R1030 1 USB30@2 12.1K_0402_1%
+3VS X X R1021 1 @ 2 4.7K_0402_5% USB30_SMI#
R1022 1 USB30@2 4.7K_0402_5% USB_PEPWRDET USB_UREXT R1032 1 USB30@2 12.1K_0402_1%
+1.2VUSB V X
USB_PEPWRDET
R1023 1 USB30@2 10K_0402_5% USB_OCI#A
+1.2VS X X R1024 1 USB30@2 10K_0402_5% USB_OCI#B R1034 R1022
S1 Mount @
* S3 @ Mount @
USB30_XT1 2 1
Power Sequence R1033
R1034
1 @
@
2 4.7K_0402_5%
4.7K_0402_5%
USB_PESEL
USB_PEPWRDET
C1004 +3VS
22P_0402_50V8J
1 2 USB_PESEL 1

3
4
D R1036 1 USB30@2 4.7K_0402_5% USB_TEST_EN C1005 D
R1037 1 USB30@2 4.7K_0402_5% USB_GPIO0 12P_0402_50V8J Y9
ASM1042 R1028 @ 4.7K_0402_5% USB_GPIO1 USB30@ 20MHZ_12PF_X3G020000FC1H-X
1 2 R1033

1
R1031 @ 4.7K_0402_5% USB_GPIO2 2 USB30@ C1045 C1046
1 2

1
2

0.1U_0603_16V7K

0.1U_0603_16V7K
+5VALW/+3VALW R1029 2 @ 1 0_0402_5% CLKREQ_USB30# * Other applaction @ @ @ @
USB30_XT2 2 1

2
+3V_PCH/+1.2VUSB Express Card/Mini Card Mount C1006
22P_0402_50V8J
+3VS/+1.2VS
T1 PORST#
T2 PE_RST#
+3VS

T1: 2~80ms EMC Caps C1045, C1046 should

+1.2VS
T2: >200ms +1.2VS be placed at board(-8430.00
U90 USB30@ -3530.00)

USB_GPIO1 1 64 USB_GPIO0
USB30_SMI# GPIO1 GPIO0 +VDD33U
16 USB30_SMI# 2 SMI# GND3 63
USB_GPIO2 3 62 Close to ASM1042
1U_0402_6.3V6K @ C1008 USB_PESEL GPIO2 VCC12_3 USB_PE_REXT
4 61

13 CLKREQ_USB30#
1 2
1 2
USB_PEPWRDET
CLKREQ_USB30#_R
5
6
PE_SEL
PE_PWRDET
PE_CLKREQ#
PE_REXT
VCC33P
PE_TXN
60
59
+VDD33U
PCIE_PRX_USB3TX_N4_C USB30@ C1009 2 1 0.1U_0402_16V7K PCIE_PRX_USB3TX_N4 13
PR-11 Q910
@ 7 58 PCIE_PRX_USB3TX_P4_C USB30@ C1010 2 1 0.1U_0402_16V7K
VCC33_1 PE_TXP PCIE_PRX_USB3TX_P4 13 +3VALW +3VUSB
R1039 0_0402_5% USB_SPISCK 8 57 AO3413L_SOT23-3
USB_SPISI SPI_CLK GNDA3
9 SPI_DO PE_RXN 56 PCIE_PTX_USB3RX_N4 13
51.1K_0402_1% R1040 USB_SPICS# 10 55 3 1

D
SPI_CS# PE_RXP PCIE_PTX_USB3RX_P4 13
USB_SPISO

0.1U_0402_16V7K
+3VS 1 2 11 SPI_DI VDD12P 54 +VDD12U

1
USB30@ R1090
100K_0402_5%

USB30@ C1061
USB30@ 12 53 USB30_XT1 1

G
GND1 XI

2
USB_PORST# 13 52 USB30_XT2 1 USB30@

2
C
T90 PAD @ PORST# XO C1062 C
14 UART_RX PE_CLKN 51 CLK_PCIE_USB30# 13
2 1 C1011 T91 PAD @ 15 50 1U_0402_6.3V6K USB30@ R1092
USB30@ 2.2U_0603_16V6K 16
UART_TX
ASM1042 PE_CLKP
49
CLK_PCIE_USB30 13 2 220_0603_5%

2
U2DN_B VCC12_1 VCC12_4 2
37 U2DN_B 17 48 +VDD12U

1
U2DP_B U2DN_B VDD12U_2 U3RXDN_A
37 U2DP_B 18 U2DP_B (TQFN 64) U3RXN_A 47
U3RXDP_A
U3RXDN_A 37
+3VUSB 19 VSUS33_1 U3RXP_A 46 U3RXDP_A 37

1
+1.2VUSB 20 VSUS12_1 GNDA2 45
U2DN_A 21 44 U3TXDN_A_C R1091
37 U2DN_A U2DN_A U3TXN_A U3TXDN_A_C 37

3
U2DP_A 22 43 U3TXDP_A_C 1K_0402_5%
37 U2DP_A PR-7 U2DP_A U3TXP_A U3TXDP_A_C 37
23 42 USB_UREXT USB30@ USB30@
VSUS33_2 UREXT
14,32,41 PCIE_WAKE# 1 2 24 41 +VDD33U

2
R1043 0_0402_5% PE_WAKE# VCC33U U3TXDN_B_C 2N7002KDWH_SOT363-6
25 PPON_A U3TXN_B 40 U3TXDN_B_C 37 5
R1044 4.7K_0402_5% 26 39 U3TXDP_B_C Q83B
PPON_B U3TXP_B U3TXDP_B_C 37

6
+3VS 2 @ 1 USB_OCI#A 27 38
37 USB_OCI#A

4
USB_OCI#B OCI_A# GNDA1 U3RXDN_B
37 USB_OCI#B 28 OCI_B# U3RXN_B 37 U3RXDN_B 37
1 2 PLT_RST#_USB30 29 36 U3RXDP_B
5,15,32,40,41 PLT_RST# PE_RST# U3RXP_B U3RXDP_B 37
0_0402_5% R1045 USB_TEST_EN 30 35 +VDD12U +VDD12U USB3_ON 2
PR-7 TEST_EN VDD12U_1 USB30@
1 31 VCC33_2 VSUS12_2 34 +1.2VUSB
C1012 32 33 Q83A

1
@ VCC12_2 GND2 2N7002KDWH_SOT363-6
0.1U_0402_16V7K
2
65

+
1
.
2
V
U
S
B
T
O
+
1
.
2
V
S
GND4

ASM1042_TQFN64_9X9
Q904
+1.2VUSB AO3404AL_SOT23 +1.2VS
+3VS

S
1 3
1

10U_0603_6.3V6M

C1037
USB30@ R1047 R1048 @ USB30@

G
2
B 4.7K_0402_5% 4.7K_0402_5% B
2 USB30@
2

U92
USB_SPICS# 1 8 USB30@
CS# VCC USB_SPISCK 1.2VS_GATE
3 WP# SCLK 6 +VSBP 1 2
7 5 USB_SPISI R1049 330K_0402_5%
HOLD# SI USB_SPISO
4 GND SO 2

1.5M_0402_5%
2

1
MX25L5121EMC-20G SOP 8P Q905 D C1036
USB30@ C1016 SUSP 2 R747 0.1U_0603_25V7K
35,41,42 SUSP
0.1U_0402_16V7K G USB30@ USB30@

2
1 USB30@ 2N7002KW 1N SOT323-3 S

1
USB30@

+1.2VUSB +1.2VS

L904
+VDD12U
PR-11
1 1 1 1 1 1 1 1
+1.2VS 1
USB30@
2 +1.5Vto +1.2VUSB Transfer
10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C1025 C1026 C1027 C1020 C1028 C1029 C1030 C1031 FBMA-L11-201209-221LMA30T_0805 1 1 1

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C1021 C1022 C1023

USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ USB30@ +5VALW +1.5V
2 2 2 2 2 2 2 2 +5VALW +1.5V +1.2VUSB

1U_0603_10V6K

10U_0603_6.3V6M
USB30@ USB30@ USB30@
2 2 2

C1018

C1019
1 1 1A U91 1A
5 VIN VOUT 3
9 VIN VOUT 4
USB30@ USB30@ 6
Pin 20 Pin 34 Pin 16 Pin 32 Pin 49 Pin 62 2 2 VCNTL R1051 1
2 1 7 POK FB 2 2
Pin 35 Pin 48 Pin 54 R1050 USB30@

10U_0603_6.3V6M
5.1K_0402_1% 8 1 11K_0402_1%
EN GND

C1032
USB30@ 1

2
+3VS USB3_ON R1053 1 2 APL5930KAI-TRG_SO8
+3VUSB 40 USB3_ON
USB30@ 1K_0402_5% USB30@ R1052

1
A +3VS +VDD33U A
USB30@ 20K_0402_1% USB30@

1
L905 R1094 C1060 2
USB30@
1 1 1 1 2 USB30@ 0.01U_0402_25V7K

1
10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

1 1 1 C1014 C1041 C1042 FBMA-L11-201209-221LMA30T_0805 100K_0402_5% USB30@

2
10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

C1038 C1039 C1040 1 1

2
0.1U_0402_16V7K

0.1U_0402_16V7K

USB30@ USB30@ USB30@ C1034 C1035

USB30@ USB30@ USB30@ 2 2 2
2 2 2 USB30@ USB30@
2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/01/11 Deciphered Date 2012/01/11 Title
Pin 19 Pin 23 Pin 7 Pin 31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Pin 60 Pin 41 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 36 of 61
5 4 3 2 1
 1 2 3 4 5

@ 1 2
R511 0_0402_5%

+5VALW
For port 0 USB3_RX1_N_L 3 4 USB3_RX1_N_R AI CHARGER PR-7
AI@ U28
@ U27 +USB_VCCA USB3_RX1_P_L 2 1 USB3_RX1_P_R R512 1 2 0_0402_5% 8 1 CEN T44 PAD @
40 USBAI_EN CB CEN
C509 1 2 2.2U_0402_6.3V6M USB20_N0_R 7 2 USB20_N0_CON
TDM DM

1
1 8 L25 DLP11TB800UL2L_4P USB20_P0_R 6 3 USB20_P0_CON
GND OUT TDP DP SELCDP
2 IN OUT 7 +5VALW 5 VDD SELCDP 4
C510 2 1 0.22U_0603_16V7K 3 6 IU3@ @ 1 2 R516 2 9
USBAI_PEN#_R 4 IN OUT USB_OC0# R514 0_0402_5% 100K_0402_5% C511 Thermal Pad
EN# OC# 5 1 2 USB_OC0# 15
0_0402_5% R515 @ 1 2 AI@ 0.1U_0402_16V7K SLG55584AVTR_TDFN8_2X2

2
R517 0_0402_5% AI@
A AP2301MPG-13 MSOP 8P 1 USB30@2 1 +5VALW A
USB_OCI#A 36
1 0_0402_5% R1056
Low Active C512 USB3_TX1_N_L 2 1 USB3_TX1_N_C 3 4 USB3_TX1_N_R
@ 1000P_0402_50V7K C648 0.1U_0402_16V7K

1
2 USB3_TX1_P_L 2 1 USB3_TX1_P_C 2 1 USB3_TX1_P_R R581
C649 0.1U_0402_16V7K 4.7K_0402_5%
L24 DLP11TB800UL2L_4P AI@

2
@ 1 2 USB20_N0_R R746 1 NAI@ 2 0_0402_5% USB20_N0_CON SELCDP
R518 0_0402_5%
40 USBAI_PEN# USBAI_PEN# 1 2 USBAI_PEN#_R USB20_P0_R R745 1 NAI@ 2 0_0402_5% USB20_P0_CON

1
R809 AI@ 0_0402_5%
放在U28背面 R580
40 USBSW_EN# USBSW_EN# 1 2 @ 4.7K_0402_5%
R810 NAI@ 0_0402_5%
CB SELCDP Function

2
@ 1 2
R519 0_0402_5% 0 X DCP autodetect charger mode
1 0 S0 charging with SDP only
USB3_RX2_N_L 3 4 USB3_RX2_N_R
+5VALW 1 1 S0 charging with SDP or CDP
For port 1
USB3_RX2_P_L 2 1 USB3_RX2_P_R

@ U29 +USB_VCCB L23 DLP11TB800UL2L_4P

1 2
C515 2.2U_0402_6.3V6M 1 8 @ 1 2
GND OUT R520 0_0402_5%
2 7
C516 2 1 0.22U_0603_16V7K
40 USBSW_EN# USBSW_EN#
3
4
IN
IN
EN#
OUT
OUT
OC#
6
5 1
IU3@
2 USB_OC0#
@ 1
R522
2
0_0402_5%
charger port: left side & near user
0_0402_5% R523

AP2301MPG-13 MSOP 8P 1 USB30@2 USB3_TX2_N_L 2 1 USB3_TX2_N_C 3 4 USB3_TX2_N_R

B USB_OCI#B 36 +USB_VCCA B
1 0_0402_5% R1057 C650 0.1U_0402_16V7K
Low Active C517 W=80mils JUSB1
@ 1000P_0402_50V7K USB3_TX2_P_L 2 1 USB3_TX2_P_C 2 1 USB3_TX2_P_R 2 R521 1 0_0402_5% 1
C651 0.1U_0402_16V7K @ USB20_N0_C VBUS
2 D-
2 L22 DLP11TB800UL2L_4P USB20_P0_C 3
1 1 D+
WCM-2012HS-900T 4
@ 1 USB20_P0_CON USB20_P0_C C513 C514 USB3_RX1_N_R GND
2 4 4 3 3 5 STDA_SSRX-
R524 0_0402_5% 470P_0402_50V7K 47U_0805_6.3V USB3_RX1_P_R 6
2 2 STDA_SSRX+
7 GND
USB20_N0_CON 1 2 USB20_N0_C USB3_TX1_N_R 8
1 2 USB3_TX1_P_R STDA_SSTX-
9 STDA_SSTX+
L27
10 GND
2 R525 1 0_0402_5% 11 GND
R1058 1 IU3@ 2 0_0402_5% USB3_RX1_P_L @ 12
15 USB3_RX1_P D27 GND
R1059 1 IU3@ 2 0_0402_5% USB3_RX1_N_L 13
+5VALW 15 USB3_RX1_N GND
USB3_RX1_N_R 1 1 109 USB3_RX1_N_R
R1060 1 USB30@2 0_0402_5% SANTA_373280-1
36 U3RXDP_A
For port 5 R1061 1 USB30@2 0_0402_5% USB3_RX1_P_R 2 2 98 USB3_RX1_P_R CONN@
+USB_VCCC 36 U3RXDN_A
@ U30 USB3_TX1_N_R 4 4 77 USB3_TX1_N_R 2 R526 1 0_0402_5%
1 2 15 USB3_TX1_P R1062 1 IU3@ 2 0_0402_5% USB3_TX1_P_L @
C518 2.2U_0402_6.3V6M 1 8 15 USB3_TX1_N R1063 1 IU3@ 2 0_0402_5% USB3_TX1_N_L USB3_TX1_P_R 5 5 66 USB3_TX1_P_R
GND OUT PR-7
2 IN OUT 7
C519 2 1 0.22U_0603_16V7K 3 6 R1064 1 USB30@2 0_0402_5% 3 3 WCM-2012HS-900T
IN OUT 36 U3TXDP_A_C
USBSW_EN# 4 5 1 2 R1065 1 USB30@2 0_0402_5% USB20_N1_R 4 3 USB20_N1_C
EN# OC# USB_OC2# 15 36 U3TXDN_A_C 8 4 3
R527 0_0402_5%

AP2301MPG-13 MSOP 8P YSCLAMP0524P_SLP2510P8-10-9 USB20_P1_R 1 2 USB20_P1_C

1 2 +USB_VCCB
1
C522 L26 JUSB2
Low Active @ 1000P_0402_50V7K
W=80mils
1 VBUS
2 R528 1 0_0402_5% USB20_N1_C 2
2 R1066 1 IU3@ USB3_RX2_P_L USB20_P1_C D-
15 USB3_RX2_P 2 0_0402_5% @ 1 1 3 D+
C R1067 1 IU3@ 2 0_0402_5% USB3_RX2_N_L 4 C
15 USB3_RX2_N GND
C520 C521 USB3_RX2_N_R 5
R1068 1 USB30@2 0_0402_5% 470P_0402_50V7K 47U_0805_6.3V USB3_RX2_P_R STDA_SSRX-
36 U3RXDP_B 6 STDA_SSRX+
R1070 1 USB30@2 0_0402_5% 2 2 7
36 U3RXDN_B GND
USB3_TX2_N_R 8
USB3_TX2_P_R STDA_SSTX-
9 STDA_SSTX+
R1073 1 IU3@ 2 0_0402_5% USB3_TX2_P_L D29
15 USB3_TX2_P
15 USB3_TX2_N R1075 1 IU3@ 2 0_0402_5% USB3_TX2_N_L USB3_RX2_N_R 1 1 109 USB3_RX2_N_R 10 GND
11 GND
36 U3TXDP_B_C R1076 1 USB30@2 0_0402_5% USB3_RX2_P_R 2 2 98 USB3_RX2_P_R 12
R1078 1 USB30@2 0_0402_5% D28 GND
36 U3TXDN_B_C 13 GND
USB3_TX2_N_R 4 4 77 USB3_TX2_N_R 6 3 USB20_N1_C
I/O4 I/O2 SANTA_373280-1
+5VALW USB3_TX2_P_R 5 5 66 USB3_TX2_P_R CONN@

For port 2 3 3 +5VALW 5 VDD GND 2

+USB_VCCD
@ U31 8
1 2
C523 2.2U_0402_6.3V6M 1 8 YSCLAMP0524P_SLP2510P8-10-9 4 1 USB20_P1_C
GND OUT PR-7 I/O3 I/O1
2 IN OUT 7
C524 2 1 0.22U_0603_16V7K 3 6 AZC099-04S.R7G_SOT23-6
USBSW_EN# IN OUT
4 EN# OC# 5 1 2 USB_OC1# 15
R529 0_0402_5% 15 USB20_N0 R1069 1 IU3@ 2 0_0402_5% USB20_N0_R
15 USB20_P0 R1071 1 IU3@ 2 0_0402_5% USB20_P0_R
AP2301MPG-13 MSOP 8P D39
1 36 U2DN_A R1072 1 USB30@2 0_0402_5% 6 3 USB20_P0_C
C525 R1074 1 USB30@2 0_0402_5% I/O4 I/O2
Low Active @ 1000P_0402_50V7K
36 U2DP_A

2 R1077 1 IU3@ 2 0_0402_5% USB20_N1_R 5 2

15 USB20_N1 +5VALW VDD GND
15 USB20_P1 R1079 1 IU3@ 2 0_0402_5% USB20_P1_R

36 U2DN_B R1080 1 USB30@2 0_0402_5%

36 U2DP_B R1081 1 USB30@2 0_0402_5% 4 1 USB20_N0_C
D I/O3 I/O1 D

AZC099-04S.R7G_SOT23-6

Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/09/22 Deciphered Date 2012/12/31 Title
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 37 of 61
1 2 3 4 5
 A B C D E

Power Button +3VALW +3VL

Screw Hole

2
PR-7
930@ R530 R531
ON/OFF switch R513 1 2 9012@ 0_0402_5% 9012@
100K_0402_5% 100K_0402_5%
1 H1 H2 H3 H5 H6 H8 1

1
SW1 D30 3P0
NTC010-BB1G-C100C 2 ON/OFF 40
2 1 ON/OFFBTN# 1 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
3 51_ON#
51_ON# 43
4 3 @ @ @ @ @ @
930@
DAN202UT106_SC70-3 H9 H10 H11 H12 H13 H14 H15 H24 H25
5

PR-1
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
LED7 @
R722 @ @ @ @ @ @ @ @

40 PWR_ON_LED1# PWR_ON_LED1# 1 2 2 1 +5VALW

19-213A-T1D-CP2Q2HY-3T_WHITE 300_0402_5% H18 H19 H20 H21

4P3

1
D H_4P3 H_4P3 H_4P3 H_4P3

1
EC_ON 2 Q30
40,45 EC_ON
G 2N7002KW 1N SOT323-3 @
@ @ @
2

S 930@

3
R532

10K_0402_5%
930@ H23
1

2 3P3 2
H_3P3

1
PWR_ON_LED1#
@

ON/OFFBTN#

H16 H17 H22

3P1
H_3P1 H_3P1 H_3P1

1
2

3
@
@ @
PJSOT24CH_SOT23-3
D31

1
@

FD1 FD2 FD3 FD4

3
Fan Control Circuit @ @ @ @ 3

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

+5VS

+3VS
1
1
C526
2

2.2U_0402_6.3V6M C527
R533 U32 2
1000P_0402_50V7K~D
10K_0402_5% 2
8 GND EN 1
JFAN1
7 GND VIN 2
6 3 +5VS_FAN 1
1

GND VOUT FAN_SPEED 1

5 GND VSET 4 1 2 2
FAN_SPEED 3
40 FAN_SPEED 3
APL5607KI-TRG_SO8 C528
1 10U_0603_6.3V6M 4 GND
C529 2
5 GND
1000P_0402_50V7K
ACES_85204-0300N
2 40 FAN_SET
CONN@

place as close as EC

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 38 of 61
A B C D E
KSO10 @ 1 2
C553 100P_0402_50V8J
KSO11 @ 1 2
C554 100P_0402_50V8J
KSO12 @ 1 2
C555 100P_0402_50V8J
KSO15 @ 1 2
C556 100P_0402_50V8J PR-4
KSI7 @ 1
C557
2
10P_0402_50V8J
INT_KBD Conn. Touch/B Connector
KSI2 @ 1 2
C558 100P_0402_50V8J TP_CLK PCH_SMBDATA
KSI3 @ 1 2
C559 100P_0402_50V8J TP_DATA PCH_SMBCLK
KSI4 @ 1 2 +3VS
KSI[0..7] C564
C560 10P_0402_50V8J
KSI[0..7] 12,40

2
KSI0 @ 1 2 1 2
C561 100P_0402_50V8J KSO[0..17] D33 D34
KSO[0..17] 40
KSI5 @ 1 2
C562 10P_0402_50V8J 0.1U_0402_16V4Z
KSI6 @ 1 2
C563 10P_0402_50V8J JTP1

1
KSI1 @ 1 2 1
C565 100P_0402_50V8J JKB1 1 L30ESDL5V0C3-2 C/A SOT-23 L30ESDL5V0C3-2 C/A SOT-23
2 2
KSO2 @ 1 2 26 3
GND2 3 TP_CLK 40
C566 100P_0402_50V8J 25 4
GND1 4 TP_DATA 40
KSO1 @ 1 2 5 1 1
C567 100P_0402_50V8J KSO15 5 PCH_SMBDATA @ @
24 24 9 G1 6 6

100P_0402_50V8J
C570

100P_0402_50V8J
C571
KSO0 @ 1 2 KSO14 23 10 7 PCH_SMBCLK +3VS
C568 100P_0402_50V8J KSO12 23 G2 7 GP_INT
22 22 8 8
KSO4 @ KSO10 2 2
1 2 21 21
C569 100P_0402_50V8J KSO11 20 ACES_51522-00801-001
20

2
KSO3 @ 1 2 KSO6 19 CONN@
C572 100P_0402_50V8J KSO8 19 R808
18 18
KSO5 @ 1 2 KSO4 17 2.2K_0402_5%
17

2
G
C573 100P_0402_50V8J KSO2 16 Q64
KSO14 @ KSO5 16
1 2 15

1
C574 100P_0402_50V8J KSO13 15 GP_INT SMBALERT#
14 14 3 1 SMBALERT# 13
KSO6 @ KSI0

D
1 2 13 13
C575 100P_0402_50V8J KSI3 12
KSO7 @ KSO1 12 BSS138_SOT23
1 2 11 11
C576 100P_0402_50V8J KSI2 10
KSO13 @ KSI4 10
1 2 9 9
C577 100P_0402_50V8J KSO3 8
KSO8 @ KSI5 8 PCH_SMBDATA
1 2 7 7 PCH_SMBDATA 10,11,13,41
C578 100P_0402_50V8J KSI6 6 PCH_SMBCLK
6 PCH_SMBCLK 10,11,13,41
KSO9 @ 1 2 KSO9 5
C579 100P_0402_50V8J KSI7 5
4 4
KSI1 3
KSO0 3
2 2
KSO7 1 1
ACES_88514-02401-071
CONN@

+5VALW 1 2
R713 10K_0402_5%

LED1

LED 40 PWR_ON_LED#
Green
2
YG G 3
1 2 1 +3VALW
200_0402_5% R714
D35
@
PCH_SATALED# 2
HT-121UYG_YELLOW-GREEN
LED2 PWR_ON_LED# 3
1 Lid Switch
Green BATT_CHG_LED# (Hall Effect Switch)
40 BATT_CHG_LED# 2 1 2 UYG
YSDA0502C 3P C/A SOT-23
100_0402_5% R716
1 +3VALW +3VALW
D36
@
Amber BATT_LOW_LED# 2 1 3 BATT_CHG_LOW_LED# 2
40 BATT_CHG_LOW_LED#
UD

300_0402_5% R715 1
BATT_CHG_LED# 3
HT-210UD-UYG_AMB-GREEN

1
LED3 YSDA0502C 3P C/A SOT-23 2
C582 R578
D37

2
Green YG G 3 @ 0.1U_0402_16V4Z U36 47K_0402_5%
2 1 2 1 WL_BT_LED# 2

VDD
40 WL_BT_LED# +3VS 1
200_0402_5% R717 1

2
CAPS_LED# 3
HT-121UYG_YELLOW-GREEN VOUT 3 LID_SW_IN# 40
YSDA0502C 3P C/A SOT-23
1

GND
LED4
C583
D38
Green YG G 3 @ 10P_0402_50V8J
12 PCH_SATALED# 2 1 2 1 +3VS NUM_LED# 2 AH1806-W-7 SC59 3P @

1
200_0402_5% R719 2
1
3
HT-121UYG_YELLOW-GREEN
YSDA0502C 3P C/A SOT-23
LED5

Green YG G 3
40 NUM_LED# 2 1 2 1 +3VS
200_0402_5% R720

HT-121UYG_YELLOW-GREEN ESD
LED6

Green YG G 3
40 CAPS_LED# 2 1 2 1 +3VS
200_0402_5% R721

HT-121UYG_YELLOW-GREEN Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 39 of 61
 5 4 3 2 1

+3VALW PR-7 L28 KSI[0..7]

KSI[0..7] 12,39
Board ID
FBMA-L11-160808-800LMT_0603 +3VALW +3VALW
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW_EC 1 2 +EC_VCCA KSO[0..17]
KSO[0..17] 39
R534 1 1 1 1 2 2 1

2
0_0805_5% C530 C531 C532 C533 C534 C535 0.1U_0402_16V4Z USBSW_EN# 1 2
R535 C536 10K_0402_5% R744 R536
1000P_0402_50V7K 0_0402_5% USBAI_PEN# 1 2 Ra 100K_0402_5%
2 2 2 2 1 1 930@ 2 ECAGND IRT-2 10K_0402_5% AI@ R743
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K

1
AD_BID0
@ 1 2 KB_RST# R537 2 1 +3VL +3VS

2
D C156 100P_0402_50V8J 9012@ 0_0402_5% 1 D
C537

111
125
@ PM_SLP_S4# PR-7 TP_CLK 33K_0603_5%
Rb

22
33
96

67
1 2 U33 2 1

9
C157 100P_0402_50V8J 4.7K_0402_5% R541 R538 0.1U_0402_16V4Z
TP_DATA 2
2 1

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

1
4.7K_0402_5% R542
close U33
8/23 Rb change to 33K
GATEA20 1 21 USBSW_EN# USBSW_EN# 37
16 GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F VGA_PWROK
16 KB_RST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 VGA_PWROK 29,53
SERIRQ 3 26 DGPU_PWROK
12 SERIRQ SERIRQ# FANPWM1/GPIO12 DGPU_PWROK 16
LPC_FRAME# 4 27 DS_WAKE#
12,41 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 DS_WAKE# 16
C539 LPC_AD3 5 2 1 ECAGND
12,41 LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C538 100P_0402_50V8J Co-lay KB930/KB9012 PECI
12,41 LPC_AD2 LAD2
2 1 R539 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMPA 1 @ 2 +3VL
12,41 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 43 +3VALW_EC
LPC_AD0 Stuff
12,41 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I R547 100K_0402_5%
ADP_I/AD2/GPIO3A 65 ADP_I 43,44
12 AD Input 66 AD_BID0 930@ KB930 R599
15 CLK_PCI_LPC PCICLK AD3/GPIO3B
5,15,32,36,41 PLT_RST# 13 PCIRST#/GPIO05 AD4/GPIO42 75 1 2
+3VALW R540 2 1 47K_0402_5% EC_RST# 37 76 DRAMRST_CNTRL_PCH 6,9,13 R549 200K_0402_5% KB9012 R571
EC_SCI# ECRST# SELIO2#/AD5/GPIO43 D32
16 EC_SCI# 20 SCI#/GPIO0E
C540 2 1 0.1U_0402_16V4Z 14 PM_CLKRUNEC# 38 ACIN_D 2 1
CLKRUN#/GPIO1D ACIN 14,44
68 USBAI_PEN# @
DAC_BRIG/DA0/GPIO3C USBAI_PEN# 37 C541
70 FAN_SET RB751V-40_SOD323-2
EN_DFAN1/DA1/GPIO3D FAN_SET 38
DA Output 71 PCH_DPWROK SA_PGOOD 1 2 0.1U_0402_16V4Z
IREF/DA2/GPIO3E PCH_DPWROK 14
KSI0 55 72 R752 1 2 0_0402_5%
+3VALW KSI0/GPIO30 DA3/GPIO3F EC_DRAMRST_CNTRL_PCH 6
KSI1 56
KSI2 KSI1/GPIO31 PR-7
57 KSI2/GPIO32
1 2 EC_SMB_CK1_R KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE_R R544 2 1 0_0402_5% EC_MUTE# EC_MUTE# 33
C R543 2.2K_0402_5% KSI4 59 84 USBAI_EN EC_MUTE# 1 2 C
KSI4/GPIO34 PSDAT1/GPIO4B USBAI_EN 37 PR-7
1 2 EC_SMB_DA1_R KSI5 60 KSI5/GPIO35 PSCLK2/GPIO4C 85 BT_ON 41
R546 2.2K_0402_5% KSI6 61 PS2 Interface 86 EAPD R545 10K_0402_5%
KSI6/GPIO36 PSDAT2/GPIO4D EAPD 33
1 2 FLASH_EN KSI7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK
TP_CLK 39
R548 @ 10K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 39
KSO1 40 C542 100P_0402_50V8J
KSO2 KSO1/GPIO21 ACIN
41 KSO2/GPIO22 2 1
KSO3 42 97 CPU1.5V_S3_GATE
KSO3/GPIO23 SDICS#/GPXOA00 CPU1.5V_S3_GATE 9
KSO4 43 98 EN_WOL
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL 32
KSO5 HDA_SDO
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
R550 2
HDA_SDO 12
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 1 NTC_V 43
KSO7 46 SPI Device Interface 9012@ 0_0402_5% PR-7
KSO8 KSO7/GPIO27 PR-1
47 KSO8/GPIO28
KSO9 48 119 PWR_ON_LED1# 38
KSO10 KSO9/GPIO29 SPIDI/RD#
49 KSO10/GPIO2A SPIDO/WR# 120 USB3_ON 36
KSO11 50 SPI Flash ROM 126 PR-11
+3VS KSO12 KSO11/GPIO2B SPICLK/GPIO58 @ EC_SPI_WP
51 KSO12/GPIO2C SPICS# 128 1 2
KSO13 52 C543 100P_0402_50V8J
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E EC_SPI_WP 12
KSO15 54 73 PR-7 Delete R558 PCH_ENBKL
KSO15/GPIO2F CIR_RX/GPIO40 PCH_ENBKL 14
1 2 EC_SCI# 81 74 EC_SPI_WP 1 2
KSO16/GPIO48 CIR_RLC_TX/GPIO41 H_PECI 5
R551 10K_0402_5% 82 89 @ T37 PAD R559 930@ 43_0402_1% Reserve for EMI please close to U4
VGA_BUF# PR-7 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED#
1 2 BATT_CHGI_LED#/GPIO52 90 BATT_CHG_LED# 39
R730 @ 10K_0402_5% 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 39
EC_SMB_CK1 1 R560 2 0_0402_5% EC_SMB_CK1_R 77 GPIO 92 SUSACK#
43,44 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 SUSACK# 14
EC_SMB_DA1 1 R561 2 0_0402_5% EC_SMB_DA1_R 78 93 BATT_CHG_LOW_LED#
43,44 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 BATT_CHG_LOW_LED# 39
13,20 PCH_SMLCLK 1 R562 2 0_0402_5% EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON 42,47
13,20 PCH_SMLDATA 1 R563 2 0_0402_5% EC_SMB_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON
VR_ON 50
127 PM_SLP_S4# PCH_PWROK 1 @ 2 10K_0402_5%
B PR-7 AC_IN/GPIO59 PM_SLP_S4# 14 B
R554

14 PM_SLP_S3# 1 R564 2 0_0402_5% PM_SLP_S3#_R 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 PCH_RSMRST#

PCH_RSMRST# 12,14
14 PM_SLP_S5# 1 R565 2 0_0402_5% PM_SLP_S5#_R 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT#
EC_LID_OUT# 16
EC_SMI# 15 102 2 R566 1 PR-7
16 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 Turbo_V 43
PCH_PWR_EN 16 103 9012@ 0_0402_5%
42 PCH_PWR_EN LID_SW#/GPIO0A EC_SWI#/GPXO06 PROCHOT 43
FLASH_EN 17 104 R568 2 1 9012@ 0_0402_5%
12 FLASH_EN SUSP#/GPIO0B ICH_PWROK/GPXO06 MAINPWON 43,45 PR-7
AC_PRESENT 18 GPO 105 BKOFF#
14 AC_PRESENT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 30
VGA_BUF# 19 GPIO 106 PBTN_OUT#
20 VGA_BUF# EC_PME#/GPIO0D WL_OFF#/GPXO09 PBTN_OUT# 12,14
EC_INV_PWM 25 107 R569 1 930@ 2 PCH_PWROK
30 EC_INV_PWM EC_THERM#/GPIO11 GPXO10 WL_BT_LED# 39
FAN_SPEED 28 108 SA_PGOOD 0_0402_5%
38 FAN_SPEED FAN_SPEED1/FANFB1/GPIO14 GPXO11 SA_PGOOD 49
SUSWARN# 29
14 SUSWARN# E51TXD_P80DATA FANFB2/GPIO15
41 E51TXD_P80DATA 30 EC_TX/GPIO16
PR-7 R570 E51RXD_P80CLK 31 110 ACIN_D PR-14
41 E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1
VR_HOT# 1 2 32 112 EC_ON @ 1 2 H_PECI_R
50 VR_HOT# 14 PCH_PWROK ON_OFF/GPIO18 ENBKL/GPXID2 EC_ON 38,45
PWR_ON_LED# 34 114 ON/OFF C1070 100P_0402_50V8J
39 PWR_ON_LED# PWR_LED#/GPIO19 GPXID3 ON/OFF 38
9012@ 0_0402_5% NUM_LED# 36 GPI 115 LID_SW_IN#
+3VS 39 NUM_LED# NUMLED#/GPIO1A GPXID4 LID_SW_IN# 39
0.1U_0402_16V4Z~D

116 SUSP#
GPXID5 SUSP# 42,46,47,48
GPXID6 117 WL_OFF# 41
1

1 @ 118 H_PECI_R R571 1 2 H_PECI Reserve for EMI please close to U33
GPXID7
C548

R572 EC_CRY1 122 9012@ 43_0402_1%

XCLK1 +V18R
0_0402_5% 14 SUSCLK_R 123 XCLK0 V18R 124
PR-7 1
2
AGND

2 R573 1 100K_0402_5% C550

GND
GND
GND
GND
GND
2

1 2 4.7U_0805_10V4Z
U34 C551 20P_0402_50V8 KB9012QF A3 LQFP 128P 2
P

11
24
35
94
113

69

5,43 H_PROCHOT# H_PROCHOT# 4 2 PROCHOT 20mil

Y A L29
NC

A A
G

ECAGND 2 1
SN74LVC1G06DCKR_SC70-5
1 R575 FBMA-L11-160808-800LMT_0603
1

100K_0402_5%
C552
47P_0402_50V8J
1

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Close to IMVP7 Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 40 of 61
5 4 3 2 1
 A B C D E

+1.5VS +3VS

WLAN/BT combo R583 2 @ 1 0_1206_5%

1
R584
PR-7 +3VALW U37 +3VS_WLAN
0_0805_5%
SI4178DY-T1-GE3_SO8
+3VS_WLAN +3VS_WLAN
80mil

10U_0603_6.3V6M
8 1
+1.5VS_WLAN 7 2

22U_0805_6.3V6
1 1 1 1 1 1 1 6 3 1

1
C584 C585 C586 C587 C588 C589 C590 5

C591
1 0.1U_0402_16V7K 1
4.7U_0805_10V4Z 0.1U_0402_16V7K 4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K R585

4
2 2 2 2 2 2 2 PR-15 2 100_0603_5%

2
3VS_WLAN_CHG
+VSBP 1 2 3VSWLAN_GATE
R724 390K_0402_5%
JMINI1

1
PCIE_WAKE# R586 1 @ 2 0_0402_5% 1 2 +3VS_WLAN C592
14,32,36 PCIE_WAKE# WAKE# 3.3V

6
3 RESERVED GND 4
PCH_BT_ON R587 1 @ 2 5 6 +1.5VS_WLAN 0.01U_0402_25V7K

2
RESERVED 1.5V

3
13 WLANCLK_REQ# 0_0402_5%~D 7 8 LPC_FRAME#_R Q82A
CLKREQ# RESERVED LPC_AD3_R SUSP
9 GND RESERVED 10 35,36,42 SUSP 2
11 12 LPC_AD2_R PR-0119
13 CLK_PCIE_WLAN# REFCLK- RESERVED
13 14 LPC_AD1_R 2N7002KDWH_SOT363-6 Q82B 5 SUSP
13 CLK_PCIE_WLAN

1
REFCLK+ RESERVED LPC_AD0_R
15 GND RESERVED 16
PCI_RST#_R 17 18 0_0402_5% 1 2 R588 2N7002KDWH_SOT363-6
PCH_WAN_RADIO_OFF# 15

4
CLK_LPC_DEBUG1_R RESERVED GND 0_0402_5% 1
19 RESERVED RESERVED 20 2@ R589 WL_OFF# WL_OFF# 40
21 22 PLT_RST#
GND PERST# PLT_RST# 5,15,32,36,40
13 PCIE_PRX_WLANTX_N2 23 24 R590 1 2 0_0603_5% +3VS_WLAN
PERn0 +3.3Vaux R591 1 @ PR-7
13 PCIE_PRX_WLANTX_P2 25 PERp0 GND 26 2 0_0603_5% +3VALW
27 28 0_0402_5%
GND +1.5V MINI1_SMBCLK R592 1 @
29 GND SMB_CLK 30 2 PCH_SMBCLK 10,11,13,39
31 32 MINI1_SMBDATA 1 @ 2 PCH_SMBDATA 10,11,13,39
13 PCIE_PTX_WLANRX_N2 PETn0 SMB_DATA
33 34 R593 0_0402_5%
13 PCIE_PTX_WLANRX_P2 PETp0 GND
35 GND USB_D- 36 USB20_N10 15
37 RESERVED USB_D+ 38 USB20_P10 15
+3VS_WLAN 39 RESERVED GND 40
2 41 42 2
RESERVED LED_WWAN#
43 RESERVED LED_WLAN# 44
45 RESERVED LED_WPAN# 46
47 RESERVED +1.5V 48
E51TXD_P80DATA R594 1 2 0_0402_5%~D 49 50
40 E51TXD_P80DATA RESERVED GND
E51RXD_P80CLK R595 1 2 0_0402_5%~D 51 52
40 E51RXD_P80CLK RESERVED +3.3V
2 R596 1
PR-5
100K_0402_5%

PCH_BT_ON R597 1 2 1K_0402_0.5% 53 54

16 PCH_BT_ON GND GND
BT_ON R598 1 2 1K_0402_0.5%
40 BT_ON
@ ACES_88915-5204
CONN@

5.2 mm High

Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
LPC_FRAME#_R R599 1 2 0_0402_5% LPC_FRAME#
LPC_FRAME# 12,40
LPC_AD3_R R600 1 2 0_0402_5% LPC_AD3
LPC_AD3 12,40
LPC_AD2_R R601 1 2 0_0402_5% LPC_AD2
3 LPC_AD2 12,40 3
LPC_AD1_R R602 1 2 0_0402_5% LPC_AD1
LPC_AD1 12,40
LPC_AD0_R R603 1 2 0_0402_5% LPC_AD0
LPC_AD0 12,40
PCI_RST#_R R604 1 2 0_0402_5% PLT_RST#
CLK_LPC_DEBUG1_R 1 2 CLK_LPC_DEBUG1 CLK_LPC_DEBUG1 15
R605 0_0402_5%

PR-7

C593
R606
2 1 1 2CLK_LPC_DEBUG1_R
@ 33_0402_5% @
22P_0402_50V8J
Reserve for EMI please close to JMINI1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/1212 Deciphered Date 2012/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 41 of 61
A B C D E
 A B C D E

+
5
V
A
L
W
T
O
+
5
V
S

+
1
.
5
V
T
O
+
1
.
5
V
S
+5VALW

+5VALW U38 +5VS

SI4178DY-T1-GE3_SO8 Q33
+1.5V AO3413L_SOT23-3 +1.5VS

1
8 1
7 2 3 1

D
2
10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

1U_0603_10V6K
6 3 1 R620

2
C594

C595

10U_0603_6.3V6M
1 1 5 1 100K_0402_5%

G
C596

C598
2

2
R607

C597
R608 R609 SUSP
35,36,41 SUSP

2
2 10_0603_5% 100K_0402_5% 470_0603_5%

3
2 2 2

1
3
1 1
40,46,47,48 SUSP# 5

6
Q76B

1
5VS_GATE Q77B SUSP R611 Q36 D 2N7002KDWH_SOT363-6
+VSBP 1 2 5

4
R610 390K_0402_5% 2N7002KDWH_SOT363-6 SUSP# 2 1 2 R622
47K_0402_5% 1 G 2 SUSP 10K_0402_5%

4
1
PR-16 C599 S 2N7002KW 1N SOT323-3

3
0.01U_0402_25V7K C600 2N7002KDWH_SOT363-6

2
6 0.22U_0603_16V7K Q76A

2
2

SUSP 2
+1.5V_CPU_VDDQ +0.75VS
Q77A
1

2N7002KDWH_SOT363-6 PR-16

1
+
3
V
A
L
W
T
O
+
3
V
S

1
R624 R623 +1.5V
220_0402_5%~D 22_0603_5%~D

1
2
+3VALW U39 +3VS +5VALW +5V_PCH R628

+1.5V_CPU_VDDQ_CHG

+DDR_CHG
SI4178DY-T1-GE3_SO8 R613
@ 470_0402_5%
8 1 1 2

2
7 2 0_0603_5%

2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K
6 3 1 1
1 1 5
C601

C602 R614

+1.5V_D
C604

C605

220_0603_5% 20mil
4

2 2 Q39

1
2 2

D
3 1

3
0.1U_0402_16V7K
C608

20K_0402_5%
R617
3

3
AO3419L 1P SOT23-3 1

G
2
2 2
+VSBP 2 1 3VS_GATE 2 5
9 RUN_ON_CPU1.5VS3#
R616 200K_0402_5% Q74B 5 SUSP Q72B SYSON# 5
2N7002KDWH_SOT363-6 PCH_PWR_EN# 2 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6 Q73B

4
1 Q72A 2N7002KDWH_SOT363-6
4

4
6

C609 @
0.1U_0402_25V6 R629
SUSP 2
2
0_0402_5%
Q74A R630
1

2N7002KDWH_SOT363-6 SUSP 1 2

0_0402_5%
PR-7 +5VALW
PR-16

1
+1.05VS +VCCP
+5VALW R619
100K_0402_5%

2
1
+3VALW +3V_PCH R626 SYSON#
R612

1
R627

6
2 @ 1 R718 470_0402_5%
0_0805_5% 100K_0402_5% 470_0402_5%

2 +V1.05S_VCCP_D
2
Q38 Q73A
40,47 SYSON 2
AO3404AL_SOT23 PCH_PWR_EN# 2

1
2N7002KDWH_SOT363-6

+V1.05S_D
40mil

1
3
R621
D

1 3
0.1U_0402_25V6

0.1U_0402_25V6

1 10K_0402_5%
1

2
10U_0603_6.3V6M
C603

C607 1 1
C1047

3 C606 5 3
G

40 PCH_PWR_EN
2

2
10U_0603_6.3V6M R615 Q71B
2

3
2 470_0603_5% 2N7002KDWH_SOT363-6
4

2 2
1

R735
100K_0402_5% SUSP 2 SUSP 5
Q75B
2
6

PR-14 2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

4
Q75A
+VSBP R618 2 1 3V_GATE
200K_0402_5% 2 PCH_PWR_EN#
2

2N7002KDWH_SOT363-6
1M_0402_5%

1
1
1

Q43 D R813 Q71A

PCH_PWR_EN# 2 @ C610
G 0.1U_0402_25V6
2N7002KW 1N SOT323-3 S 2
3

PR-9

PR-16

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/1212 Deciphered Date 2012/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 42 of 61
A B C D E
 A B C D

PL1 For KB930 --> Keep PU1 circuit

DCIN jack P/N:SP02000N000, HCB2012KF-121T50_0805 PH1 under CPU botten side :
(Vth = 0.825V)
need doble confirm P/N with ME 1 2 VIN CPU thermal protection at 93 +-3 degree C
PL2 For KB9012 (Red square) --> Remove PU1 circuit, but keep PR56
HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
ADPIN 1 2
PH1, PR2, PQ1, PR7,PQ15,PR73,PR56
VL +3VL
CONN@

1000P_0402_50V7K

1000P_0402_50V7K

21.5K_0402_1%
100P_0402_50V8J
ACES_88299-0610

1
39,43 ADP_I

12.1K_0402_1%
100P_0402_50V8J
GND 8

1
1K_0402_1%
1
GND 7 1

PC1

PC2

PC3

PC5

PR56

PR3
@PC4
@ PC4
6 6

PR2
0.1U_0603_16V7K
5 5

2
@
4 4

2
3 3 +3VS @

2
PU1
2 2 NTC_V
1 1 1 VCC TMSNS1 8

100K_0402_1%
PJPDC1 2 7 OTP_N_002 2 1
GND RHYST1

100K_0402_1%_TSM0B104F4251RZ
PR5
3 6 Turbo_V @PR4
@ PR4
5,39 H_PROCHOT# OT1 TMSNS2 10K_0402_1%
@ 4 5 ADP_OCP_2 1 2
OT2 RHYST2

1
1
1

2
D

20K_0402_1%
G718TM1U_SOT23-8 @PR6
@ PR6

PH1
@ PQ1 2ADP_OCP_1 29.4K_0402_1%

OTP_N_003

PR7

39 NTC_V
SSM3K7002FU_SC70-3 G
S

2
Change DC040007T0L to DC041112050

1
39 Turbo_V
@PR9
@ PR9
PL3 0_0402_5%
HCB2012KF-121T50_0805 39 PROCHOT 1 2 2 1 MAINPWON 39,44
1 2 @PR73
@ PR73 0_0402_5%

VMB
GND 11 PL4
GND 10 HCB2012KF-121T50_0805
9 9
8 8 1 2 BATT+
B+
3 1
+VSBP
7 7

0.01U_0402_25V7K

0.22U_0603_25V7K

0.1U_0603_25V7K
6 6

100K_0402_1%
10U_0805_25V6K
EC_SMCA
5 5

PC9
EC_SMDA
4 4

1
PC128

PR13
2
TS_A 2

3 3
2

PC7

PC8
2 2

2
1 1
PR27 PC6 VL

2
PJSOT24CW_SOT323-3

1K_0402_1% 1000P_0402_50V7K PQ3

2

2
1

PJP2 PR14 TP0610K-T1-E3_SOT23-3

@SUYIN_200045GR009MX8SZR 22K_0402_1%
1
PD1

1 2 VSB_N_001

1VSB_N_003
@ PR16
100K_0402_1%
2

PR18

1
0_0402_5% D

44 POK 1 2VSB_N_002 2 PQ4

@ PD2
@PD2 G SSM3K7002FU_SC70-3

.1U_0402_16V7K
PJSOT24CW_SOT323-3 S

3
1

PC10
2
1
3

2
1 2 EC_SMB_CK1 39,43
PR28 100_0402_1%

1 2 EC_SMB_DA1 39,43
PR31 100_0402_1%

1 2 +3VALW
PR29 100K_0402_5%

3 3

1 2 PJ3
BATT_TEMPA 39
PR30 1K_0402_1%
2 1
+CHGRTC 2 1 +3VL
JUMP_43X39
VIN
2

@
PD3
LL4148_LL34-2

RTC Battery
VS_N_001
1

@PD4
@ PD4
LL4148_LL34-2 PBJ1

BATT+ 2 1
Must close PBJ1
+
1

@
@PR19
@ PR19 PR20
@ PQ5
@PQ5 68_1206_5% 68_1206_5% 2 1
TP0610K-T1-E3_SOT23-3 - + +RTCBATT
2

N1 3 1
VS
1

@ LOTES_AAA-BAT-054-K01
1

@ PC12 CONN@
@PR23
@ PR23 PC11 0.1U_0603_25V7K
100K_0402_1% 0.22U_0603_25V7K
2

Change RTC For Cost Down

2

4 4

37 51_ON#
@ 1 2 VS_N_002 SP07000H700
PR24 22K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/01/23 2010/01/23 Title
For KB9012 --> Remove all 51_ON# circuit Issued Date Deciphered Date SCHEMATIC A8222
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 43 of 61
A B C D
 A B C D

for reverse input protection

1
PQ106 D
2
G SI1304BDL-T1-E3_SC70-3
S

3
PR103 PR104
1 2 1 2

1
1M_0402_5% 3M_0402_5% 1

1UH_FDSD0630-H-1R0M-P3_11A_20%
VIN PQ101 P1 P2 B+ PQ103
TPCA8059-H_PPAK56-8-5 PQ102 PR101 DMG4406LSS-13 1N SO8
DMG4406LSS-13 1N SO8 PL102 0.01_1206_1%
1 1 8 1 2 1 4 8 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2 2 7 7 2

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5 3 3 6 2 3 6 3
2200P_0402_50V7K

0.1U_0402_25V6

1
5 5

PC111

PC101
1

1
0_0402_5%

PC129

PC130

PC105

PC104

PC103

PC102

0.01U_0402_50V7K
@ PR105

1
VIN

0_0402_5%
PC110

PR106
4

PC114
2

2
@
PC112

2
1

2
3

2
@

0.1U_0402_25V6

2
PD101
2

BQ24725_ACDRV_1 BAS40CW_SOT323-3

1
BQ24725_BATDRV 1 2BQ24725_BATDRV_1

PC115
0.047U_0402_25V7K PR107

1 1

10_1206_1%
1 2 4.12K_0603_1%
PC116

PR110
PC113 1 2
0.1U_0402_25V6

5
2.2_0603_5%
PR111
PD102

BQ24725_VCC
0.1U_0603_25V7K

2
RB751V-40_SOD323-2
PQ104

1
AON7408L

PC117

BQ24725_ACP

BQ24725_BST 2

BQ24725_REGN2
1 2DH_CHG1
4
4.12K_0603_1%

4.12K_0603_1%

2
PC118 PR125 2

BQ24725_LX
2
1

1 2 DH_CHG BATT+
PR108

PR109

0_0402_5%

DH_CHG
PL101
1U_0603_25V6K PC119 4.7UH_ETQP3W4R7WFN_5.5A_20% PR102

3
2
1
0.02_1206_1%

BQ24725_ACN
1 2
BQ24725_LX 1 2 CHG 1 4
2

1U_0603_25V6K

5
6
7
8
20

19

18

17

16
2 3
PU101

2200P_0402_50V7K

0.01U_0402_50V7K
CSON1
CSOP1
1

680P_0402_50V7K 4.7_1206_5%
PQ105

VCC

PHASE

BTST
HIDRV

REGN

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR114
21 AO4468L_SO8

0.1U_0402_25V6

0.1U_0402_25V6
PAD

PC108

PC109
PC120

PC106

PC107
1

1
1 15 DL_CHG 4
ACN LODRV @

PC121

PC122
2

2
2 14 @
ACP GND PR115

3
2
1

2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_1%

PC123
BQ24725_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR116

2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1 @

2
ACDRV SRN

+3VALW 1 2 BQ24725_ACOK 5 ACOK BATDRV 11 BQ24725_BATDRV PC124

@PR117
@ PR117 10K_0402_1% 0.1U_0603_16V7K
ACDET Remember to change PC124 from SE000006S80

IOUT

SDA

ILIM
SCL
to SE025104K80 (2011-02-22)
1 2 Pre_chg +3VALW
+3VL
6

10
PR126 10K_0402_1%
PR119
1

3 3

BQ24725_ILIM 1 2

0.01U_0402_25V7K
1 2 @ PD8
@PD8
14,20,39 ACIN

100K_0402_1%
PR118 10K_0402_1% RB751V-40_SOD323-2 120K_0402_1%

PC125
PR121

1
BQ24725_ACDET
2

VIN 1 2

2
154K_0402_1%

PR120
2
1

255K_0402_1%
PR122
2

Vin Dectector
0.1U_0402_25V6

66.5K_0402_1%

EC_SMB_CK1 39,42
1

Min. Typ Max.

1

100_0402_5%
PR123
PC126

PR124

H-->L 17.23V
EC_SMB_DA1 39,42
2

L--> H 17.63V
2

PC127
1

2 1 ADP_I 39,42
ILIM and external DPM 100P_0402_50V8J
3.97A
Please locate the RC
Near EC chip
4 2011-02-22 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 44 of 61
A B C D
 A B C D E

2VREF_51125

1
PC308
1U_0603_16V6K

2
1 1

PR301 PR305
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR302 PR306
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 FB_3V FB_5V 1 2
HCB2012KF-121T50_0805

1 2 +3VLP

ENTRIP2

ENTRIP1
PR303 PR307
2200P_0402_50V7K

2200P_0402_50V7K

10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6

0.1U_0402_25V6
133K_0402_1% 174K_0402_1%
680P_0603_50V7K

1 2 1 2
1

1
PC309

PC310

PC304

PC311

PC312

PC306
1
PC322

1
PU301
2

5
ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
2

1
@ PC313
4 10U_0805_6.3V6M 25
PQ303 P PAD

2
AON7408L

2
0_0402_5%
7 24 4 PQ305
VO2 VO1 AON7408L

1
2
3

0_0402_5%
PR318
PC314 8 23 PR309 PC315
VREG3 PGOOD

PR323
0.1U_0402_10V7K PR308 2.2_0402_5% 0.1U_0402_10V7K
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2

3
2
1
2 2.2_0402_5% BOOT2 BOOT1 2
PL303 UG_3V 10 21 UG_5V PL305

1
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE2 UGATE1 2.2UH_ETQP3W2R2WFN_8.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP 8 PHASE2 PHASE1
7
6
5

5
LG_3V 12 19 LG_5V
LGATE2 LGATE1

SKIPSEL
1

1
4.7_1206_5%

4.7_1206_5%
150U_V_6.3VM_R18

150U_V_6.3VM_R18
VREG5
PR312

PR313
1 PR314 1

GND

VIN
499K_0402_1%

NC
EN
PC303

PC305
4 1 2 4 +
B++ POK 42
@ @
1 SNUB_3V 2

13

14

15

16

17

18

SNUB_5V 2
RT8205LZQW(2)_WQFN24_4X4
2 EN0 PQ306 2
PQ304 FDMC7692S_MLP8-5
1
2
3

3
2
1

680P_0402_50V7K
AO4468L_SO8 VL

1
680P_0402_50V7K

1
PC316

PC317
PR315
95.3K_0402_1% PC320
1U_0603_10V6K
2

2
1
@ @
PC318
4.7U_0805_10V6K

2
1
B++
PC319

2
0.1U_0603_25V7K
ENTRIP1

ENTRIP2

2VREF_51125

3 3
6

D D
PQ307A 2N_3_5V_001 5 PQ307B
SSM6N7002FU_US6 G G SSM6N7002FU_US6

S S +3VLP +3VL
1

PJP302
2 1

PAD-OPEN 2x2m
PR322
2.2K_0402_1% PR317
1 2 100K_0402_5%
37,39 EC_ON PR321
0_0402_5%
1 2 VL
1

PJP305
1 2
39,42 MAINPWON PQ308
+5VALWP 1 2 +5VALW (5A,200mils ,Via NO.= 10)
DRC5115E0L_SOD323-3
PAD-OPEN 4x4m
1 2 N_3_5V_002 2
VS PJP303
42.2K_0402_1%

4.7U_0805_25V6-K

@ PR319 1 2 +3VALW (4A,120mils ,Via NO.= 8)

+3VALWP
1

100K_0402_1%
1
PR320

PC321

PAD-OPEN 4x4m
3
2

@
2

4 4

For KB930 --> Keep PR319, Remove PR322

For KB9012 (Red square) --> Remove PR319
Keep PR322 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 45 of 61
A B C D E
 A B C D

1 1

PL402 PU401 PL401

4
HCB1608KF-121T30_0603 1UH_FDSD0630-H-1R0M-P3_11A_20%
1 2 VIN_1.8VSP 10 2 LX_1.8VSP 1 2

PG
+5VALW PVIN LX +1.8VSP

68P_0402_50V8J
9 PVIN LX 3

1
1

1
PC404
4.7_1206_5%
PC403 8 SVIN

PR403
22U_0805_6.3V6M PR401
6 20K_0402_1%

2
FB

22U_0805_6.3V6M

22U_0805_6.3V6M
5

2
EN

1
NC

NC
TP

PC401

PC402
FB_1.8VSP

11

2
SNUB_1.8VSP
2
39,41,46,47,48 SUSP# 1 2 EN_1.8VSP 2

1
PR404

0.1U_0402_10V7K
0_0402_5% SY8033BDBC_DFN10_3X3 PR402

1
10K_0402_1%

PC405

2
680P_0603_50V7K
@ PR405
@PR405
47K_0402_5%

PC406
2
@

2
PJP401
+1.8VSP 1 2 +1.8VS (3A,120mils ,Via NO.= 6)
PAD-OPEN 4x4m

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 46 of 61
A B C D
 5 4 3 2 1

0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
PL502
HCB1608KF-121T30_0603 OCP Current 0.9A
D B+ 1 2 1.5V_B+ D
PR504
BST_1.5V 1 2 BOOT_1.5V +1.5V
2.2_0402_5%
680P_0603_50V7K

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

4.7U_0805_25V6-K
PR511
DH_1.5V_1 1 2 DH_1.5V +0.75VSP
1

1
PC516

0.22U_0402_10V6K
0_0402_5%

PC504

PC505

PC502

PC503

PC506

10U_0805_6.3V6K

10U_0805_6.3V6K

10U_0805_6.3V6K
SW_1.5V
2

2
@

1
PC507

PC508

PC517
@

1
5
DL_1.5V

16

17

18

19

20
PU501

2
PHASE

UGATE

BOOT

VTT
VLDOIN
21 @
PAD
4 15 LGATE VTTGND 1

PQ501 PR505 14 2
PL501 AON7408L 20K_0402_1% PGND VTTSNS

1
2
3
1UH_FDSD0630-H-1R0M-P3_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC509 CS RT8207MZQW_WQFN20_3X3 GND

5
1U_0603_10V6K
1 2 12 4 VTTREF_1.5V
PR507 VDDP VTTREF
330U_D2_2.5VY_R15M

1 5.1_0603_5%
C
+
1 2 VDD_1.5V 11 VDD VDDQ 5 +1.5VP C
PC501

PGOOD
@ PR506 4

1
4.7_1206_5%

TON
PQ502 +5VALW PC511

FB
S5

S3
SNUB_+1.5VP 2

1
2 FDMC7692S_MLP8-5 0.033U_0402_16V7K

2
PC510

1
2
3

10

6
1U_0603_10V6K
+5VALW

2
PR501
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP

TON_1.5V
1

@ PC512
680P_0402_50V7K
2

Mode Level +0.75VSP VTTREF_1.5V

2
PR503
S5 L off off

1
887K_0402_1% PR502 PC513
S3 L off on PR508 1.5V_B+ 1 2 10K_0402_1% .1U_0402_16V7K
S0 H on on 0_0402_5%

2
1 2 EN_1.5V
39,41 SYSON

1
Note: S3 - sleep ; S5 - power off

EN_0.75VSP
1 @ PC514
0.1U_0402_10V7K
B B
2

PR510
0_0402_5%
PJP501
2 1
1 2 39,41,45,46,47 SUSP#
PAD-OPEN 4x4m

1
PJP502
1 2 +1.5V (9A,360mils ,Via NO.= 18) @ PC515
+1.5VP
0.1U_0402_10V7K

2
PAD-OPEN 4x4m

PJP503

+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)

PAD-OPEN 3x3m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 47 of 61
5 4 3 2 1
 5 4 3 2 1

PL702
HCB1608KF-121T30_0603
+1.05VSP_B+ 2 1
B+
+3VS

2200P_0402_50V7K

680P_0603_50V7K
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1

1
PC704

PC705

PC702

PC703

PC711
D D

2
PR712

5
100K_0402_1% @

2
PR703 PC706
4.7_0402_5% 0.22U_0402_10V6K 4 PQ701
49 +V1.05S_VCCP_PWRGOOD
1 2 BST1_+1.05VSP 1 2 AON7518

PU701
PR704 1 10 BST_+1.05VSP

3
2
1
80.6K_0402_1% PGOOD VBST
PR711
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP 1 2 UG_+1.05VSP1 PL701
TRIP DRVH 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
0_0402_5%
EN_+1.05VSP 3 EN SW 8 SW_+1.05VSP 1 2 +1.05VSP

5
PR705 FB_+1.05VSP 4 7
0_0402_5% VFB V5IN
+5VALW

330U_D2_2.5VY_R15M
1
1 2 RF_+1.05VSP 5 6 LG_+1.05VSP 1
39,41,45,46,48 SUSP# TST DRVL

1
+

PC701
11 PR706
TP
1

PC707 4 4.7_1206_5%
1

TPS51212DSCR_SON10_3X3 1U_0603_10V6K PQ702

1SNUB_+1.05VSP2
@ PC708 PR707 MDU1512RH 2
0.1U_0402_16V7K 470K_0402_1%
2

1
PC766
2

3
2
1
C .1U_0402_16V7K C

2
@ PC710 @ PR709 PC709
1000P_0402_50V7K 1.2K_0402_1% 680P_0402_50V7K

2
1 2 +1.05VSP1 1 2 +1.05VSP

PR701 PR708
4.99K_0402_1% 100_0402_1%
2 1 VCCIO_SENSE1 2 1 VCCIO_SENSE 8,46
2

PR702
10K_0402_1%
1

PJP701
1 2
PAD-OPEN 4x4m

PJP702
B +1.05VSP 1 2 +1.05VS (12A,480mils ,Via NO.= 24) B
PAD-OPEN 4x4m

PJP606
1 2
PAD-OPEN 4x4m

PJP607
+1.05VSP 1 2 +VCCP
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 48 of 61
5 4 3 2 1
 5 4 3 2 1

The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. VID [0] VID[1] VCCSA Vout
0 0 0.9V
D D
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network

2
@ PC805
680P_0402_50V7K

1 SNUB_+VCCSA
+VCC_SAP
TDC 4.2A
Peak Current 6A

2
@ PR801 OCP current 7.2A
4.7_1206_5%

1
PL803 PU801 PL801
HCB1608KF-121T30_0603 SY8037BDCC_DFN12_3X3 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
+5VALW 1 2 +VCCSA_PWR_SRC 12 PVIN LX 1
+VCCSA_PHASE 1 2 +VCCSAP
11 PVIN LX 2
PC815

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
68P_0402_50V8J 10 3 PR804 39 SA_PGOOD
SVIN LX

2
PC801

PC802

PC803

PC804
2200P_0402_50V7K

22U_0805_6.3V6M

22U_0805_6.3V6M
100K_0402_5%

0.1U_0603_25V7K
C +VCCSAP_FB
2 1 9 4 2 1 C
2 FB PG +3VS

1
PC818

PC817

PC819

PC820

1
8 5 +VCCSA_EN 1 2
VOUT EN

GND
2

2
1 PR806
7 VID1 VID0 6
0_0402_5%

0.1U_0402_10V7K
13
PR812

PC809
100_0402_5%

2
1K_0402_5%

1K_0402_5%
48 +V1.05S_VCCP_PWRGOOD 2 1

PR802

PR805

2
@ PR811
0_0402_5%

1
2 1 +VCCSA_SENSE 9

H_VCCSA_VID0 9

H_VCCSA_VID1 9

PJP801
B +VCCSAP 1 2 +VCCSA B
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2010/07/20 Deciphered Date 2012/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 49 of 61
5 4 3 2 1
 5 4 3 2 1

HF: 3.3n
3P: 3.3n
2P: 33n
HF: 24K
HF: 22p 2P: 24K PUT CLOSE
HF: 2.1K HF: 2.74K HF: 4700p 2P: 10p TO GT
3P: 2.1K 2P: 5.11K 2P: 3300p 1P: 24.9K
1P: 10p Inductor
PR201 PC214 2P: 806 1P: 5.11K 1P: 1500p PC253
10_0402_1% 3300P_0402_50V7K .1U_0402_16V7K
1 2 FBA3 1 2 1 2

1500P_0402_50V7K

560P_0402_50V7K
D D

75K_0402_1%
PR203 PR204

1
1.15K_0402_1% 2.1K_0402_1% 1 2

PC261

PC250

PR205
TRBSTA# 1 2 FBA1 1 2
PR202 PH203 PR206 PC235

1
24K_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
PR208 PC240

2
1
PC236 10_0402_1% 330P_0402_50V7K 2 PR207 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K
0.033U_0402_16V7K 1 2 FBA2 1 2 PC244 1 2 22P_0402_50V8J
HF: 1.15K 165K_0402_1% HF: 1.65K

2
PR210 PC252 2P: install
3P: 1.15K 1 2 1 2 COMPA1 1 2 1 PR211 2 SWN2A 2P: 1.65K
2P: 8.06K 1P: @ 1P: 1K
PR209 2.74K_0402_1% 4700P_0402_16V7K 28.7K_0603_1% CSREFA

1
1K_0402_1% PC255 TSENSEA

2
1 PR212 2 SWN1A @ PR277 0.047U_0402_16V7K
0_0402_5%
28.7K_0603_1% HF: 28.7K PR213 6.98K_0402_1%

1
HF: 21.5K , 2P: 21.5K , 1P: 15.8K CSP1A 1 2 SWN1A 51

2
2P: 66.5K

2
21.5K_0402_1%
CSCOMPA
PC257 1P: 66.5K
9 VCC_AXG_SENSE

2
1000P_0402_50V7K

1PR215

13.7K_0402_1%
1
PC237 CSREFA 2P: install PH204

PR216
1000P_0402_50V7K
CSREFA 51

1
1P: @

2
@ PR278 PC249 100K_0402_1%_TSM0B104F4251RZ
9 VSS_AXG_SENSE
PC264 0_0402_5% 0.047U_0402_16V7K

1
CSP2A
CSP1A
1 2

1
TRBSTA#

DROOPA

CSSUMA
CSP2A

TSENSEA
1 2

COMPA
SWN2A 51

2
IMONA
FBA
.1U_0402_16V7K PR218

DIFFA

ILIMA
6.98K_0402_1%

PR221 PR220 2P: 36K

2_0603_5% 1 2 PUT CLOSE
+5VS 36K_0402_1% 1P: 26.1K

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
1 2
+VCCP PU201 TO V_GT
C C
PC259 HOT SPOT

VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD
6132_PWMA 51
2.2U_0603_10V7K
1 2 6132_VCC
1 45 PR222 PC241
VCC PWMA
1

PR228 2 44 BST3 1 2 BST3_1 1 2

VDDBP BSTA +5VS
54.9_0402_1%

PC269 PC270 0_0402_5% 3 43 2.2_0603_5% 0.22U_0402_10V6K

VRDYA HGA HG3 51
2

2
130_0402_1%

.1U_0402_16V7K .1U_0402_16V7K 1 2 VR_ON_CPU 4 42

39 VR_ON SW3 51
2

EN SWA
PR223

PR224

VR_SVID_DAT1 5 41 PC267
SDIO LGA LG3 51
PR227 VR_SVID_ALRT# 6 40 BST2 1 PR2262 BST2_1 1 2 2Phase: @
PR232 10K_0402_1% VR_SVID_CLK ALERT# BST2 2.2_0603_5% 0.22U_0402_10V6K
7 39 HG2 51
SCLK HG2 1Phase: install

1
51.1K_0402_1% 1 2 VBOOT 8 38 Option for
SW2 51
1

VBOOT NCP81012BMNR2G_QFN60_7X7 SW2

8 VR_SVID_DAT 1 2VR_SVID_DAT1 1 2 ROSC_CPU 9 ROSC LG2 37 LG2 51 1 phase GFX @PR231
@ PR231
PR266 0_0402_5% CPU_B+ 1 2 VRMP 10 36 6132P_VCCP 1 2 1 2 0_0402_5%
8 VR_SVID_ALRT# VRMP PVCC
VR_HOT# 11 35 PR279 0_0402_5% PC245 2.2U_0603_10V7K
8 VR_SVID_CLK VRHOT# PGND
PR230
0.01U_0402_25V7K

VGATE 12 34 1 2
LG1 51 +5VS

2
1K_0402_1% VRDY LG1 PR265 0_0402_5% CSP2A
13 VSN SW1 33 SW1 51
1

+VCCP +3VS
PC239

14 VSP HG1 32 HG1 51

DIFF_CPU 15 31 BST1 1 2 BST1_1 1 2

CSCOMP
DIFF BST1

TRBST#
PR233

DROOP

CSSUM

DRVEN
CSREF
2
1

COMP

TSNS
CSP3
CSP2
CSP1
2.2_0603_5% PC238

PWM
IOUT
ILIM
2

PC271 PR234 PR235 0.22U_0402_10V6K

FB
47P_0402_50V8J 75_0402_1% 10K_0402_5% +5VS
1

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3P: 73.2K
2

1 PR2362
39 VR_HOT# 5,14 VGATE 2P: 41.2K

1
FB_CPU 73.2K_0402_1% Option for 3Phase: @
COMP_CPU
TRBST#

PR237 HF: 22p 2 phase CPU @PR264

@ PR264

DROOP

TSENSE
ILIM_CPU
1 2 VSN 0_0402_5% 2Phase: install
8 VSSSENSE 3P: 10p 6132_PWM 51
1

0_0402_5%
IMON

PC246 2P: 10p DRVEN 51

2
PR254 1000P_0402_50V7K CSP3 1 PR2392 CSP3
SWN3 51
2

1
1 2 VSP PC254 6.65K_0402_1%
8 VCCSENSE
2

1
21K_0402_1%

0_0402_5% 1 2 @ PR274
@PR274
0_0402_5% PC265 3P: install
B .1U_0402_16V7K 0.047U_0402_16V7K B

2
HF: 330p PR259 CSP1 CSREF 2P: @ TSENSE

2
1 2 PC263 2 122P_0402_50V8J CSP2
1

3P: 560p 1K_0402_1% CSP3

2P: 470p CSP2 1 PR2462
SWN2 51

1
PR250

6.65K_0402_1%

1
PR247 PC262 PR249 PC256 3P: 21K @PR275
@ PR275
1 2FB_CPU1 1 2 2 1COMP_CPU1
2 1 0_0402_5% PC260
PR248 PC242 49.9_0402_1% 2.74K_0402_1% 2P: 12.4K 0.047U_0402_16V7K

13.7K_0402_1%
1 2FB_CPU3 1 2 330P_0402_50V7K HF: 2.74K 4700P_0402_16V7K CSREF

2 PR251 1

2
10_0402_1%
CSREF 51
CSCOMP

0.033U_0402_16V7K 3P: 6.04K PH202

2

PR263 PR260 2P: 6.34K CSP1 1 PR2582

SWN1 51

1
TRBST# 1 2 FB_CPU2 1 2 PC243 HF: 1500p 6.65K_0402_1% 100K_0402_1%_TSM0B104F4251RZ

1
1000P_0402_50V7K @PR276
@ PR276
0.033U_0402_16V7K

1
3P: 1500p
1

10K_0402_1% 3.65K_0402_1% HF: 4700P 0_0402_5% PC248

PC266 2P: 1500p 0.047U_0402_16V7K

2
HF: 10K HF: 3.65K 3P: 1200p CSSUM CSREF
2

2
3P: 10K 3P: 3.65K 2P: 1200p
1 2
2P: 8.06K 2P: 806 PC258 1500P_0402_50V7K 1 PR2612 SWN1
23.7K_0402_1%

59K_0603_1% PUT CLOSE

2

.1U_0402_16V7K

TO VCORE
PC247

3P: 23.7K 1 2 1 PR2532 SWN2

PR252

PC268 330P_0402_50V7K 59K_0603_1% HOT SPOT

1

2P: 24.9K
1 2 1 2 1 PR2562 SWN3
1

PR262 PR255 59K_0603_1% HF: 59K

PR257 PC251 75K_0402_1% 165K_0402_1%
CSCOMP 1 2 DROOP 1 2 CSREF 3P: install 3P: 143K
2P: @ 2P: 143K
806_0402_1% 1000P_0402_50V7K 2 1
3P: 806
PH201 220K_0402_5%_ERTJ0EV224J
2P: 1K
A A
HF: 330p
PUT CLOSE 3P: 330p
TO VCORE 2P: 220p
Phase 1
Inductor

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 50 of 61
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

5
2200P_0402_25V7K

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC201

PC202

PC280

PC281

PC203

PC204

PC282

PC283
PR291 PR292

AON7518

AON7518

AON7518

AON7518
2.2_0603_5% 2.2_0603_5%

2
PQ201

PQ211

PQ203

PQ212
50 HG1 1 2 4 4 50 HG2 1 2 4 4
+VCC_CORE +VCC_CORE

3
2
1

3
2
1

3
2
1

3
2
1
D D
PL201 PL202
0.15UH 20% PCMB104T-R15MS0R485 40A 0.15UH 20% PCMB104T-R15MS0R485 40A
50 SW1 1 4 50 SW2 1 4

1
2 3 2 3

5
PR281
PR280 4.7_1206_5%
4.7_1206_5%

2
PR282 PR283

1SNUB_CPU1
2
4 PQ202 V1N_CPU 2 1 4 PQ204 V2N_CPU 2 1

SNUB_CPU2
50 LG1 CSREF 50 50 LG2 CSREF 50
FDMS0308AS FDMS0308AS
10_0402_1% 10_0402_1%

SWN1 50 SWN2 50

3
2
1

3
2
1
PC284
680P_0402_50V7K

1
PC285
PL206
HCB2012KF-121T50_0805 680P_0402_50V7K

2
B+ 2 1
CPU_B+
PL207
HCB2012KF-121T50_0805
2 1 CPU_B+

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
1 1

1
+ +

PC207

PC208

PC291

PC292
PC299 PC211 PC212
10U_0805_25V6K 100U_25V_M 100U_25V_M

2
5

5
2 2
QC 45W CPU (HF)
PR293
solution: 3+2
AON7518

AON7518
2.2_0603_5% MOS: cpu_core -->上2(AON7518)下1(FDMS0308AS)
PQ207

50 HG3 1 2 4 4 PQ213
C Gfx_core -->上2(AON7518)下1(FDMS0308AS) C
QC 45W CPU DC 35W CPU
+VCC_CORE VID1=0.9V VID1=1.05V
3
2
1

3
2
1

PL204
0.15UH 20% PCMB104T-R15MS0R485 40A
IccMax=94A IccMax=53A QC 45W CPU
50 SW3 1 4 Icc_Dyn=66A Icc_Dyn=43A solution: 3+2
Icc_TDC=56A Icc_TDC=33A MOS: cpu_core -->上1(AON7518)下1(FDMS0308AS)
1

2 3
5

R_LL=1.9m ohm R_LL=1.9m ohm

PR268
OCP~110A OCP~65A
Gfx_core -->上1(AON7518)下1(FDMS0308AS)
4.7_1206_5%
2

PQ206
50 LG3 4
FDMS0308AS DC 35W CPU
SNUB_CPU3

solution: 2+1
V3N_CPU 2 PR2711 MOS: cpu_core -->上1(AON7518)下1(FDMS0308AS)
CSREF 50
3
2
1

10_0402_1% Gfx_core -->上1(AON7518)下1(FDMS0308AS)

1

PC296
680P_0402_50V7K SWN3 50
2

CPU_B+
CPU_B+ 2Phase: install
B 1Phase:: @ B

2200P_0402_25V7K
PR284

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
BSTA1 1 2 BSTA1_1

1
PC209

PC210

PC293

PC294
2.2_0603_5%
5

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
0.22U_0402_10V6K
1

2
1

5
PC205

PC206

PC287

PC288

PC286 BSTA2 1 PR288 2 BSTA2_1

PC295
2

1
AON7518

AON7518

2.2_0603_5% 0.22U_0402_10V6K
2

2
PQ205

PQ214

4 4

AON7518

AON7518
2

PQ209

PQ215
PU202 4 4
1 9 PR294 +VCC_GFXCORE_AXG
BST FLAG 0_0603_5% PU203 +VCC_GFXCORE_AXG
3
2
1

3
2
1

2 8 HG1A 1 2 PL203 1 9 PR295

50 6132_PWMA PWM DRVH BST FLAG
PR285 0.15UH 20% PCMB104T-R15MS0R485 40A 0_0603_5%

3
2
1

3
2
1
50 DRVEN 2 1EN_GFX1 3 EN SW 7 SW1A 1 4 50 6132_PWM 2 PWM DRVH 8 HG2A 1 2 PL205
2K_0402_1% 0.15UH 20% PCMB104T-R15MS0R485 40A
2 1VCC_GFX1
2 1 4 VCC GND 6 2 3 50 DRVEN 2 PR267 1EN_GFX2 3 EN SW 7 SW2A 1 4
5

PR272 PR289 2K_0402_1%

1

+5VS 0_0402_5% 0_0402_5% 5 LG1A +5VS 2 1VCC_GFX22 1 4 6 2 3

DRVL VCC GND
V1N_GFX

5
PR273 PR290

V2N_GFX
1

1
NCP5911MNTBG_DFN8_2X2 PR286 0_0402_5% 0_0402_5% 5
4.7_1206_5% DRVL
1
PC289 4 2 PR287 1 NCP5911MNTBG_DFN8_2X2 PR269
1SNUB_GFX1

CSREFA 50 50 CSREFA
2

2.2U_0603_10V7K PC298 4.7_1206_5% PR270

PQ208 10_0402_1% 2.2U_0603_10V7K LG2A 4 2 1
2

2
FDMS0308AS 10_0402_1%
PQ210

SNUB_GFX2
SWN1A 50
3
2
1

FDMS0308AS
PC290

3
2
1
680P_0402_50V7K SWN2A 50
2

1
PC297
680P_0402_50V7K

2
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2009/12/01 Deciphered Date 2010/12/31 Title

R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 51 of 61
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+VCC_CORE +VCC_GFXCORE_AXG
5 x 22 µF (0805)
1

1
PC1101 PC1102 PC1103 PC1104 PC1105
Socket Bottom 5 x (0805) no-stuff
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M sites
2

2
D +VCC_GFXCORE_AXG D

7 x 22 µF (0805)
Socket Top 2 x (0805) no-stuff
sites
1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1

PC1151

PC1152

PC1153

PC1154

PC1155

PC1156

PC1157

PC1158
PC1106 PC1107 PC1108 PC1109 PC1110
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2

2
2 2 2 2 2 2 2 2 +VCCP
+VCC_CORE +VCCP

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1

PC751

PC752

PC753

PC754

PC755

PC756

PC757

PC758

PC759

PC760

PC761
PC1111 PC1112 PC1113 PC1114 PC1115
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1

PC1159

PC1160

PC1161

PC1162
2 2 2 2

22U_0805_6.3V6M
1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1 1 1 1

PC762

PC763

PC764

PC765
+ + +
PC1116 PC1117 PC1118 PC1119 PC1120
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
C 2 2 2 2 2 2 2 2 2 C
1 1 1

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
PC1164

PC1165

PC1166
+ + +
@
2 2 2
1 1 1 1 1 1
PC1121 PC1122 PC1123 PC1124 PC1125 PC1126
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2

+VCC_CORE
Chief River 330uF*9m 470uF*4.5m 22uF 10uF
1 1 1 1 1
@ @
+ PC1127 + PC1128 + PC1129 + PC1130 + PC1131
330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y

2 2 2 2 2 8layer for DC CPU 16 10

4
B B

8layer for QC CPU 5 16 10

6layer for DC CPU 5 16 10

6layer for QC CPU 4 1 16 10

GFX_CORE DC 2 12

GFX_CORE QC 3 12

1.05V_VCCP 2 12
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 52 of 61
5 4 3 2 1
 A B C D

+VGA_B+
PL903
HCB2012KF-121T50_0805
1 2 B+
PL904
HCB2012KF-121T50_0805

2200P_0402_50V7K

10U_0805_25V6K
1 2

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1P : @

1
PC971
1

1
PC936

PC937

PC907

PC908
2P: install

2
1 1
PR917

2
2
68K_0402_1%

5
2 1
PR902 PQ903
0_0402_5% AON7518
PR903

20
20
20
20
20
20
150K_0402_1% @ PQ905
1 2 VRON_VGA 4 4 AON7518

GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
15,20,29 DGPU_PWR_EN

PR904 PC938
2.2_0603_5% 0.22U_0603_10V7K
1 2 1P : @

3
2
1

3
2
1
PC939 .1U_0402_16V7K BOOT2_VGA 2 1BOOT2_2_VGA 1 2 PR911
2.2_0603_5%
UGATE2_VGA 2 1 UGATE2_VGA1 PL902
2P: install
+VGA_CORE
0.36UH_FDUM0640J-H-R36M-P3_22A_20%
1 2 DPRSLPVR_VGA PHASE2_VGA 1 4
PR905 10K_0402_1%

5
1P: @ LF2_VGA 2 3 V2N_VGA

GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
2P: 1.91K

10K_0402_1%
3.65K_0805_1%
PQ904

1
+3VS PR910 FDMS0309S_POWER56-8-5

GPU_VID6

PR907
1.91K_0402_1% PR909

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1

PR908
1 2 CLK_ENABLE#_VGA LGATE2_VGA 4 PR906 1_0402_1%
+ + +

PC903

PC904

PC910
4.7_1206_5%
1

HW端有PULL

SNUB2_VGA 2

2
PR915
1.91K_0402_1% 2 2 2

3
2
1
@ PD901
RB751V-40TE17_SOD323-2
2

2 1 VSUM+_VGA ISEN2_VGA VSUM-_VGA

29,39 VGA_PWROK
1P: @ PR918

1
100K_0402_5% PC940
2P: 100K 1 2 680P_0402_50V7K
+3VS

2
2 PR919
47K_0402_1%
+VGA_CORE Under VGA Core 2

PR912
2 1 +VGA_CORE Near VGA Core
100K_0402_5% 1P : @ PC941
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

+3VS 1 2
PU901 2P: install 1 2
PR913

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
CLK_EN#
DPRSLPVR

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON
PSI#_VGA
RBIAS_VGA

0_0402_5%

1
PC923

PC920

PC921

PC922

PC924

PC925

PC911

PC919

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 2 BOOT2 30 1 1 1 1

1
20 ACIN_BUF

PC930

PC929

PC928

PC927
UGATE2 29
1 28 PC926

2
PGOOD PHASE2 47U_0805_6.3V6M
2 27

2
PR914 PSI# VSSP2 PR920 2 2 2 @ 2 @
3 RBIAS LGATE2 26
11.3K_0402_1% VGA_VR_TT# 4 25 VCCP_VGA1
1 2 VCCP_VGA 1 2 +5VS
VR_TT# VCCP
1 2NTC_MOS_VGA 1 2 NTC_MOSFET_VGA 5 NTC PWM3 24 0_0402_5% PR921 0_0402_5%
VW_VGA 6 23
PH902 COMP_VGA VW LGATE1
7 COMP VSSP1 22
470K_0402_5%_TSM0B474J4702RE FB_VGA

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
8 FB PHASE1 21
1 2 ISEN3_VGA 9 ISEN3

1
UGATE1

PC912

PC913

PC914

PC915

PC916

PC917

PC918

PC931

PC932

PC933

PC934

PC935
10
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN
1000P_0402_50V7K

IMON

@ PC942
VDD
RTN

1
VIN
249K_0402_1%

8.06K_0402_1%

22P_0402_50V8J 41 PC943

2
AGND
2

1U_0603_10V6K @ @ @ @ @
1
PR922

PR923

PC944

ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20

PR924
499_0402_1% PC945
2

ISUM-_VGA

@ 1 2FB1_VGA1 2
VDD_VGA
RTN_VGA
1

@ PR945
680P_0402_50V7K 0_0402_5%
PC946 PR926

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
2 1
47P_0402_50V8J 3.48K_0402_1% VGA的電容用料 (20W ~ 35W的bulk cap都用330uF_9m * 4)

1
PC968

PC965

PC966

PC967

PC969

PC970

PC963

PC964
1 2 1 2 VSEN_VGA IMON_VGA 1 2 +5VS
PR925 0_0402_5% 35W--> 5 * 0.1uF +15 * 4.7u + 22u * 3 + 330_9m * 4

2
ISEN2_VGA VIN_VGA 1 2 +VGA_B+ @ @ @ @
1 2FB2_VGA1 2 PR927 0_0402_5%
ISEN1_VGA +VGA_B+
PC947 PR928 PR929 1 21_0402_5%
0.22U_0402_10V6K

0.22U_0402_10V6K

3 3
+5VS
1

150P_0402_50V8J 267K_0402_1%
1U_0603_10V6K

0.22U_0603_25V7K

1P: 120K PR930

2

1
PC948

PC949

PC950

PC951

249K_0402_1%
2P: @249K

2200P_0402_50V7K
@ PR944

10U_0805_25V6K

10U_0805_25V6K
BOOT1_VGA

0.1U_0402_25V6
1P: 68nF
2

5
0_0402_5%
2

2P: 0.022uF

1
PC952

PC953

PC905

PC906
1

1P: install PR916

2
1P: @ VSUM+_VGA 2.2_0603_5%
2P: @ 2P: 0.22u UGATE1_VGA 2 1 UGATE1_VGA1 4 4
+5VS VSUM-_VGA
+VGA_CORE 1 2
PR934 PC954
1

82.5_0402_5%

2.61K_0402_1%

PR931 2.2_0603_5% 0.22U_0603_10V7K PQ901

3
2
1

3
2
1
1
PR932

10_0402_5% 2 1 BOOT1_1_VGA 1 2 AON7518 @ PQ906

PR933

AON7518
PL901 +VGA_CORE
22 VCCSENSE_VGA 1 2 @ 0.36UH_FDUM0640J-H-R36M-P3_22A_20%
2

PHASE1_VGA 1 4
2

5
PR935
0.22U_0603_10V7K

0.022U_0603_25V7K
VSUM_VGA_N001
1

0_0402_5% 2 3 V1N_VGA
NTC_VGA
1
11K_0402_1%

@ PC955 LF1_VGA
1

1
PC956

PC957

PR941

330P_0402_50V7K
2

1
10K_0402_1%
3.65K_0805_1%
LGATE1_VGA

330U_D2_2V_Y

330U_D2_2V_Y
4 1 1
2

PR937

PR938
PR936
0.01U_0402_25V7K

+ +

PC901

PC902
330P_0402_50V7K

PQ902 4.7_1206_5% PR939

1
PC959

PC960

FDMS0309S_POWER56-8-5 1_0402_1%

2
1

PC958 PH901

3
2
1

2
PR940 0.01U_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ 2 2

SNUB1_VGA
0_0402_5%
2

22 VSSSENSE_VGA 1 2 @ @ 1P : @
2

Layout Note: 2P: install

PR942 PR943 Place near Phase1 Choke VSUM+_VGA ISEN1_VGA VSUM-_VGA
10_0402_5% 1.58K_0402_1%

1
4 4
1 2 1 2 VSUM-_VGA
PC961
680P_0402_50V7K

2
1

1P: @ 1P: 866 1P: 0.1uF PC962

0.1U_0402_16V7K
2P: 1.58K 2P: 0.22uF 20W 25W ~30W
2

solution:1P solution:2P
OCP:38A OCP:75A Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 53 of 61
A B C D
 5 4 3 2 1

Power block
CPU OTP
Page 56
D Turn Off D

B+
Input +3VALWP: TDC:6A
DC IN Switch Page 57 Always
+5VALWP: TDC:6.1A
RT8205LZQW(2) WQFN Page 52

CHARGER
CC:0A~3.64A +1.8VP: TDC:1.2A SUSP#
CV:12.6V(6cell) SY8033BDBC
BQ24725RGRR Page 59

Page 57

C C
+VCCPP: TDC:8.5A SUSP#

Battery TPS51212DSCR Page 60

+V1.05SP: TDC:7.9A SUSP#

TPS51212DSCR Page 61

+1.5VP: TDC:16A SYSON

TPS51212DSCR
Page 62
+VGA_CORE
DGPU_PWR_EN
TDC:23A
B TPS51212DSCR B

Page 65 +0.75VSP: TDC:2A +3VALW

APL5331KAC-TRL
Page 62

+VCCSAP: TDC:4.2A +V1.05S_VCCP_PWRGOOD

+VCC_CORE TPS51461RGER
VR_ON
TDC: 52A Page 63

ISL95832HRTZ-T
Page 64

+VCC_GFXCORE_AXG
VR_ON
A TDC: 38A A

ISL95832HRTZ-T
Page 64

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 54 of 61
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/09/15 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 55 of 61
5 4 3 2 1
 5 4 3 2 1

Timing Diagram for G3 or S4-5/M-off (Suspend Well Off) to S0/M0 [non Deep S4/S5 Platform]

ACIN/BATT-IN

+5VALW/+3VALW

D
VCCSUS D

(+5V_PCH/+3V_PCH)

PCH_RSMRST#

PM_SLP_SUS# T3>0ms

T5<90ms
AC_PRESENT

PWRBTN_OUT# T0>16ms

PM_SLP_S5#

T9>30us
PM_SLP_S4#

T10>30us
PM_SLP_S3#
C C

CPU1.5V_S3_GATE CPU1.5V_S3_GATE may come up before SUSP# and come down after SUSP#

SUSP# T>?ms

+V1.05S_VCCP(CPU),
+V1.05S(VccASW) T=?ms

T11>1ms PCH_APWROK may come up anytime before PCH_PWROK, but not after PCH_PWROK assertion
PCH_APWROK

SA_PGOOD

T>?ms

VR_ON
T33<5ms

CPU SVID BUS

50<T36<2000us
+VCC_CORE
T37<5ms
B B

VGATE

PCH_PWROK T14>99ms

T20>2ms

H_CPUPWRGD
T18>0ms

PM_DRAM_PWRGD 2ms<T17<650ms

SYSTEM_PWROK

SM_DRAMPWROK

+1.8VS_VCCPLL

PLT_RST# T43>100ms H_CPUPWRGD to PLT_RST# 1ms<T25<100ms

A A

Color Command

Signal Names Timing of these signals is set by PCH or processor

Signal Names Timing of these signals should be met by the platform (EC)

Signal Names Timing of these signals is set by IntelR MVP

Signal Names Voltage rails or chip-to-chip buses

Security Classification Compal Secret Data COMPAL Electronics，Inc

Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
SCHEMATIC A8222
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 56 of 61
5 4 3 2 1
 5 4 3 2 1

LA-8222P Version change list (P.I.R. List) Page 1 of 3 ( for HW internal reference only)

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
14 Delete R205

D
ER01 HW Design 0.2 05 Un-stuff R577, Stuff R576 09/21
D
Add R745,R746 for non AI
ER02 For non AI co-lay 0.2 37
AI parts change to AI@
09/21

12 Change R132/R134 PU power to +3V_SPI

ER03 +3VS Leakage HW Design 0.2 13
40
Delete Q3.A/B
Delete R552, R556
Add R135, R137 09/21

Swap U90.39/40 to U90.36/37 net

ER04 Can`t detect USB30 (JUSB2) HW Design 0.2 36 Change R1040 to 47K from 4.7K ohm
Add Reserve R1029
09/21

Add Q20,R773,R775 (10/3 - follow K45 change Dual FET

ER05 Design change for card reader 0.2 34 Reserve R768, R774
Change Card reader Conn
09/22 location from Q63 to Q20)

Change to Q3(AO3404L) from U22(AO4430L)

ER06 HW Design / VGA sequence 0.2 29 Change R433 to 0 ohm, R432 to 10K ohm
Un stuff C396
09/21

Change R1049 to 330k

ER07 HW Design 0.2 36 Change Q904 to AO3404L from AP2301GN
Delete R1046, Add R747
09/21

ER08 HW Design 0.2 42 Change Q33 to AO3413L from AP2301GN 09/21

C
ER09 HW Design 0.2 18 Add un stuff R290 09/23
C

ER10 Refer to ORB 0.2 05 Change R577.2 power rail from +3VS to +3V_PCH 10/04

Del R135, R137.

ER11 Refer to ORB 0.2 13 Change SML1CLK to PCH_SML1CLK 10/04
Change SML1DATA to PCH_SML1DATA

ER12 HW Design 0.2 40 Del Y5 , C545 , C546 10/04

Replace R230 NR with R780-R783.

ER13 Refer to purchaser suggestion 0.2 15 Replace R237 NR with R784-R787. 10/04
Replace R242 NR with R792, R793, R288.

29
ER14 Refer to purchaser suggestion 0.2 31 Change C387, C389, C399, C447, C602 PN 10/04
42

B
ER15 HW Design 0.2 40 Del U33.123 EC_CRY2 net name 10/04
B

ER16 DRAMRST_CNTRL_PCH signal timing Reserved for Instant-On function. 0.2 13 Add R750 10/04 (10/06 - Change location from R1082
to R750,
And Change its tolerance from 1% to
ER17 EMC request to reserve these caps. 0.2 36 Add C1045-C1048 10/04 5%).

ER18 0.2 43-55 Update Power circuit (1003) 10/04

ER19 Instant-On function - DRAMRST control by PCH. 0.2 13 Un-stuff R157, Stuff R750 10/06

Change H16, H17, H22 screw hole type to 3P5.

ER20 ME Design Change. 0.2 38 (dGPU & VRAM) 10/07

ER21 0.2 43-55 Update Power circuit (1011) - Del PC1163. 10/11

ER22 Refer to ORB design 0.2 14 un-stuff D2, Add R751

10/13
40 un-stuff D32, R547, Add R752
Assign U33.18 to AC_PRESENT signal.
A A

ER23 Fine-tune timing. 0.2 29 change R432 from 100R to 10K.

change R435 from 10R to 200R. 10/13
42 change R607 from 220R to 10R.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 57 of 61
5 4 3 2 1
 5 4 3 2 1

LA-8222P Version change list (P.I.R. List) Page 2 of 3 ( for HW internal reference only)

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D
ER24 Follow to ORB 0.2 05 Un-stuff R576, Stuff 0R to R577. 10/13
D
change for GPU H/W strapping STRAP1 to PL 45K
ER25 ohm to enhanced the PCIe PEG driving. 0.2 22 Change R349 from 34.8K to 45.3K 10/13

ER26 Refer to Intel review feedback item 5. 0.2 09 Add R277 0R 0805 5% 10/13

ER27 Refer to Intel review feedback item 11. 0.2 09 Add 149 10/13

ER28 Refer to Intel review feedback item 33. 0.2 31 Revise SATA P/N signals. 10/13

ER29 Refer to Intel review feedback item 37. 0.2 18 Del L6, Add R289 10/13

ER30 Refer to Intel review feedback item 40. 0.2 17 Del L4, Add R293 10/13

ER31 Refer to Intel review feedback item 42. 0.2 42 Add R230 10/13

C
ER32 Refer to Intel review feedback item 43. 0.2 42 on Stuff R244 10/18
C
Refer test report to fine-tune oscillation Change Y1 P/N,
ER33 frequency 0.2 12 Change C144, C145 to 18pF. 10/14

Refer test report to fine-tune oscillation Change Y2 P/N,

ER34 frequency 0.2 13 Change C163, C164 to 12pF.
10/14
Refer test report to fine-tune oscillation Change Y3 P/N,
ER35 frequency 0.2 20 Change C901, C900 to 12pF.

Refer test report to fine-tune oscillation Change Y4 P/N,

ER36 frequency 0.2 32 Change C469, C4735 to 12pF. 10/14

Refer test report to fine-tune oscillation

ER37 frequency 0.2 36 Change Y9 P/N.
10/14

ER38 0.2 43-55 Update Power circuit (1014) - Modify Choke footprint.

ER39 For EMI request 0.2 32 R484 and R486 change to C219 and C300 to 0.1u. 10/17

B
ER40 For LED issue 0.2 39 change LED2 footprint to LED_HT-210UD-UYG_3P 10/17
B

ER41 For EMI request 0.2 05 Add R12 0 ohm at H_CPUPWRGD 10/17

ER42 For SATA GEN2 EA pass. 0.2 31 change R671 to 3.3k ohm. 10/17

ER43 For EMI request 0.2 16 Add C151 0.1uF to GND on H_THERMTRIP# 10/17

ER44 For EMI request 0.2 33

1.GND pin3→pin1,USBN9 pin1→Pin2,USBP9 pin2→Pin3
2.GND pin5→pin7,+USB_VCCD pin6,7→pin5,6 10/17

ER45 For EMI request 0.2 33 Add L34 , L35 , reserve R552, R556 ,R748 , R749 10/17

ER46 For EMI request 0.2 5 remove T2,T3,T4,T5,T6,T7,T8,T9,T46,T47

T38,T39,T40,T41,T42,T43,T10,T11,T45 10/17
7
38
ER47 For Power request 0.2
40
Change +3VLP to +3VL 10/17

PAR8520@ : U41-U43, R671=3.3K

ER48
A A
SATA Re-driver 2nd source.
0.2 38 ASM1466@ : 1) Add R426,R405,R419,R403,R396,R417 U41-U43.
2) R459, R669, R672 = 4.7K 10/17
3) R682, R690, R698 = 2K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 58 of 61
5 4 3 2 1
 5 4 3 2 1

LA-8222P Version change list (P.I.R. List) Page 3 of 3 ( for HW internal reference only)

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

ER49 For EMI request 0.2 34 remove C620 , C611 , C631

10/18

ER50
D D
for HW design 0.2 39 change U36 PN to SA00003B900 and C583 unpop
10/18

ER51 For EMI request. 0.2 05 H_CPUPWRGD net name change to H_CPUPWRGD_R 10/20

Reserve R137 , Q63, pop R135

ER52 For T88 request for ROM WP function 0.2 12 change EC_PECI to EC_SPI_WP 10/26

ER53 For EMI request 0.2 13 Add R185 10/20

20 Change ACIN_BUF circuit

ER54 to prevent +3VSG leakage when Optimus. 0.2
40 unstuff R730 10/20

ER55 For remove MS fuction 0.2 34 Delete R637 10/20

ER56 For AP2301 EOS issue 0.2 37 change C510,C516,C519,C524 PN to SE026224K80 10/20

ER57 for EMI request 0.2 40 Add C156 , C157 10/21

C C
14 Add unstuff R800,R801,R802,R803,R804,R805
ER58 Reserve for Deep Sx 0.2
40 Add PCH_DPWROK,DS_WAKE#,SUSACK#,SUSWARN#
10/19

ER59 for EMI request 0.2 35 Change L31~L33 PN to SM070000N00 10/26

Change R668,R671 to 2K ohm for PAR8520

ER2-1 For SATA signal driving 0.3 31 Add 10K ohm (R675,R677,R683,R685) for PAR8520
Unstuff R396,R417,R698,U43 for Asm1466
11/22
Unstuff C644,C645,C646

ER2-2 For EMI request 0.3 32 Add 0.1uF (C219,C300)

11/22
Change TS1 to SP050007G00 from SP050006L00

ER2-3 For Card reader function 0.3 34 Change SDD2 to U40.21 and SDD3 to U40.20
11/22

ER2-4 For USB charge & wake function 0.3 37 Add 0 ohm (R809,R810)
11/22

ER2-5 For WIN8 0.3 12 Add U5 SPI ROM 8M for Win8

11/22

13 Connect SMBUS to click pad.

B ER2-6 For change Click Pad from Glide Pad. 0.3 39
40
Del SW3,SW4. change JTP1 Add Q64 , R808
Change PU to +3VS ( TP_CLK.TP_DATA )
12/12 B

39 Update JTP1(SP01001AE00) connector 8 pin

ER2-7 For HDMI LOYALTY 0.3 35 Add 46@ HDMI LOYALTY 11/22

ER2-8 Change Main source for HDMI power switch 0.3 35 Change U44 SA00004ZB00 to SA00004ZA00 11/22

ER2-9 For +3VSG leackag when boot first time 0.3 15 Add R443 10k pull down , unstuff R244 12/01

ER2- For N13M-GS DID 0.3 22 Update strap pin table 12/01

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 59 of 61
5 4 3 2 1
 5 4 3 2 1

LA-8225P Version change list (P.I.R. List) Page 4 of 4 ( for HW internal reference only)

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Change 2N7002 single to dual channel< Q71~Q77>
Del R625, Q64
D
ER2-10 HW Design 0.3 42 Change Q38 SI4178DY to AO3404AL
Add R813 PD 1.5M ohm
12/12
D

ER2-11 For USB3.0 chip sequence 0.3 36 Change C1011 to 2.2uf from 1uF << 0402 to 0603
Change R1040 to 51.1k +-1% ohm
12/05

29 Change 2N7002 single to dual channel <Q78~Q80>

ER2-12 HW Design 0.3 32
41
Change 2N7002 single to dual channel <Q81>
Change 2N7002 single to dual channel <Q82>
12/05

ER2-13 HW Design for power saving 0.3 12 Un stuff R111~R113 12/05

06 Change C73 SE070473Z80 to SE076473K80

ER2-14 HW Design 0.3 42
17
Change C600 SE027224Z80 to SE026224K80
Change C180 SE000008L80 to SE000000I10
12/07

12 Change 1U(0603) SE052105Z80 to SE080105K80

ER2-15 HW Design 0.3 35
42 Page PCH,HDMI,DCDC,DIMM
12/07

15 30
ER2-16 EMI EMI request 0.3 33
37
34
41
Change USB2.0 port & OC# 12/15

ER2-17 HW Design 0.3 16 Add R812 to GPIO22 PD 10k ohm , Unstuff R252 12/09

14
C
ER2-18 HW Design 0.3
40
Un-Stuff R554, Stuff R226 (Change to 10k) 12/12
C

ER2-19 Intel New chip of PCH HM76 rev.C1 0.3 PCH Change U3 PN to SA00005FH10 12/12

Change All 2n7002 to SB00009Q80 from SB00009620

ER2-20 HW Design 0.3
Change 0.1uF SE102104K00 to SE076104K80
12/12

35 Add 2pF C700~C707

ER2-21 EMI request 0.3
30 Add R820,R821 & L40(Unstuff)
12/12

ER2-22 HW Design 0.3 20 Change Q900.2 control pin to +3VSG 12/12

ER2-23 For EMI request 0.3 39 Change U36 to SA000058600 12/14

Add Reverse 100pf

ER2-24 For EMI request 0.3 29
C710~C715,C717~C723 to +1.5VSG and other power plan
12/15

ER2-25 For EMI request 0.3 05 Add R12 1k ohm and C640 0.1u Capacitor 12/19

40
B
PR-1 For ASUS request 1.0
38
Add PWR_ON_LED1# on U33 Pin 119 01/02
B

R12 change to 33ohm (SD028330A80)and C640

PR-2 For EMI request 1.0 05 change to 100p(SE071101J80) 01/03

R432 change to 100K(SD028100380)and C395 change

PR-3 For power consumption @ AC S5 1.0 29 to 0.01u (SE075103K80) 01/03

PR-4 For ENE request 1.0 39 reserve KSI4,5,6,7 cap 10p to GND 01/06

PR-5 For debug function 1.0 41 stuff R595 01/06

PR-6 For GS gen3 support 1.0 22 R352 ,R349 bom structure change to @ 01/06

change 0 ohm footrprint to R_short

PR-7 For HW design 1.0
41 change R584 footrprint 1206 to 0805 R_short
01/06

Add R445 and reserve R444

PR-8 For PLT_RST# leakage when power on 1.0 15
unstuff R234
01/06

29 Add R830 amd R831 470k ohm to GND

A
PR-9 For Mos max Vgs voltage tolerance 1.0
42 Add R813 1M ohm to GND
01/19
A

PR-10 For Asmedia SATA redriver 1.0 31 Change R690 to 1.5K ohm to GND 01/06

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/1215 Deciphered Date 2012/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 60 of 61
5 4 3 2 1
 5 4 3 2 1

LA-8222P Version change list (P.I.R. List) Page 5 of 5( for HW internal reference only)

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
36 modify asmedia power schematic
PR-11 For power consumption 1.0
40 Add USB3_ON at U33 pin 120
01/09
D D

PR-12 For EMI 1.0 33 Reserve C723~C726 1.8P capacitor to GND 01/13

30
PR-13 For HW design 1.0
34
C422,C423,C619 footprint change to 0603 from 0805 01/13

42 Change C1047 and C606 to 0.1uF

PR-14 For EMI 1.0
40 Add Reserve C1070
01/17

Change U37 to SI4178DY-T1-GE3 from AO4478

PR-15 For HW deaign 1.0 41 (WLAN power MOS) 01/17

Change R610,R724 to 390k from 47k ohm

PR-16 For power consumption @ AC S5 1.0 42 41 C599,C592 change to 0.01uF. 01/19

32 Change C475 to 10P (SE00000UO00)

PR-17 For EMI 1.0 5 Change C72 to 12P 01/30
Add C647

IRT-1 For EMI 1.A 30 Add C544 C545 02/08

C
IRT-1 For check AI charger exit or not 1.A 40 Change R743 bom structure to AI@ 02/10
C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/1215 Deciphered Date 2012/11/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 61 of 61
5 4 3 2 1
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