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Memory Initialization in VHDL

This document discusses different methods for initializing memory in VHDL, including initializing with zeroes or ones, constant values from a binary, hex or integer, values from a text file by reading the file line by line, and using a mathematical function. It provides code examples for initializing memory using each of these methods.

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ganga_ch1
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227 views

Memory Initialization in VHDL

This document discusses different methods for initializing memory in VHDL, including initializing with zeroes or ones, constant values from a binary, hex or integer, values from a text file by reading the file line by line, and using a mathematical function. It provides code examples for initializing memory using each of these methods.

Uploaded by

ganga_ch1
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Memory initialization in VHDL
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January 1, 2018

In this post we will illustrate different methods of memory initialization in Subscribe Now

VHDL, before reading this post it is recommended to read the Memory


Modeling in VHDL post SEARCH BY TAGS
Initialization with zeroes :
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The Memory can be initialized with zeroes or ones by simply setting all
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bits into Zeros or ones as follow :
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type memory is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA
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-- initialize the RAM with constants
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Initialization with constant values : veriog vhdl

The memory content can be initialized using constant values written in


binary, hex or integer the following example shows the initialization of FEATURED POSTS
memory with
type memory is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA
-- initialize the RAM with constants
signal RAM:memory:=(x"00", x"01", x"F0", x"34", x"44", x"00", x"01",

 
Initialization from text file :
A text file can be used to initialize the memory in VHDL, for this purpose
library textio is used. A function is written before declaring the memory
signal, this function reads the text file line by line, converts each value in
the line to std_logic_vector type and use it to initialize the memory. the
following code shows an example of initializing a memory with from text
file
- Text file
011000000001
000100000000
111100000000
011100000001
001000000000
011100000000
110000000110
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000
000000000000

- VHDL code
--------------------------------------------------------------
-- fpgagate.com: FPGA Projects, VHDL Tutorials, VHDL projects
-- Memory initialization in VHDL
--------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;

entity mem_array is
generic( DATA_WIDTH: integer := 12;
ADDR_WIDTH: integer := 8;
INIT_FILE: string := "inst_mem.txt");

port(ADDR: in std_logic_vector(ADDR_WIDTH-1 downto 0);


DATAIN : in std_logic_vector(DATA_WIDTH-1 downto 0);
CLK : in std_logic;
WE : in std_logic;
OUTPUT : out std_logic_vector(DATA_WIDTH-1 downto 0));
end mem_array;

architecture behavioral of mem_array is


--Memory array
Type MEMORY_ARRAY is array(0 to (2**ADDR_WIDTH)-1) of std_logic_vector(D

------------------------------------
-- function to initialize memory content
function init_memory_wfile(mif_file_name : in string) return MEMORY_ARRA
file mif_file : text open read_mode is mif_file_name;
variable mif_line : line;
variable temp_bv : bit_vector(DATA_WIDTH-1 downto 0);
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
readline(mif_file, mif_line);
read(mif_line, temp_bv);
temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
-------------------------------------
signal Memory: MEMORY_ARRAY := init_memory_wfile(INIT_FILE);
begin
process(clk) is
begin
if rising_edge(clk) then
if we='1' then
Memory(to_integer(unsigned(ADDR))) <= DATAIN;
end if;
OUTPUT <= Memory(to_integer(unsigned(ADDR)));
end if;
end process;

end behavioral;

 
Initialization using a mathematical function :
In this initialization method the memory arry is initialized using a
mathematical function, such as sine, cosine, linear .... etc.
a function should first be written before declaring the memory signal, this
function shall describe the required mathematical formula that will be used
to fill the memory locations. The following code shows an example of
using a linear function to initialize the memory.
--------------------------------------------------------------
-- fpgagate.com: FPGA Projects, VHDL Tutorials, VHDL projects
-- Memory Initialization in VHDL
--------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity mem_array2 is
generic( DATA_WIDTH: integer := 12;
ADDR_WIDTH: integer := 8);
port(ADDR: in std_logic_vector(ADDR_WIDTH-1 downto 0);
DATAIN : in std_logic_vector(DATA_WIDTH-1 downto 0);
CLK : in std_logic;
WE : in std_logic;
OUTPUT : out std_logic_vector(DATA_WIDTH-1 downto 0));
end mem_array2;

architecture behavioral of mem_array2 is


--Memory array
Type MEMORY_ARRAY is array(0 to (2**ADDR_WIDTH)-1) of std_logic_vector(D
------------------------------------
-- function to initialize memory content
function init_memory(DATA_WIDTH : in integer) return MEMORY_ARRAY is
variable temp_mem : MEMORY_ARRAY;
begin
for i in MEMORY_ARRAY'range loop
temp_mem(i) := std_logic_vector(to_unsigned(i,DATA_WIDTH));
end loop;
return temp_mem;
end function;
-------------------------------------
signal Memory: MEMORY_ARRAY := init_memory(DATA_WIDTH);
begin
process(clk) is
begin
if rising_edge(clk) then
if we='1' then
Memory(to_integer(unsigned(ADDR))) <= DATAIN;
end if;
OUTPUT <= Memory(to_integer(unsigned(ADDR)));
end if;
end process;

end behavioral;

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