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VHDL 5 Memory Models

VHDL FPGA

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158 views14 pages

VHDL 5 Memory Models

VHDL FPGA

Uploaded by

ganga_ch1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VHDL: Modeling RAM and Register

Files
Textbook Chapters: 6.6.1, 8.7, 8.8, 9.5.2, 11.2
Memory Synthesis
 Approaches:
 Random logic using flip-flops or latches
 Register files in datapaths
 RAM standard components
 RAM compilers
 Computer “register files” are often just multi-port RAMs
 ARM CPU: 32-bit registers R0-R15 => 16 x 32 RAM
 MIPS CPU: 32-bit registers R0-R31 => 32 x 32 RAM
 Communications systems often use dual-port RAMs as
transmit/receive buffers
 FIFO (first-in, first-out RAM)
Basic memory/register array
K bits
Word/Register 0
2N x K-bit memory Word/Register 1
N-bit Word/Register 2
Address AN-1 – A0
. 2N Words /
DINK-1 – DIN0 .
K-bit Registers
Data DOUTK-1 – DOUT0 .
Control
Signals
Word/Register 2N - 1

-- 2N x K-bit memory VHDL struture


signal MemArray: array (0 to 2**N – 1) of std_logic_vector(K-1 downto 0);
-- ARM register file is 16 32-bit registers
signal ARMregisterFile: array (0 to 15) of std_logic_vector(31 downto 0);
Example: 4 x n-bit register file
Data in Data out
Write
Address
Read
Address
Write
enable
Clock Clk
Technology-independent RAM Models
-- N x K RAM is 2-dimensional array of N K-bit words
library IEEE; ADDR
use IEEE.std_logic_1164.all; DIN NxK
use IEEE.std_numeric_std.all; DOUT RAM
WR
entity RAM is
generic (K: integer:=8; -- number of bits per word
A: integer:=8); -- number of address bits; N = 2^A
port (
WR: in std_logic; -- active high write enable
ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
DIN: in std_logic_vector (K-1 downto 0); -- write data
DOUT: out std_logic_vector (K-1 downto 0)); -- read data
end entity RAM;
RAM Models in VHDL
architecture RAMBEHAVIOR of RAM is
subtype WORD is std_logic_vector ( K-1 downto 0); -- define size of WORD
type MEMORY is array (0 to 2**A-1) of WORD; -- define size of MEMORY
signal RAM256: MEMORY; -- RAM256 as signal of type MEMORY
begin
process (WR, DIN, ADDR)
variable RAM_ADDR_IN: natural range 0 to 2**W-1; -- translate address to integer
begin
RAM_ADDR_IN := to_integer(UNSIGNED(ADDR)); -- convert address to integer
if (WR='1') then -- write operation to RAM
RAM256 (RAM_ADDR_IN) <= DIN ;
end if;
DOUT <= RAM256 (RAM_ADDR_IN); -- continuous read operation
end process;
end architecture RAMBEHAVIOR;

Multi-port RAM (two parallel outputs):


DOUT1 <= RAM256(to_integer(UNSIGNED(ADDR1));
DOUT2 <= RAM256(to_integer(UNSIGNED(ADDR2));
Initialize RAM at start of simulation
process (WR, DIN, ADDR)
variable RAM_ADDR_IN: natural range 0 to 2**W-1; -- to translate address to integer
variable STARTUP: boolean := true; -- temp variable for initialization
begin

if (STARTUP = true) then -- for initialization of RAM during start of simulation


RAM256 <= (0 => "00000101", -- initializes first 4 locations in RAM
1 => "00110100", -- to specific values
2 => "00000110", -- all other locations in RAM are
3 => "00011000", -- initialized to all 0s
others => "00000000");
DOUT <= "XXXXXXXX"; -- force undefined logic values on RAM output
STARTUP :=false; -- now this portion of process will only execute once
else
-- “Normal” RAM operations
RAM with bidirectional data bus

Copyright ©2008,Thomson Engineering, a division of Thomson Learning Ltd.


Cs_b =0 and Oe_b = 0

Data from
array
IO
Data to
array

Disable output drivers

Copyright ©2008,Thomson Engineering, a division of Thomson Learning Ltd.


Synthesizing RAM
 Previous model synthesizes to 1736 Spartan 3 LUTs (16 bits
per LUT), but could easily fit into a single “block RAM”

Spartan 3 block RAM


= 18K bits

Can instantiate Xilinx


block RAM model
Single-port distributed RAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; a
entity rams_04 is di 64x16
port ( clk : in std_logic; do LUT
we : in std_logic;
a : in std_logic_vector(5 downto 0); we RAM
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0)); clk
end rams_04;
architecture syn of rams_04 is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(a)); From Xilinx “Synthesis and Simulation
end syn; Design Guide”
Block RAM inferred
library ieee;
use ieee.std_logic_1164.all; addr
use ieee.std_logic_unsigned.all;
di
entity rams_01 is
port ( clk : in std_logic; do
we : in std_logic; 64x16
en : in std_logic; we BRAM
addr : in std_logic_vector(5 downto 0);
di : in std_logic_vector(15 downto 0); en
do : out std_logic_vector(15 downto 0));
end rams_01; clk
architecture syn of rams_01 is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM: ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
RAM(conv_integer(addr)) <= di;
end if;
do <= RAM(conv_integer(addr)) ; -- read-first operation
end if;
end if;
end process; From Xilinx “Synthesis and Simulation
end syn;
Design Guide”

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