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Memory Interfacing PDF

The document discusses interfacing memory chips with the 8085 microprocessor. It describes the requirements of read/write memory and EPROM chips, including address lines, data lines, and control signals. It then covers the basic concepts of memory interfacing, including address decoding, timing diagrams, and designing interface circuits using decoders. Specific examples are provided on interfacing a 2732 EPROM chip and a 6116 read/write memory chip with the 8085 microprocessor.

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Bhola Kumar
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Download as PDF, TXT or read online on Scribd
232 views

Memory Interfacing PDF

The document discusses interfacing memory chips with the 8085 microprocessor. It describes the requirements of read/write memory and EPROM chips, including address lines, data lines, and control signals. It then covers the basic concepts of memory interfacing, including address decoding, timing diagrams, and designing interface circuits using decoders. Specific examples are provided on interfacing a 2732 EPROM chip and a 6116 read/write memory chip with the 8085 microprocessor.

Uploaded by

Bhola Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Memory

Interfacing
Slides-3
Dr. Ritika
Department of Computer
Application
8085 interfacing with memory Chips
Microprocessor need to access memory quite frequently to read
instructions and data stored in memory; the interface circuit enables that
access.

The interface process involves designing a circuit that will match the memory
requirements with the microprocessor signal.[Memory has certain signal
requirements to read from and write into memory. Similarly
Microprocessor initiates the set of signals when it wants to read from
and write into memory].

*
Memory Structure and its Requirements

R/W Memory: Group of Registers.

Figure Shows:

2048 registers
●

Register store 8-bits


●

8 input, 8-output lines


●

●11 address lines(AD10-AD0), 1 chip


select, 2 control lines to enable input
and output buffer.

●Internal decoder to decode address


lines

Fig: R/W Static Memory

*
Memory Structure and its Requirements

EPROM : Chip must be programmed


before it can be used as ROM.

Figure Shows:

4096 (4K) registers.


●

Register store 8-bits


●

8 input lines
●

●Internal decoder to decode address


lines.

●12 address lines(A11-A0), 1 chip select,


1 Read control Signal lines to enable
output buffer. Fig: EPROM

Quartz window(covered with opaque*


●
Basic concepts of Memory Interfacing
● 8085 places 16-bit address on address bus,
and with this address only one register should
be selected (only 11 low order address lines
are required). Internal decoder of chip will
identify and select the register for EPROM.

●Remaining 8085 address lines (A15-A11)


should be decoded to generate chip select.

●8085 provides two signal-IO/M’ and RD’– to


indicate that is memory read operation
MEMR’. MEMR’ control signal that can be
used to enable output buffer by connecting to
memory signal RD’. (Similarly signal-IO/M’
and WR’– indicates memory write operation
MEMW’).

●Memory places data byte from address


register during T2 and that is read by the
microprocessor before the end of T3.

Fig: Timing Diagram of Memory Write Cycle


*
Basic concepts of Memory Interfacing

Primary Function of memory


interfacing is that the microprocessor
should be able to read from and write
into a given register of a memory chip:

●Select the Chip


●Identify the register
●Enable the appropriate buffer.

Timing Diagram of 8085 Memory


Read/Write Machine Cycle allows to
understand microprocessor
interfacing concepts.

Fig: Timing Diagram of Memory Read


Cycle
*
Basic concepts of Memory Interfacing

*
Address Decoding and Memory Addresses
●EPROM Address Lines A11-A0 are connected to memory
chip.

●Remaining Address lines A15-A12 of 8085


microprocessor must be decoded.

●Two methods to decoding these lines:

●by NAND gate: Output of NAND gate is active and select


the chip only when all address lines A15-A12 are at logic1

●by using 3x8 Decoder: If enable line is active eight


different logic combination can be identified by output line
O7.E1 and E2 are enable by grounding and A15 must be
at logic 1.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0


0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H

Chip Select 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH

*
Interfacing Circuit

Fig :

*
Interfacing Circuit
Fig: Interfacing Circuit using 3x8 Decoder to interface 2732 EPROM.

● The 8085 address lines A11-A0 are connected to the pins A11-A0 of the memory chip.

● Decoder decode A15-A12 and output O0 is connected to CE’ which is asserted only
when A15-A12 is 0000 (A15 low enables decoder and input 000 asserts the output O0).

● One control signal MEMR’ is connected to OE’ to enable output buffer.


*
Interfacing Circuit
● Examine how 8085 places the Fig: Address decoding and reading from
address 0FFFH on address memory.
bus.

● The address 0000H goes to


decoder.

● Output line O0 of the decoder


selects the chip.

● Remaining address lines


FFFH goes on address lines
of the chip and the internal
decoder decodes the address
and selects the register FFFH.

● When RD’ is asserted the


output buffer is enabled and
the contents of register
0FFFH are places on the data
bus for the processor to read.

*
Interfacing 6116 Memory Chip with 2K
Registers
● 11 Address lines A10-A0 to decode 2048K registers.
● Address lines A15-A11 are connected to decoder(which is enabled by IO/M’ signal in
addition to the address lines A15 and A14).
● RD’ and WR’ signals are directly connected to memory chip.
● MEMR’ and MEMW’ need not to be generated separately (this technique save two gates).
● Memory Address Ranges from 8800H to 8FFFH.
● A13-A11(001) activate output O1 of decoder which is connected to CE’ of memory chip
and it is asserted only when IO/M’ is low.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0


1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 8800H
Chip Select 1 1 1 1 1 1 1 1 1 1 1 1 8FFFH

Fig: Interfacing R/W* Memory


8155 Memory Segment
Fig: 8155 Memory Section Block Diagram Fig: 8155 Memory Section Internal Structure

● 8 Address lines.
● One CE’.
● Includes 256x8 memory locations
● 5 Control and status signals (IO/M’, ALE, RD’,
● Internal latch for de-multiplexing
WR’ and RESET). ● CE’, MEMR and MEMW’ control
signals

*
Interfacing the 8155 Memory Segment
●8205, a 3x8 Decoder, decodes the
address lines A15-A11, O4 enables the
memory chip. Control and status signals from
8085 are connected to the respective signals
of memory chip.

●A7-A0 address any one of the 256


registers.

●A14-A15 are active low and third line is


permanently enable by tying it with +5V.

●A10-A8 are not connected(don’t care


lines).

●O4 is low for following address.

A15 A14 A13 A12 A11 A10 A9 A8


0 0 1 0 0 0 0 0 20H
Fig: Interfacing 8155 Memory schematic
●Memory Address range is from 2000H to from SDK-85 System
20FFH (When don’t care lines are at logic 0,
by convention it is called primary address
remaining are fold back memory or mirror *

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