M27C160

16 Mbit (2Mb x 8 or 1Mb x 16) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION
■ ACCESS TIME: 70ns
■ BYTE-WIDE or WORD-WIDE
CONFIGURABLE 42 42

■ 16 Mbit MASK ROM REPLACEMENT

1 1
■ LOW POWER CONSUMPTION
FDIP42W (F) PDIP42 (B)
– Active Current 70mA at 8MHz
– Standby Current 100µA
■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V
■ PROGRAMMING TIME: 100µs/word 44

■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h 1

– Device Code: B1h PLCC44 (K) SO44 (M)

DESCRIPTION
The M27C160 is a 16 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one Figure 1. Logic Diagram
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage and is organised as either 2 Mbit words of
8 bit or 1 Mbit words of 16 bit. The pin-out is com-
patible with a 16 Mbit Mask ROM. VCC
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat- 20
tern. A new pattern can then be written rapidly to Q15A–1
the device by following the programming proce- A0-A19
15
dure.
For applications where the content is programmed Q0-Q14
only one time and erasure is not required, the E M27C160
M27C160 is offered in PDIP42, PLCC44 and
SO44 packages. G

BYTEVPP

VSS
AI00739B

September 2000 1/17

M27C160

Figure 2A. DIP Connections Figure 2B. PLCC Connections

A18 1 42 A19
A17 2 41 A8
A7 3 40 A9

VSS
A17
A18

A19

A10
A11
A6 4 39 A10

A5
A6
A7

A8
A9
A5 5 38 A11
1 44
A4 6 37 A12 A4 A12
A3 7 36 A13 A3 A13
A2 8 35 A14 A2 A14
A1 9 34 A15 A1 A15
A0 10 33 A16 A0 A16
M27C160 E 12 M27C160 34 BYTEVPP
E 11 32 BYTEVPP
VSS VSS
VSS 12 31 VSS
G Q15A–1
G 13 30 Q15A-1
Q0 Q7
Q0 14 29 Q7 Q8 Q14
Q8 15 28 Q14 Q1 Q6
Q1 16 27 Q6 23
Q9 17 26 Q13

Q10

Q11
NC
VCC

Q12

Q13
Q9
Q2

Q3

Q4

Q5
Q2 18 25 Q5
AI03012
Q10 19 24 Q12
Q3 20 23 Q4
Q11 21 22 VCC
AI00740

Figure 2C. SO Connections Table 1. Signal Names

A0-A19 Address Inputs
NC 1 44 NC
A18 2 43 A19 Q0-Q7 Data Outputs
A17 3 42 A8 Q8-Q14 Data Outputs
A7 4 41 A9
Q15A–1 Data Output / Address Input
A6 5 40 A10
A5 6 39 A11 E Chip Enable
A4 7 38 A12 G Output Enable
A3 8 37 A13
BYTEVPP Byte Mode / Program Supply
A2 9 36 A14
A1 10 35 A15 VCC Supply Voltage
A0 11 34 A16 VSS Ground
M27C160
E 12 33 BYTEVPP
VSS 13 32 VSS NC Not Connected Internally
G 14 31 Q15A-1
Q0 15 30 Q7
Q8 16 29 Q14
Q1 17 28 Q6
Q9 18 27 Q13
Q2 19 26 Q5
Q10 20 25 Q12
Q3 21 24 Q4
Q11 22 23 VCC
AI01264

2/17
 M27C160

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes

Mode E G BYTEVPP A9 Q15A–1 Q8-Q14 Q7-Q0

Read Word-wide VIL VIL V IH X Data Out Data Out Data Out

Read Byte-wide Upper VIL VIL VIL X VIH Hi-Z Data Out

Read Byte-wide Lower VIL VIL VIL X VIL Hi-Z Data Out

Output Disable VIL V IH X X Hi-Z Hi-Z Hi-Z

Program VIL Pulse V IH V PP X Data In Data In Data In

Verify VIH VIL V PP X Data Out Data Out Data Out

Program Inhibit VIH V IH V PP X Hi-Z Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z Hi-Z

Electronic Signature VIL VIL V IH V ID Code Codes Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h

Device Code VIH 1 0 1 1 0 0 0 1 B1h

Note: Outputs Q15-Q8 are set to ’0’.

3/17
M27C160

Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit

1.3V
High Speed

3V 1N914

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit
Input Capacitance (except BYTEVPP) VIN = 0V 10 pF
C IN
Input Capacitance (BYTEVPP) VIN = 0V 120 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION lower 8 bits of the 16 bit data are selected and with
The operating modes of the M27C160 are listed in A–1 at VIH the upper 8 bits of the 16 bit data are
the Operating Modes Table. A single power supply selected.
is required in the read mode. All inputs are TTL The M27C160 has two control functions, both of
compatible except for VPP and 12V on A9 for the which must be logically active in order to obtain
Electronic Signature. data at the outputs. In addition the Word-wide or
Read Mode Byte- wide organisation must be selected.
The M27C160 has two organisations, Word-wide Chip Enable (E) is the power control and should be
and Byte-wide. The organisation is selected by the used for device selection. Output Enable (G) is the
signal level on the BYTEVPP pin. When BYTEVPP output control and should be used to gate data to
is at VIH the Word-wide organisation is selected the output pins independent of device selection.
and the Q15A–1 pin is used for Q15 Data Output. Assuming that the addresses are stable, the ad-
When the BYTEV PP pin is at V IL the Byte-wide or- dress access time (tAVQV) is equal to the delay
ganisation is selected and the Q15A–1 pin is used from E to output (tELQV). Data is available at the
for the Address Input A–1. When the memory is output after a delay of tGLQV from the falling edge
logically regarded as 16 bit wide, but read in the of G, assuming that E has been low and the ad-
Byte-wide organisation, then with A–1 at VIL the dresses have been stable for at least tAVQV-tGLQV.

4/17
 M27C160

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ V CC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL, G = VIL,
70 mA
IOUT = 0mA, f = 8MHz
ICC Supply Current
E = VIL, G = VIL,
50 mA
IOUT = 0mA, f = 5MHz

ICC1 Supply Current (Standby) TTL E = VIH 1 mA

ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA 2.4 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.

Standby Mode System Considerations

The M27C160 has a standby mode which reduces The power switching characteristics of Advanced
the active current from 50mA to 100µA. The CMOS EPROMs require careful decoupling of the
M27C160 is placed in the standby mode by apply- supplies to the devices. The supply current ICC
ing a CMOS high signal to the E input. When in the has three segments of importance to the system
standby mode, the outputs are in a high imped- designer: the standby current, the active current
ance state, independent of the G input. and the transient peaks that are produced by the
Two Line Output Control falling and rising edges of E.
Because EPROMs are usually used in larger The magnitude of the transient current peaks is
memory arrays, this product features a 2 line con- dependent on the capacitive and inductive loading
trol function which accommodates the use of mul- of the device outputs. The associated transient
tiple memory connection. The two line control voltage peaks can be suppressed by complying
function allows: with the two line output control and by properly se-
lected decoupling capacitors. It is recommended
a. the lowest possible memory power dissipation,
that a 0.1µF ceramic capacitor is used on every
b. complete assurance that output bus contention device between VCC and VSS. This should be a
will not occur. high frequency type of low inherent inductance
For the most efficient use of these two control and should be placed as close as possible to the
lines, E should be decoded and used as the prima- device. In addition, a 4.7µF electrolytic capacitor
ry device selecting function, while G should be should be used between VCC and VSS for every
made a common connection to all devices in the eight devices.
array and connected to the READ line from the This capacitor should be mounted near the power
system control bus. This ensures that all deselect- supply connection point. The purpose of this ca-
ed memory devices are in their low power standby pacitor is to overcome the voltage drop caused by
mode and that the output pins are only active the inductive effects of PCB traces.
when data is required from a particular memory
device.

5/17
M27C160

Table 8. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C160

Symbol Alt Parameter Test Condition -70 (3) -90 -100 -120/-150 Unit

Min Max Min Max Min Max Min Max

Address Valid to
tAVQV tACC E = VIL, G = VIL 70 90 100 120 ns
Output Valid
BYTE High to
tBHQV tST E = VIL, G = VIL 70 90 100 120 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 70 90 100 120 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 35 45 50 60 ns
to Output Valid
BYTE Low to Output
tBLQZ (2) tSTD E = VIL, G = VIL 30 30 40 50 ns
Hi-Z
Chip Enable High to
tEHQZ (2) tDF
Output Hi-Z
G = VIL 0 25 0 30 0 40 0 50 ns

Output Enable High

tGHQZ (2) tDF E = VIL 0 25 0 30 0 40 0 50 ns
to OutputHi-Z
Address Transition
tAXQX tOH E = VIL, G = VIL 5 5 5 5 ns
to Output Transition

BYTE Low to
tBLQX tOH E = VIL, G = VIL 5 5 5 5 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.

Figure 5. Word-Wide Read Mode AC Waveforms

A0-A19 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q15

AI00741B

Note: BYTEV PP = VIH.

6/17
 M27C160

Figure 6. Byte-Wide Read Mode AC Waveforms

A–1,A0-A19 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q7

AI00742B

Note: BYTEV PP = VIL.

Figure 7. BYTE Transition AC Waveforms

A0-A19 VALID

A–1 VALID

tAVQV tAXQX

BYTEVPP

tBHQV

Q0-Q7 DATA OUT

tBLQX
Hi-Z
Q8-Q15 DATA OUT

tBLQZ

AI00743C

Note: Chip Enable (E) and Output Enable (G) = VIL.

7/17
M27C160

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V)
Symbol Parameter Test Conditio n Min Max Unit
ILI Input Leakage Current 0 ≤ V IN ≤ VCC ±1 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

V IL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.4 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –2.5mA 3.5 V

VID A9 Voltage 11.5 12.5 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.

Table 10. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Valid to Chip Enable Low 2 µs

tQVEL tDS Input Valid to Chip Enable Low 2 µs

tVPHAV tVPS VPP High to Address Valid 2 µs

tVCHAV tVCS VCC High to Address Valid 2 µs

tELEH tPW Chip Enable Program Pulse Width 45 55 µs

tEHQX tDH Chip Enable High to Input Transition 2 µs

tQXGL tOES Input Transition to Output Enable Low 2 µs

tGLQV tOE Output Enable Low to Output Valid 120 ns

tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns

Output Enable High to Address

tGHAX tAH 0 ns
Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Programming light (UV EPROM). The M27C160 is in the pro-

When delivered (and after each erasure for UV gramming mode when V PP input is at 12.5V, G is
EPROM), all bits of the M27C160 are in the ’1’ at VIH and E is pulsed to VIL. The data to be pro-
state. Data is introduced by selectively program- grammed is applied to 16 bits in parallel to the data
ming ’0’s into the desired bit locations. Although output pins. The levels required for the address
only ’0’s will be programmed, both ’1’s and ’0’s can and data inputs are TTL. VCC is specified to be
be present in the data word. The only way to 6.25V ± 0.25V.
change a ’0’ to a ’1’ is by die exposure to ultraviolet

8/17
 M27C160

Figure 8. Programming and Verify Modes AC Waveforms

A0-A19 VALID

tAVEL

Q0-Q15 DATA IN DATA OUT

tQVEL tEHQX

BYTEVPP

tVPHAV tGLQV tGHQZ

VCC

tVCHAV tGHAX

tELEH tQXGL

PROGRAM VERIFY
AI00744

Figure 9. Programming Flowchart PRESTO III Programming Algorithm

The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 52.5 seconds. Pro-
VCC = 6.25V, VPP = 12.5V
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9). During
n=0 programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran-
tee that each cell is programed with enough mar-
E = 50µs Pulse gin. No overprogram pulse is applied since the
NO verify in MARGIN MODE provides the necessary
margin to each programmed cell.
++n NO
= 25 VERIFY ++ Addr Program Inhibit
Programming of multiple M27C160s in parallel
YES YES with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
Last NO M27C160 may be common. A TTL low level pulse
FAIL Addr applied to a M27C160’s E input and VPP at 12.5V,
will program that M27C160. A high level E input in-
YES
hibits the other M27C160s from being pro-
CHECK ALL WORDS grammed.
BYTEVPP =VIH Program Verify
1st: VCC = 6V A verify (read) should be performed on the pro-
2nd: VCC = 4.2V
grammed bits to determine that they were correct-
AI01044B ly programmed. The verify is accomplished with E
at VIH and G at VIL, VPP at 12.5V and VCC at
6.25V.

9/17
M27C160

Electronic Signature ERASURE OPERATION (applies to UV EPROM)

The Electronic Signature (ES) mode allows the The erasure characteristics of the M27C160 is
reading out of a binary code from an EPROM that such that erasure begins when the cells are ex-
will identify its manufacturer and type. This mode posed to light with wavelengths shorter than ap-
is intended for use by programming equipment to proximately 4000 Å. It should be noted that
automatically match the device to be programmed sunlight and some type of fluorescent lamps have
with its corresponding programming algorithm. wavelengths in the 3000-4000 Å range. Research
The ES mode is functional in the 25°C ± 5°C am- shows that constant exposure to room level fluo-
bient temperature range that is required when pro- rescent lighting could erase a typical M27C160 in
gramming the M27C160. To activate the ES about 3 years, while it would take approximately 1
mode, the programming equipment must force week to cause erasure when exposed to direct
11.5V to 12.5V on address line A9 of the sunlight. If the M27C160 is to be exposed to these
M27C160, with VPP = VCC = 5V. Two identifier types of lighting conditions for extended periods of
bytes may then be sequenced from the device out- time, it is suggested that opaque labels be put over
puts by toggling address line A0 from VIL to VIH. All the M27C160 window to prevent unintentional era-
other address lines must be held at V IL during sure. The recommended erasure procedure for
Electronic Signature mode. Byte 0 (A0 = VIL) rep- M27C160 is exposure to short wave ultraviolet
resents the manufacturer code and byte 1 light which has a wavelength of 2537 Å. The inte-
(A0 = VIH) the device identifier code. For the grated dose (i.e. UV intensity x exposure time) for
STMicroelectronics M27C160, these two identifier erasure should be a minimum of 30 W-sec/cm2.
bytes are given in Table 4 and can be read-out on The erasure time with this dosage is approximate-
outputs Q7 to Q0. ly 30 to 40 minutes using an ultraviolet lamp with
12000 µW/cm2 power rating. The M27C160
should be placed within 2.5cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.

10/17
 M27C160

Table 11. Ordering Information Scheme

Example: M27C160 -70 X M 1 TR

Device Type
M27

Supply Voltage
C = 5V

Device Function
160 = 16 Mbit (2mb x 8 or 1Mb x 16)

Speed
-70 (1,2) = 70 ns
-90 = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns

V CC Tolerance
blank = ± 10%
X = ± 5%

Package
F = FDIP42W
B = PDIP42
K = PLCC44(3)
M = SO44

Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C

Optio ns
TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

2. This speed is guaranteed at VCC = 5V ± 5%.
3. The M27C160 product PLCC44 package version is offered in the Temperature Range 0 to 70 °C only.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.

11/17
M27C160

Table 12. Revision History

Date Revision Details
January 1999 First Issue

09/20/00 AN620 Reference removed

12/17
 M27C160

Table 13. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 54.41 54.86 2.142 2.160
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 14.50 14.90 0.571 0.587
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
K 9.40 – – 0.370 – –
K1 11.43 – – 0.450 – –
α 4° 11° 4° 11°
N 42 42

Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline

A2 A3 A

A1 L α
B1 B e1 C
eA
D2
eB
D
S
N

K E1 E

1 K1
FDIPW-b

Drawing is not to scale.

13/17
M27C160

Table 14. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.25 – 0.010 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.53 0.015 0.021
B1 1.27 1.65 0.050 0.065
C 0.20 0.36 0.008 0.014
D 52.20 52.71 2.055 2.075
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 0.86 1.37 0.034 0.054
α 0° 10° 0° 10°
N 42 42

Figure 11. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Outline

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale.

14/17
 M27C160

Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max

A 4.20 4.70 0.165 0.185

A1 2.29 3.04 0.090 0.120
A2 – 0.51 – 0.020
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 17.40 17.65 0.685 0.695
D1 16.51 16.66 0.650 0.656

D2 14.99 16.00 0.590 0.630

E 17.40 17.65 0.685 0.695
E1 16.51 16.66 0.650 0.656
E2 14.99 16.00 0.590 0.630
e 1.27 – – 0.050 – –
F 0.00 0.25 0.000 0.010
R 0.89 – – 0.035 – –
N 44 44
CP 0.10 0.004

Figure 12. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline

D A1
D1 A2

1 N
B1

e
Ne E1 E F D2/E2
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Drawing is not to scale.

15/17
M27C160

Table 16. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010
A2 2.25 2.35 0.089 0.093
B 0.50 0.020
C 0.10 0.25 0.004 0.010
D 28.10 28.30 1.106 1.114
E 13.20 13.40 0.520 0.528

e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° – – 3° – –
N 44 44
CP 0.10 0.004

Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Drawing is not to scale.

16/17
 M27C160

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

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