16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 / SST39VF6401

SST39VF1602 / SST39VF3202 / SST39VF6402
SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories
www.DataSheet4U.com Preliminary Specifications
FEATURES:
• Organized as 1M x16: SST39VF1601/1602 • Security-ID Feature
2M x16: SST39VF3201/3202 – SST: 128 bits; User: 128 bits
4M x16: SST39VF6401/6402
• Fast Read Access Time:
• Single Voltage Read and Write Operations
– 70 ns
– 2.7-3.6V – 90 ns
• Superior Reliability • Latched Address and Data
– Endurance: 100,000 Cycles (Typical) • Fast Erase and Word-Program:
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms (typical)
• Low Power Consumption (typical values at 5 MHz) – Block-Erase Time: 18 ms (typical)
– Active Current: 9 mA (typical) – Chip-Erase Time: 40 ms (typical)
– Standby Current: 3 µA (typical) – Word-Program Time: 7 µs (typical)
– Auto Low Power Mode: 3 µA (typical) • Automatic Write Timing
• Hardware Block-Protection/WP# Input Pin – Internal VPP Generation
– Top Block-Protection (top 32 KWord) • End-of-Write Detection
for SST39VF1602/3202/6402
– Toggle Bits
– Bottom Block-Protection (bottom 32 KWord)
– Data# Polling
for SST39VF1601/3201/6401
• Sector-Erase Capability • CMOS I/O Compatibility
• JEDEC Standard
– Uniform 2 KWord sectors
– Flash EEPROM Pinouts and command sets
• Block-Erase Capability
– Uniform 32 KWord blocks • Packages Available
– 48-lead TSOP (12mm x 20mm)
• Chip-Erase Capability
– 48-ball TFBGA (6mm x 8mm) for 16M and 32M
• Erase-Suspend/Erase-Resume Capabilities – 48-ball TFBGA (8mm x 10mm) for 64M
• Hardware Reset Pin (RST#)

PRODUCT DESCRIPTION
The SST39VF160x/320x/640x devices are 1M x16, 2M The SST39VF160x/320x/640x devices are suited for appli-
x16, and 4M x16 respectively, CMOS Multi-Purpose cations that require convenient and economical updating of
Flash Plus (MPF+) manufactured with SST’s proprietary, program, configuration, or data memory. For all system
high performance CMOS SuperFlash technology. The applications, they significantly improve performance and
split-gate cell design and thick-oxide tunneling injector reliability, while lowering power consumption. They inher-
attain better reliability and manufacturability compared ently use less energy during Erase and Program than alter-
with alternate approaches. The SST39VF160x/320x/640x native flash technologies. The total energy consumed is a
write (Program or Erase) with a 2.7-3.6V power supply. function of the applied voltage, current, and time of applica-
These devices conform to JEDEC standard pinouts for tion. Since for any given voltage range, the SuperFlash
x16 memories. technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Featuring high performance Word-Program, the
Program operation is less than alternative flash technolo-
SST39VF160x/320x/640x devices provide a typical Word-
gies. These devices also improve flexibility while lowering
Program time of 7 µsec. These devices use Toggle Bit or
the cost for program, data, and configuration storage appli-
Data# Polling to indicate the completion of Program opera-
cations.
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes. The SuperFlash technology provides fixed Erase and Pro-
Designed, manufactured, and tested for a wide spectrum of gram times, independent of the number of Erase/Program
applications, these devices are offered with a guaranteed cycles that have occurred. Therefore the system software
typical endurance of 100,000 cycles. Data retention is rated or hardware does not have to be modified or de-rated as is
at greater than 100 years. necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.

©2003 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
S71223-03-000 11/03 MPF is a trademark of Silicon Storage Technology, Inc.
1 These specifications are subject to change without notice.
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

To meet high density, surface mount requirements, the first. The Program operation, once initiated, will be com-
SST39VF160x/320x/640x are offered in 48-lead TSOP pleted within 10 µs. See Figures 4 and 5 for WE# and CE#
and 48-ball TFBGA packages. See Figures 1 and 2 for controlled Program operation timing diagrams and Figure
pin assignments. 19 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the
Device Operation internal Program operation, the host is free to perform addi-
tional tasks. Any commands issued during the internal Pro-
Commands are used to initiate the memory operation func- gram operation are ignored. During the command
tions of the device. Commands are written to the device sequence, WP# should be statically held high or low.
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE# Sector/Block-Erase Operation
or CE#, whichever occurs last. The data bus is latched on The Sector- (or Block-) Erase operation allows the system
the rising edge of WE# or CE#, whichever occurs first. to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF160x/320x/640x offer both Sec-
The SST39VF160x/320x/640x also have the Auto Low
tor-Erase and Block-Erase mode. The sector architecture
Power mode which puts the device in a near standby
is based on uniform sector size of 2 KWord. The Block-
mode after data has been accessed with a valid Read
Erase mode is based on uniform block size of 32 KWord.
operation. This reduces the IDD active read current from
The Sector-Erase operation is initiated by executing a six-
typically 9 mA to typically 3 µA. The Auto Low Power mode
byte command sequence with Sector-Erase command
reduces the typical IDD active read current to the range of 2
(30H) and sector address (SA) in the last bus cycle. The
mA/MHz of Read cycle time. The device exits the Auto Low
Block-Erase operation is initiated by executing a six-byte
Power mode with any address transition or control signal
command sequence with Block-Erase command (50H)
transition used to initiate another Read cycle, with no
and block address (BA) in the last bus cycle. The sector or
access time penalty. Note that the device does not enter
block address is latched on the falling edge of the sixth
Auto-Low Power mode after power-up with CE# held
WE# pulse, while the command (30H or 50H) is latched on
steadily low, until the first address transition or CE# is
the rising edge of the sixth WE# pulse. The internal Erase
driven high.
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Read Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
The Read operation of the SST39VF160x/320x/640x is ing waveforms and Figure 23 for the flowchart. Any com-
controlled by CE# and OE#, both have to be low for the mands issued during the Sector- or Block-Erase operation
system to obtain data from the outputs. CE# is used for are ignored. When WP# is low, any attempt to Sector-
device selection. When CE# is high, the chip is dese- (Block-) Erase the protected block will be ignored. During
lected and only standby power is consumed. OE# is the the command sequence, WP# should be statically held
output control and is used to gate data from the output high or low.
pins. The data bus is in high impedance state when
either CE# or OE# is high. Refer to the Read cycle timing Erase-Suspend/Erase-Resume Commands
diagram for further details (Figure 3).
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
Word-Program Operation read from any memory location, or program data into any
The SST39VF160x/320x/640x are programmed on a sector/block that is not suspended for an Erase operation.
word-by-word basis. Before programming, the sector The operation is executed by issuing one byte command
where the word exists must be fully erased. The Program sequence with Erase-Suspend command (B0H). The
operation is accomplished in three steps. The first step is device automatically enters read mode typically within 20
the three-byte load sequence for Software Data Protection. µs after the Erase-Suspend command had been issued.
The second step is to load word address and word data. Valid data can be read from any sector or block that is not
During the Word-Program operation, the addresses are suspended from an Erase operation. Reading at address
latched on the falling edge of either CE# or WE#, which- location within erase-suspended sectors/blocks will output
ever occurs last. The data is latched on the rising edge of DQ2 toggling and DQ6 at “1”. While in Erase-Suspend
either CE# or WE#, whichever occurs first. The third step is mode, a Word-Program operation is allowed except for the
the internal Program operation which is initiated after the sector or block selected for Erase-Suspend.
rising edge of the fourth WE# or CE#, whichever occurs

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

2
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications
To resume Sector-Erase or Block-Erase operation which has ing the completion of an internal Write operation, the
been suspended the system must issue Erase Resume remaining data outputs may still be invalid: valid data on the
command. The operation is executed by issuing one byte entire data bus will appear in subsequent successive Read
command sequence with Erase Resume command (30H) cycles after an interval of 1 µs. During internal Erase oper-
at any address in the last Byte sequence. ation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
Chip-Erase Operation ‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
The SST39VF160x/320x/640x provide a Chip-Erase oper- Block- or Chip-Erase, the Data# Polling is valid after the
ation, which allows the user to erase the entire memory rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
array to the “1” state. This is useful when the entire device Data# Polling timing diagram and Figure 20 for a flowchart.
must be quickly erased.
The Chip-Erase operation is initiated by executing a six- Toggle Bits (DQ6 and DQ2)
byte command sequence with Chip-Erase command
During the internal Program or Erase operation, any con-
(10H) at address 5555H in the last byte sequence. The
secutive attempts to read DQ6 will produce alternating “1”s
Erase operation begins with the rising edge of the sixth
and “0”s, i.e., toggling between 1 and 0. When the internal
WE# or CE#, whichever occurs first. During the Erase
Program or Erase operation is completed, the DQ6 bit will
operation, the only valid read is Toggle Bit or Data# Polling.
stop toggling. The device is then ready for the next opera-
See Table 6 for the command sequence, Figure 9 for tim-
tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)
ing diagram, and Figure 23 for the flowchart. Any com-
is valid after the rising edge of sixth WE# (or CE#) pulse.
mands issued during the Chip-Erase operation are
DQ6 will be set to “1” if a Read operation is attempted on an
ignored. When WP# is low, any attempt to Chip-Erase will
Erase-Suspended Sector/Block. If Program operation is ini-
be ignored. During the command sequence, WP# should
tiated in a sector/block not selected in Erase-Suspend
be statically held high or low.
mode, DQ6 will toggle.

Write Operation Status Detection An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
The SST39VF160x/320x/640x provide two software sector is being actively erased or erase-suspended. Table 1
means to detect the completion of a Write (Program or shows detailed status bits information. The Toggle Bit
Erase) cycle, in order to optimize the system write cycle (DQ2) is valid after the rising edge of the last WE# (or CE#)
time. The software detection includes two status bits: Data# pulse of Write operation. See Figure 7 for Toggle Bit timing
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write diagram and Figure 20 for a flowchart.
detection mode is enabled after the rising edge of WE#,
which initiates the internal Program or Erase operation.
TABLE 1: WRITE OPERATION STATUS
The actual completion of the nonvolatile write is asyn- Status DQ7 DQ6 DQ2
chronous with the system; therefore, either a Data# Poll-
Normal Standard DQ7# Toggle No Toggle
ing or Toggle Bit read may be simultaneous with the Operation Program
completion of the write cycle. If this occurs, the system Standard 0 Toggle Toggle
may possibly get an erroneous result, i.e., valid data may Erase
appear to conflict with either DQ7 or DQ6. In order to pre- Erase- Read from 1 1 Toggle
vent spurious rejection, if an erroneous result occurs, the Suspend Erase-Suspended
Mode Sector/Block
software routine should include a loop to read the
accessed location an additional two (2) times. If both Read from Data Data Data
Non- Erase-Suspended
reads are valid, then the device has completed the Write Sector/Block
cycle, otherwise the rejection is valid. Program DQ7# Toggle N/A
T1.0 1223
Note: DQ7 and DQ2 require a valid address when reading
Data# Polling (DQ7) status information.
When the SST39VF160x/320x/640x are in the internal
Program operation, any attempt to read DQ7 will produce
the complement of the true data. Once the Program oper-
ation is completed, DQ7 will produce true data. Note that
even though DQ7 may have valid data immediately follow-

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

3
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

Data Protection Hardware Reset (RST#)

The SST39VF160x/320x/640x provide both hardware and The RST# pin provides a hardware method of resetting the
software features to protect nonvolatile data from inadvertent device to read array data. When the RST# pin is held low
writes. for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
Hardware Data Protection operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 take place (see Figure 15).
ns will not initiate a write cycle.
The Erase or Program operation that has been interrupted
VDD Power Up/Down Detection: The Write operation is needs to be reinitiated after the device resumes normal
inhibited when VDD is less than 1.5V. operation mode to ensure data integrity.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert- Software Data Protection (SDP)
ent writes during power-up or power-down.
The SST39VF160x/320x/640x provide the JEDEC
approved Software Data Protection scheme for all data
Hardware Block Protection alteration operations, i.e., Program and Erase. Any Pro-
The SST39VF1602/3202/6402 support top hardware block gram operation requires the inclusion of the three-byte
protection, which protects the top 32 KWord block of the sequence. The three-byte load sequence is used to initiate
device. The SST39VF1601/3201/6401 support bottom the Program operation, providing optimal protection from
hardware block protection, which protects the bottom 32 inadvertent Write operations, e.g., during the system
KWord block of the device. The Boot Block address ranges power-up or power-down. Any Erase operation requires the
are described in Table 2. Program and Erase operations inclusion of six-byte sequence. These devices are shipped
are prevented on the 32 KWord when WP# is low. If WP# is with the Software Data Protection permanently enabled.
left floating, it is internally held high via a pull-up resistor, See Table 6 for the specific software command codes. Dur-
and the Boot Block is unprotected, enabling Program and ing SDP command sequence, invalid commands will abort
Erase operations on that block. the device to read mode within TRC. The contents of DQ15-
DQ8 can be VIL or VIH, but no other value, during any SDP
TABLE 2: BOOT BLOCK ADDRESS RANGES command sequence.

Product Address Range

Common Flash Memory Interface (CFI)
Bottom Boot Block
The SST39VF160x/320x/640x also contain the CFI infor-
SST39VF1601/3201/6401 000000H-007FFFH
mation to describe the characteristics of the device. In
Top Boot Block order to enter the CFI Query mode, the system must write
SST39VF1602 0F8000H-0FFFFFH three-byte sequence, same as product ID entry command
SST39VF3202 1F8000H-1FFFFFH with 98H (CFI Query command) to address 5555H in the
SST39VF6402 3F8000H-3FFFFFH last byte sequence. Once the device enters the CFI Query
T2.0 1223 mode, the system can read CFI data at the addresses
given in Tables 7 through 10. The system must write the
CFI Exit command to return to Read mode from the CFI
Query mode.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

4
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

Product Identification Security ID

The Product Identification mode identifies the devices as The SST39VF160x/320x/640x devices offer a 256-bit
the SST39VF1601, SST39VF1602, SST39VF3201, Security ID space. The Secure ID space is divided into two
SST39VF3202, SST39VF6401, SST39VF6402, and 128-bit segments - one factory programmed segment and
manufacturer as SST. This mode may be accessed soft- one user programmed segment. The first segment is pro-
ware operations. Users may use the Software Product grammed and locked at SST with a random 128-bit num-
Identification operation to identify the part (i.e., using the ber. The user segment is left un-programmed for the
device ID) when using multiple manufacturers in the same customer to program as desired.
socket. For details, see Table 6 for software operation,
To program the user segment of the Security ID, the user
Figure 11 for the Software ID Entry and Read timing dia-
must use the Security ID Word-Program command. To
gram and Figure 21 for the Software ID Entry command
detect end-of-write for the SEC ID, read the toggle bits. Do
sequence flowchart.
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
TABLE 3: PRODUCT IDENTIFICATION This disables any future corruption of this space. Note that
Address Data regardless of whether or not the Sec ID is locked, neither
Manufacturer’s ID 0000H BFH Sec ID segment can be erased.
Device ID The Secure ID space can be queried by executing a three-
SST39VF1601 0001H 234BH byte command sequence with Enter Sec ID command
SST39VF1602 0001H 234AH (88H) at address 5555H in the last byte sequence. To exit
SST39VF3201 0001H 235BH this mode, the Exit Sec ID command should be executed.
Refer to Table 6 for more details.
SST39VF3202 0001H 235AH
SST39VF6401 0001H 236BH
SST39VF6402 0001H 236AH
T3.2 1223

Product Identification Mode Exit/

CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command
codes, Figure 13 for timing waveform, and Figures 21 and
22 for flowcharts.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

5
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

FUNCTIONAL BLOCK DIAGRAM

SuperFlash
X-Decoder Memory

Memory Address
Address Buffer & Latches
Y-Decoder

CE#
OE# I/O Buffers and Data Latches
WE# Control Logic
WP#
RESET# DQ15 - DQ0
1223 B1.0

SST39VF6401/6402 SST39VF3201/3202 SST39VF1601/1602 SST39VF160x/320x/640x

A15 A15 A15 1 48 A16

A14 A14 A14 2 47 NC
A13 A13 A13 3 46 VSS
A12 A12 A12 4 45 DQ15
A11 A11 A11 5 44 DQ7
A10 A10 A10 6 43 DQ14
A9 A9 A9 7 42 DQ6
A8 A8 A8 8 41 DQ13
A19 A19 A19 9 Standard Pinout 40 DQ5
A20 A20 NC 10 39 DQ12
WE# WE# WE# 11 Top View 38 DQ4
RST# RST# RST# 12 37 VDD
A21 NC NC 13 Die Up 36 DQ11
WP# WP# WP# 14 35 DQ3
NC NC NC 15 34 DQ10
A18 A18 A18 16 33 DQ2
A17 A17 A17 17 32 DQ9
A7 A7 A7 18 31 DQ1
A6 A6 A6 19 30 DQ8
A5 A5 A5 20 29 DQ0
A4 A4 A4 21 28 OE#
A3 A3 A3 22 27 VSS
A2 A2 A2 23 26 CE#
A1 A1 A1 24 25 A0

1223 48-tsop P01.3

FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

6
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

TOP VIEW (balls facing down) TOP VIEW (balls facing down)
SST39VF1601/1602 SST39VF3201/3202
6 6
A13 A12 A14 A15 A16 NC DQ15 VSS A13 A12 A14 A15 A16 NC DQ15 VSS
5 5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4 4
WE# RST# NC A19 DQ5 DQ12 VDD DQ4 WE# RST# NC A19 DQ5 DQ12 VDD DQ4
3 3

1223 48-tfbga B3K P02a.2

1223 48-tfbga B3K P02.0
NC WP# A18 NC DQ2 DQ10 DQ11 DQ3 NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3
2 2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1 1
A3 A4 A2 A1 A0 CE# OE# VSS A3 A4 A2 A1 A0 CE# OE# VSS

A B C D E F G H A B C D E F G H

TOP VIEW (balls facing down)

SST39VF6401/6402

6
A13 A12 A14 A15 A16 NC DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# RST# A21 A19 DQ5 DQ12 VDD DQ4
3
NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3
2
1223 4-tfbga B1K P02b.2

A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

1
A3 A4 A2 A1 A0 CE# OE# VSS

A B C D E F G H

FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

7
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

TABLE 4: PIN DESCRIPTION

Symbol Pin Name Functions
AMS1-A0 Address Inputs To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.
RST# Reset To reset and return the device to Read mode.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V
VSS Ground
NC No Connection Unconnected pins.
T4.2 1223
1. AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

TABLE 5: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1 Sector or block address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
X X VIH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 6
T5.0 1223
1. X can be VIL or VIH, but no other value.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

8
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications
TABLE 6: SOFTWARE COMMAND SEQUENCE
Command 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4 30H
Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 50H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Erase-Suspend XXXXH B0H
Erase-Resume XXXXH 30H
Query Sec ID5 5555H AAH 2AAAH 55H 5555H 88H
User Security ID 5555H AAH 2AAAH 55H 5555H A5H WA6 Data
Word-Program
User Security ID 5555H AAH 2AAAH 55H 5555H 85H XXH6 0000H
Program Lock-Out
Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H
CFI Query Entry 5555H AAH 2AAAH 55H 5555H 98H
Software ID Exit9,10 5555H AAH 2AAAH 55H 5555H F0H
/CFI Exit/Sec ID Exit
Software ID Exit9,10 XXH F0H
/CFI Exit/Sec ID Exit
T6.6 1223
1. Address format A14-A0 (Hex).
Addresses A15-A19 can be VIL or VIH, but no other value, for Command sequence for SST39VF1601/1602,
Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF3201/3202,
Addresses A15- A21 can be VIL or VIH, but no other value, for Command sequence for SST39VF6401/6402.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence
3. WA = Program Word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX, for Block-Erase; uses AMS-A15 address lines
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
5. With AMS-A4 = 0; Sec ID is read with A3-A0,
SST ID is read with A3 = 0 (Address range = 000000H to 000007H),
User ID is read with A3 = 1 (Address range = 000010H to 000017H).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000010H-000017H.
7. The device does not remain in Software Product ID Mode if powered down.
8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1601 Device ID = 234BH, is read with A0 = 1,
SST39VF1602 Device ID = 234AH, is read with A0 = 1,
SST39VF3201 Device ID = 235BH, is read with A0 = 1,
SST39VF3202 Device ID = 235AH, is read with A0 = 1,
SST39VF6401 Device ID = 236BH, is read with A0 = 1,
SST39VF6402 Device ID = 236AH, is read with A0 = 1.
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID
mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and
000010H-000017H.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

9
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

TABLE 7: CFI QUERY IDENTIFICATION STRING1 FOR SST39VF160X/320X/640X

Address Data Data
10H 0051H Query Unique ASCII string “QRY”
11H 0052H
12H 0059H
13H 0001H Primary OEM command set
14H 0007H
15H 0000H Address for Primary Extended Table
16H 0000H
17H 0000H Alternate OEM command set (00H = none exists)
18H 0000H
19H 0000H Address for Alternate OEM extended Table (00H = none exits)
1AH 0000H
T7.1 1223
1. Refer to CFI publication 100 for more details.

TABLE 8: SYSTEM INTERFACE INFORMATION FOR SST39VF160X/320X/640X

Address Data Data
1BH 0027H VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH 0036H VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH 0000H VPP min. (00H = no VPP pin)
1EH 0000H VPP max. (00H = no VPP pin)
1FH 0003H Typical time out for Word-Program 2N µs (23 = 8 µs)
20H 0000H Typical time out for min. size buffer program 2N µs (00H = not supported)
21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms)
23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 µs)
24H 0000H Maximum time out for buffer program 2N times typical
25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T8.3 1223

TABLE 9: DEVICE GEOMETRY INFORMATION FOR SST39VF1601/1602

Address Data Data
27H 0015H Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0001H y = 511 + 1 = 512 sectors (01FF = 511
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y = 31 + 1 = 32 blocks (001F = 31)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.0 1223

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

10
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications
TABLE 10: DEVICE GEOMETRY INFORMATION FOR SST39VF3201/3202
Address Data Data
27H 0016H Device size = 2N Bytes (16H = 22; 222 = 4 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0003H y = 1023 + 1 = 1024 (03FFH = 1023)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 003FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y = 63 + 1 = 64 blocks (003FH = 63)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T10.2 1223

TABLE 11: DEVICE GEOMETRY INFORMATION FOR SST39VF6401/6402

Address Data Data
27H 0017H Device size = 2N Bytes (17H = 23; 223 = 8 MByte)
28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface
29H 0000H
2AH 0000H Maximum number of bytes in multi-byte write = 2N (00H = not supported)
2BH 0000H
2CH 0002H Number of Erase Sector/Block sizes supported by device
2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH 0007H y = 2047 + 1 = 2048 sectors (07FFH = 2047)
2FH 0010H
30H 0000H z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H 007FH Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H 0000H y =127 + 1 = 128 blocks (007FH = 127)
33H 0000H
34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T11.2 1223

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

11
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

12
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

TABLE 12: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V1

Limits
Symbol Parameter Min Max Units Test Conditions
IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read3 18 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 20 µA CE#=VIHC, VDD=VDD Max
IALP Auto Low Power 20 µA CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILIW Input Leakage Current 10 µA WP#=GND to VDD or RST#=GND to VDD
on WP# pin and RST#
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max
VIH Input High Voltage 0.7VDD V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T12.8 1223
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 17
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units
TPU-READ1 Power-up to Read Operation 100 µs
TPU-WRITE 1 Power-up to Program/Erase Operation 100 µs
T13.0 1223
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 14: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF
CIN 1 Input Capacitance VIN = 0V 6 pF
T14.0 1223
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 15: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method
NEND 1,2 Endurance 10,000 Cycles JEDEC Standard A117
TDR1 Data Retention 100 Years JEDEC Standard A103
ILTH 1 Latch Up 100 + IDD mA JEDEC Standard 78
T15.2 1223
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

13
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

AC CHARACTERISTICS

TABLE 16: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V

SST39VFxx01/xx02-70 SST39VFxx01/xx02-90
Symbol Parameter Min Max Min Max Units
TRC Read Cycle Time 70 90 ns
TCE Chip Enable Access Time 70 90 ns
TAA Address Access Time 70 90 ns
TOE Output Enable Access Time 35 45 ns
TCLZ1 CE# Low to Active Output 0 0 ns
TOLZ1 OE# Low to Active Output 0 0 ns
TCHZ1 CE# High to High-Z Output 20 30 ns
TOHZ1 OE# High to High-Z Output 20 30 ns
TOH1 Output Hold from Address Change 0 0 ns
TRP1 RST# Pulse Width 500 500 ns
TRHR 1 RST# High before Read 50 50 ns
TRY1,2 RST# Pin Low to Read Mode 20 20 µs
T16.3 1223
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase and Program operations.
This parameter does not apply to Chip-Erase operations.

TABLE 17: PROGRAM/ERASE CYCLE TIMING PARAMETERS

Symbol Parameter Min Max Units
TBP Word-Program Time 10 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1 WE# Pulse Width High 30 ns
TCPH1 CE# Pulse Width High 30 ns
TDS Data Setup Time 30 ns
TDH1 Data Hold Time 0 ns
TIDA1 Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TBE Block-Erase 25 ms
TSCE Chip-Erase 50 ms
T17.1 1223
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

14
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

TRC TAA

ADDRESS AMS-0

TCE
CE#

TOE
OE#

VIH TOLZ TOHZ

WE#

TCHZ
TOH
HIGH-Z TCLZ HIGH-Z
DQ15-0
DATA VALID DATA VALID

1223 F03.2
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

FIGURE 3: READ CYCLE TIMING DIAGRAM

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 5555 2AAA 5555 ADDR

TAH
TDH
TWP
WE#
TAS TWPH TDS

OE#

TCH
CE#

TCS

DQ15-0 XXAA XX55 XXA0 DATA

SW0 SW1 SW2 WORD

(ADDR/DATA) 1223 F04.3

Note: AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

15
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

INTERNAL PROGRAM OPERATION STARTS

TBP

ADDRESS AMS-0 5555 2AAA 5555 ADDR

TAH
TDH
TCP
CE#
TAS TCPH TDS

OE#

TCH
WE#

TCS

DQ15-0 XXAA XX55 XXA0 DATA

SW0 SW1 SW2 WORD

(ADDR/DATA) 1223 F05.3

Note: AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

ADDRESS AMS-0

TCE

CE#

TOEH TOES

OE#

TOE

WE#

DQ7 DATA DATA# DATA# DATA

1223 F06.2

Note: AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

FIGURE 6: DATA# POLLING TIMING DIAGRAM

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

16
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

ADDRESS AMS-0

TCE

CE#

TOE TOES
TOEH

OE#

WE#

DQ6 and DQ2

TWO READ CYCLES

1223 F07.3
WITH SAME OUTPUTS
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

FIGURE 7: TOGGLE BITS TIMING DIAGRAM

TSCE
SIX-BYTE CODE FOR CHIP-ERASE

ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555

CE#

OE#

TWP

WE#

DQ15-0
XXAA XX55 XX80 XXAA XX55 XX10

SW0 SW1 SW2 SW3 SW4 SW5

1223 F08.4

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

17
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

TBE
SIX-BYTE CODE FOR BLOCK-ERASE

ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA BAX

CE#

OE#

TWP

WE#

DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50

SW0 SW1 SW2 SW3 SW4 SW5

1223 F09.4
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
BAX = Block Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

SIX-BYTE CODE FOR SECTOR-ERASE TSE

ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX

CE#

OE#

TWP

WE#

DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30

SW0 SW1 SW2 SW3 SW4 SW5

1223 F10.4
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
SAX = Sector Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

18
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

Three-Byte Sequence for Software ID Entry

ADDRESS A14-0 5555 2AAA 5555 0000 0001

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ15-0
XXAA XX55 XX90 00BF Device ID

SW0 SW1 SW2 1223 F11.2

Note: Device ID = 234BH for 39VF1601, 234AH for 39VF1602, 235BH for 39VF3201, 235AH for 39VF3202,
236BH for 39VF6401, and 236AH for 39VF6402,
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 11: SOFTWARE ID ENTRY AND READ

Three-Byte Sequence for CFI Query Entry

ADDRESS A14-0 5555 2AAA 5555

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ15-0
XXAA XX55 XX98

SW0 SW1 SW2

1223 F12.1
Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 12: CFI QUERY ENTRY AND READ

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

19
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

ADDRESS A14-0 5555 2AAA 5555

DQ15-0 XXAA XX55 XXF0

TIDA
CE#

OE#

TWP
WE#
T WHP
SW0 SW1 SW2 1223 F13.0

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value

FIGURE 13: SOFTWARE ID EXIT/CFI EXIT

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

ADDRESS AMS-0 5555 2AAA 5555

CE#

OE#

TWP TIDA

WE#

TWPH
TAA
DQ15-0
XXAA XX55 XX88

SW0 SW1 SW2

1223 F20.1
Note: AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value.

FIGURE 14: SEC ID ENTRY

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

20
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

TRP

RST#

CE#/OE# TRHR
1223 F22.1

FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)

TRP

RST#
TRY

CE#/OE#

End-of-Write Detection
(Toggle-Bit) 1223 F23.0

FIGURE 16: RST# TIMING DIAGRAM (DURING PROGRAM OR ERASE OPERATION)

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

21
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

VIHT

INPUT VIT REFERENCE POINTS VOT OUTPUT

VILT

1223 F14.0

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: VIT - VINPUT Test

VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TO TESTER

TO DUT

CL

1223 F15.0

FIGURE 18: A TEST LOAD EXAMPLE

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

22
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load Word
Address/Word
Data

Wait for end of

Program (TBP,
Data# Polling
bit, or Toggle bit
operation)

Program
Completed

1223 F16.0

X can be VIL or VIH, but no other value

FIGURE 19: WORD-PROGRAM ALGORITHM

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

23
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

Internal Timer Toggle Bit Data# Polling

Program/Erase Program/Erase Program/Erase

Initiated Initiated Initiated

Wait TBP, Read word Read DQ7

TSCE, TSE
or TBE

Read same No Is DQ7 =

Program/Erase word true data?
Completed
Yes

No Does DQ6 Program/Erase

match? Completed

Yes

Program/Erase
Completed
1223 F17.0

FIGURE 20: WAIT OPTIONS

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

24
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

CFI Query Entry Sec ID Query Entry Software Product ID Entry

Command Sequence Command Sequence Command Sequence

Load data: XXAAH Load data: XXAAH Load data: XXAAH

Address: 5555H Address: 5555H Address: 5555H

Load data: XX55H Load data: XX55H Load data: XX55H

Address: 2AAAH Address: 2AAAH Address: 2AAAH

Load data: XX98H Load data: XX88H Load data: XX90H

Address: 5555H Address: 5555H Address: 5555H

Wait TIDA Wait TIDA Wait TIDA

Read CFI data Read Sec ID Read Software ID

X can be VIL or VIH, but no other value

1223 F21.0

FIGURE 21: SOFTWARE ID/CFI ENTRY COMMAND FLOWCHARTS

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

25
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XXAAH Load data: XXF0H

Address: 5555H Address: XXH

Load data: XX55H

Wait TIDA
Address: 2AAAH

Load data: XXF0H Return to normal

Address: 5555H operation

Wait TIDA

Return to normal
operation

X can be VIL or VIH, but no other value

1223 F18.1

FIGURE 22: SOFTWARE ID/CFI EXIT COMMAND FLOWCHARTS

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

26
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

Chip-Erase Sector-Erase Block-Erase

Command Sequence Command Sequence Command Sequence

Load data: XXAAH Load data: XXAAH Load data: XXAAH

Address: 5555H Address: 5555H Address: 5555H

Load data: XX55H Load data: XX55H Load data: XX55H

Address: 2AAAH Address: 2AAAH Address: 2AAAH

Load data: XX80H Load data: XX80H Load data: XX80H

Address: 5555H Address: 5555H Address: 5555H

Load data: XXAAH Load data: XXAAH Load data: XXAAH

Address: 5555H Address: 5555H Address: 5555H

Load data: XX55H Load data: XX55H Load data: XX55H

Address: 2AAAH Address: 2AAAH Address: 2AAAH

Load data: XX10H Load data: XX30H Load data: XX50H

Address: 5555H Address: SAX Address: BAX

Wait TSCE Wait TSE Wait TBE

Chip erased Sector erased Block erased

to FFFFH to FFFFH to FFFFH

1223 F19.0
X can be VIL or VIH, but no other value

FIGURE 23: ERASE COMMAND SEQUENCE

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

27
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

PRODUCT ORDERING INFORMATION

SST 39 VF 6402 - 70 - 4C - EK E
XX XX XXXX - XXX - XX - XXX X
Environmental Attribute
E = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
E = TSOP (type1, die up, 12mm x 20mm)
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
B1 = TFBGA (8mm x 10mm, 0.8mm pitch)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
90 = 90 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
160 = 16 Mbit
320 = 32 Mbit
640 = 64 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash

Valid Combinations for SST39VF1601

SST39VF1601-70-4C-EK SST39VF1601-70-4C-B3K
SST39VF1601-70-4C-EKE SST39VF1601-70-4C-B3KE
SST39VF1601-90-4C-EK SST39VF1601-90-4C-B3K
SST39VF1601-90-4C-EKE SST39VF1601-90-4C-B3KE
SST39VF1601-70-4I-EK SST39VF1601-70-4I-B3K
SST39VF1601-70-4I-EKE SST39VF1601-70-4I-B3KE
SST39VF1601-90-4I-EK SST39VF1601-90-4I-B3K
SST39VF1601-90-4I-EKE SST39VF1601-90-4I-B3KE

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

28
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications
Valid Combinations for SST39VF1602
SST39VF1602-70-4C-EK SST39VF1602-70-4C-B3K
SST39VF1602-70-4C-EKE SST39VF1602-70-4C-B3KE
SST39VF1602-90-4C-EK SST39VF1602-90-4C-B3K
SST39VF1602-90-4C-EKE SST39VF1602-90-4C-B3KE
SST39VF1602-70-4I-EK SST39VF1602-70-4I-B3K
SST39VF1602-70-4I-EKE SST39VF1602-70-4I-B3KE
SST39VF1602-90-4I-EK SST39VF1602-90-4I-B3K
SST39VF1602-90-4I-EKE SST39VF1602-90-4I-B3KE

Valid Combinations for SST39VF3201

SST39VF3201-70-4C-EK SST39VF3201-70-4C-B3K
SST39VF3201-70-4C-EKE SST39VF3201-70-4C-B3KE
SST39VF3201-90-4C-EK SST39VF3201-90-4C-B3K
SST39VF3201-90-4C-EKE SST39VF3201-90-4C-B3KE
SST39VF3201-70-4I-EK SST39VF3201-70-4I-B3K
SST39VF3201-70-4I-EKE SST39VF3201-70-4I-B3KE
SST39VF3201-90-4I-EK SST39VF3201-90-4I-B3K
SST39VF3201-90-4I-EKE SST39VF3201-90-4I-B3KE

Valid Combinations for SST39VF3202

SST39VF3202-70-4C-EK SST39VF3202-70-4C-B3K
SST39VF3202-70-4C-EKE SST39VF3202-70-4C-B3KE
SST39VF3202-90-4C-EK SST39VF3202-90-4C-B3K
SST39VF3202-90-4C-EKE SST39VF3202-90-4C-B3KE
SST39VF3202-70-4I-EK SST39VF3202-70-4I-B3K
SST39VF3202-70-4I-EKE SST39VF3202-70-4I-B3KE
SST39VF3202-90-4I-EK SST39VF3202-90-4I-B3K
SST39VF3202-90-4I-EKE SST39VF3202-90-4I-B3KE

Valid Combinations for SST39VF6401

SST39VF6401-70-4C-EK SST39VF6401-70-4C-B1K
SST39VF6401-70-4C-EKE SST39VF6401-70-4C-B1KE
SST39VF6401-90-4C-EK SST39VF6401-90-4C-B1K
SST39VF6401-90-4C-EKE SST39VF6401-90-4C-B1KE
SST39VF6401-70-4I-EK SST39VF6401-70-4I-B1K
SST39VF6401-70-4I-EKE SST39VF6401-70-4I-B1KE
SST39VF6401-90-4I-EK SST39VF6401-90-4I-B1K
SST39VF6401-90-4I-EKE SST39VF6401-90-4I-B1KE

Valid Combinations for SST39VF6402

SST39VF6402-70-4C-EK SST39VF6402-70-4C-B1K
SST39VF6402-70-4C-EKE SST39VF6402-70-4C-B1KE
SST39VF6402-90-4C-EK SST39VF6402-90-4C-B1K
SST39VF6402-90-4C-EKE SST39VF6402-90-4C-B1KE
SST39VF6402-70-4I-EK SST39VF6402-70-4I-B1K
SST39VF6402-70-4I-EKE SST39VF6402-70-4I-B1KE
SST39VF6402-90-4I-EK SST39VF6402-90-4I-B1K
SST39VF6402-90-4I-EKE SST39VF6402-90-4I-B1KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

29
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

PACKAGING DIAGRAMS

1.05
0.95
Pin # 1 Identifier

0.50
BSC

0.27
12.20 0.17
11.80

0.15
18.50 0.05
18.30

DETAIL
1.20
max.
0.70
0.50 20.20
19.80
0˚- 5˚
0.70
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, 0.50
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
1mm
3. Coplanarity: 0.1 mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM

SST PACKAGE CODE: EK

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

30
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
www.DataSheet4U.com Preliminary Specifications

TOP VIEW BOTTOM VIEW

8.00 ± 0.20 5.60
0.80 0.45 ± 0.05
(48X)

6 6
5 5
4 4.00 4
6.00 ± 0.20
3 3
2 2
1 1
0.80

A B C D E F G H H G F E D C B A

A1 CORNER A1 CORNER
1.10 ± 0.10
SIDE VIEW

0.12
SEATING PLANE 1mm
0.35 ± 0.05

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm) 48-tfbga-B3K-6x8-450mic-4

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM

SST PACKAGE CODE: B3K

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

31
 16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
Preliminary Specifications
www.DataSheet4U.com

TOP VIEW BOTTOM VIEW

10.00 ± 0.20 5.60
0.80

6 6
5 5
4.00
4 4
8.00 ± 0.20
3 3
2 2
1 1
0.80
0.45 ± 0.05
(48X)

A B C D E F G H H G F E D C B A

A1 CORNER A1 CORNER

1.10 ± 0.10
SIDE VIEW

0.12 1mm
SEATING PLANE
0.35 ± 0.05

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm) 48-tfbga-B1K-8x10-450mic-4

48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM

SST PACKAGE CODE: B1K

TABLE 18: REVISION HISTORY

Number Description Date
00 • Initial release Mar 2003
01 • Corrected Pin 15 from A20 to NC for SST39VF160x in Figure 1 on page 6 Apr 2003
02 • Changed data sheet title Jun 2003
03 • 2004 Data Book Nov 2003
• Updated the B3K and B1K package diagrams
• Added non-Pb MPNs and removed footnote. (See page 28)

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com

©2003 Silicon Storage Technology, Inc. S71223-03-000 11/03

32