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A REVIEW APPROACH OF POWER GRID ANALYSIS IN VLSI DESIGNS

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International Journal of Advanced Computational Engineering and Networking, ISSN: 2320-2106 Volume- 1, Issue- 6,Aug-2013

A REVIEW APPROACH OF POWER GRID ANALYSIS IN VLSI

DESIGNS
1
NWOKORIE E.C., 2ELUSOJI A. A.

Computer Science Department, Federal University of Technology, Owerri

Computer Science Department, Yaba College of Technology, Lagos-State Nigeria.
Email: [email protected], [email protected]

Abstract- One of the most critical challenges in today’s CMOS VLSI design is the lack of predictability in chip performance
at design stage. One of the process variability comes from the voltage drop variations in on-chip power distribution
networks. Power distribution systems in integrated circuits are used to provide the voltages and currents the devices need to
operate properly. It provides the voltages and currents that devices in a circuit need to operate properly and silicon success
requires its careful design and verification. In our work, we have Proposed the cell characterization methodology for
instantaneous IR drop analysis as well as Power Up analysis for MTCMOS, computed resistances and capacitors based on
technology data for 130nm node. A sample program was written to realize the mesh structure. This new algorithm is very
efficient and scalable for huge networks with a large number of variation variables.

Keywords: Power grid, Verification, Simulation, Voltage drop

I. INTRODUCTION Power grid analysis and verification is, one of the

most important steps in the design flow, yet
The power distribution system design is an area of computationally a very complex one. Power grid
increasing concern in semiconductor industry. verification is usually accomplished by simulation
According to data in [1], more than 50% of tape outs [5], [9]. The disadvantage of simulation is that stimuli
using 0.13-micron technology would fail, if the must be generated very carefully such that the
power distribution system were not validated relevant scenarios are accounted for. Only settings
beforehand. Lower operating voltages, increased corresponding to the chosen stimuli are simulated and
device integration density and leakage currents, thus verified, so they should be chosen appropriately
higher operating frequencies and the use of low and should be representative of relevant situations.
power design techniques; they all tend to stress the Since the power grid encompasses the whole die area,
power grid as technology evolves. The design of such its description is rather large and the simulation
systems is complex and error-prone, since there is a process is slow and highly complex. These results
wide variety of an aspect that must be taken into from the necessity to take into account a huge number
account. Of these, perhaps the four major problems of power grid parameters (RLC non-idealities) and all
that may affect power distribution systems are the devices that take current from it, as shown in Fig.
voltage drop, ground bounce, and L di/dt noise and 1. Simulating the power grid with all the devices
electro migration [4]. might be impossible for VLSI circuits, as it would
consume too many resources. Furthermore,
Voltage drop, also called IR drop, is the voltage simulating for all possible device settings is also
reduction that occurs on power supply networks. The impossible, as it would take too long. In addition,
IR drop can be static or dynamic and results from the given the size of current designs, it is also impossible
existence of non-ideal elements: the resistance within to assume that designer intervention will be sufficient
the power and ground supply wiring and the to generate appropriate sets of stimuli for the grid
capacitance between them. While static voltage drop verification. Typically no single designer knows
considers only the average currents, dynamic voltage enough of the circuit behavior, as a whole, to perform
drop considers current waveforms within clock cycles such task. Even if that were possible, it would require
and has a RC transient behavior. Similar effects may considerable effort from designers and might delay
be found in ground wiring, usually referred as ground significantly the design process. Therefore, an
bounce. Both effects contribute to lower operating automatic way of generating realistic sets of stimuli
voltages within devices (i.e. logic cells/gates in given the knowledge of the actual circuit
digital circuits), which in general increase the overall implementation is necessary.
time response of a device and might cause a failure in
its operation. The L di/dt noise is caused by current
spikes on wires that will induce abrupt voltage
changes on these wires and their neighboring wires,
due to inductance coupling [6], [2].

A Review Approach Of Power Grid Analysis In VLSI Designs

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International Journal of Advanced Computational Engineering and Networking, ISSN: 2320-2106 Volume- 1, Issue- 6,Aug-2013

that purpose, a RC extraction is done as well as the

definition of power grid stimuli. This mainly consists
on the definition of the circuit cells, which must be
considered throughout the simulation, and their
correspondent current waveforms.

Some of the simulation tools consider all the circuit

devices as stimuli to the power grid. Others allow
users to define which stimuli should be applied, i.e.,
which circuit cells are going to be considered during
simulation. Most of the times this definition is based
Figure 1. A Simplified power grid model.
on user experience and knowledge. However, both
options may deteriorate the quality and resulting
Hopefully, this task can be integrated in a standard accuracy of power grid simulation [8].
design & verification framework and accomplished
efficiently in an acceptable time.
Timing and spatial constraints arising from the circuit
net list and placement prevent most of the devices
from being active at the same time. Therefore, power
grid simulation that considers all the circuit devices
as simultaneously active is clearly unnecessary.
Voltage drop and ground bounce may occur if there is
a significant number of devices becoming active in a
short period of time and drawing current from close
regions of the power grid. We propose a technique to
determine, within a time frame, how many devices
become active on nearby regions of the power grid.
The higher the number of devices in this situation, the
greater the possibility of voltage drop and/or ground
bounce effects be felt in the power grid (assuming the
grid has a regular structure and that all devices take
an equal amount of current) [7]. Combining timing
and spatial information obtained in a traditional
design flow it is possible to know when and which
devices are active in order to generate a set of more
realistic worst-case stimuli for grid verification.
Figure 2. Traditional design flow (with emphasis on power grid
II. A RELATED TRADITIONAL DESIGN
FLOW A critical region may be neglected if the user misses
the combination of grid stimuli that will cause the
Simulation is the most commonly used method to worst voltage drop or ground bounce (a false
validate the power grid. It enables one to verify if the negative). Results from a simulation obtained on the
power grid is suited for a given design, that is, if it is assumption that all cells need to be accounted for,
robust enough to deal with problems such as voltage may also identify invalid critical regions of the power
drop and ground bounce. In Fig. 2 a simplified grid that are supposedly affected by voltage drop or
version of a standard design flow, with emphasis in ground bounce (a false positive) [10]. This occurs
power grid design and analysis, is presented. As can because in normal working conditions all cells in the
be seen in Fig. 2 a typical flow starts with a circuit circuit cannot draw current from the power grid at the
description in VHDL or Verilog. This description is same time. Moreover, this type of simulation may
converted into a gate-level net list of a given also increase total runtime and memory requirements
technology library during logical synthesis. After from simulators. After this simulation procedure, the
synthesis, place & route of circuit cells is done. To designer will try to solve IR-drop problems, usually
ensure the circuit timing sign-off, static timing by placing decoupling capacitance inside those
analysis (STA) is usually done afterwards. If STA critical regions [14]. If those regions are non-critical,
fails, a new place & route should be performed. Then, from a voltage drop and ground bounce point of view,
power grid planning is done based on the knowledge the insertion of decoupling capacitance will only
of power distribution along the circuit [3]. However, increase the overall static power consumption and it
this knowledge is, of course, rather limited. After the will be a waste of silicon area. This circuit changes
power grid design, a simulation (at electrical level) of can itself cause voltage drop and ground bounce to
the grid along with the “circuit” is performed. For appear in other circuit regions

A Review Approach Of Power Grid Analysis In VLSI Designs

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International Journal of Advanced Computational Engineering and Networking, ISSN: 2320-2106 Volume- 1, Issue- 6,Aug-2013

III. CURRENT CHARACTERIZATION

METHODOLOGY

For instantaneous Power Grid analysis, we analyzed

cell peak current waveforms. Figure 3.1 shows
transient waveform of inverter cell which was
simulated at 250MHz. (VDD is power pin and VSS is
ground pin) It has voltage waveform of primary input
and primary output (VA, VY) of inverter. It also has
current waveform in VDD and VSS port (IRVDD,
IRVSS). The voltage waveform at VDD and VSS
port is seen. (VVDD_INV1, VVSS_INV1). Note that
current waveform at VDD and VSS are similar except
one difference – transition direction. The current
waveform at VDD when output is charging is same as Figure 3.2 transition time vs. peak power for Inverter
current waveform at VSS when output is discharging
and vice versa. This is true in this case for inverter
but it can vary if the cell is not balanced properly.
However in any case the amount of charge
supplied/discharged will be constant since it is
governed by load connected at output

Figure 3.3 Transition time vs. peak power for nand gate

· Peak power varies while change in output load. The

change is as expected since capacitance increase
along with MOS resistance provides exponential
voltage ramp up. Peak is largely dependent on MOS
ON resistance as well as initial voltage. Figure 3.4
and Figure 3.5 shows the plot of variation for AND as
well as OR gate. Note that the variation is ~1-3%
across wide range of load.

Figure 3.1 Inverter waveforms measured at different nodes

Note here that the overall simulation time decreases

when frequency increases for a same set of patterns.
This is not a surprise as the load being charged and
discharged is same during each transition for the
same slew and for the same set of patterns. In case of
CMOS gate, shape of current waveform remains
same for very high frequencies (period ~= 3 times of
0-100% slew).
· The slew or transition time (used interchangeably)
plays a big role for peak power determination of cells.
When the slew decreases, the width of the current
spike decreases with increase in peak. Figure 3.2 and
Figure 3.3 shows the peak power variation for
different input transition times. Note the variation of
~2x for inverter and ~1.5x for 2 input NAND gate. Figure 3.4 Load vs. peak power for AND gate

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International Journal of Advanced Computational Engineering and Networking, ISSN: 2320-2106 Volume- 1, Issue- 6,Aug-2013

IV. ANALYSIS OF THE POWER GRID

NETWORK MODELING

This section describes the Power Grid network

building using cell characterization data. Power Grid
offers resistance, capacitance as well as inductance to
the switching logic. Figure 3.7 shows schematic
of typical power grid. [15] The power & ground
supply pins are modeled as ideal voltage sources. The
methodology however vastly varies in terms of
current source modeling and capacitance estimation
Figure 3.5 Load vs. Peak power for OR gate [5, 11, 14, 3]
· For cell characterization, pattern dependency is not
critical. This is expected as most of the circuits will
be 1-2 level of logic where each pattern will
activate/deactivate most of the transistors. However,
soon when cells start becoming larger, some logic
may not get activated during switching. In this case, it
is important to choose useful patterns for cell current
characterization [9].
· For cell characterization, transition direction matters
for a given power supply. It means that output rise
transition or fall transition are important to capture
during characterization and use them appropriately
during use. (Figure 3.1) In our case, we capture rise
and fall transition together and use them for analysis,
making proposed approach direction independent.
Figure 3.6 State Dependency on cell switching
Figure 3.7 Power Grid Modeling

Once, the power grid is determined along with

capacitance and current source distribution, it can be
realized as matrix data structure and can be solved for
computing voltages at desired nodes – specifically the
nodes where cell components are connected as below.
V*Y=I
Where V is voltage value at each node, Y is
admittance or resistance of PG segment, I is current
that we have characterized.
OR
v(t) = Z * i(t) ( Z = R – jW for power
Figure 3.6 State Dependency on cell switching network )
V(w) = z(w) * i(w)
1. Slew impacts the short circuit current of the device.
For multi-stage block, slew impacts 1st stage the In our work, we have computed resistances and
most and the overall current waveform is unaffected capacitors based on technology data for 130nm node.
due to this change. The impact varies from lo to hi A sample program was written to realize the mesh
when the design stages are decreasing. structure as shown in Figure 3.7 for VDD network
2. Glitches or hazardous transitions can contribute to and VSS was taken as ideal ground. This is not an
peak current need of the circuit. issue since we can lump all the VSS network
Modeling glitches in non-SPICE analysis is not elements to VDD network. After determining Power
trivial. It is desired that glitches are reduced by robust Grid Current Waveform, we solved the network
design practices. In this work, it is assumed that there through SPICE simulations [17].
are no glitches in the design. A) Power Grid Current Waveform Modeling
3. The temporal correlation between different inputs Power Grid Current waveform modeling involves
influences the characterization data a lot. This is due following steps:
to simultaneous switching. We have used the least 1. Compute Toggle frequency for each of the instance
affecting combination i.e. 0 skew between multiple in design
inputs in our analysis – this is worst case also. (Figure 2. Transform the current data at the computed toggle
3.6) frequency.
A Review Approach Of Power Grid Analysis In VLSI Designs

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International Journal of Advanced Computational Engineering and Networking, ISSN: 2320-2106 Volume- 1, Issue- 6,Aug-2013

3. Compute the input arrival for each of the instance we do that, the generated simulation time is
in design. This is done using Static Timing Analysis. prohibitively high. The memory space also becomes
Compute the shift required in current waveform with high.
reference to clock edge. For simplicity, we have · In reality we are using a smaller number than that to
assumed 0 skew for clock network. ensure less simulation time and more realistic data.
4. Hook up the current sources and solve the PG Instead we computed simulation time as below.
network. Tstop = f(minimum toggle frequency, max
5. Determine the PG model simulation time. delay)
These are explained further below. = Time Period of minimum freq
cell + maximum delay of all cell outputs
A) Read the characterized data. = 2000 ns (for minimum frequency
Characterized data was transformed from time as 1 MHz and 1000 ns as worst delay)
domain to frequency domain. The sampling is done at
fixed frequency (much higher than common design E) Establishing temporal relationship
frequency
values) – 1000/75 ~ 13.33 GHz and [t, i(t)] are stored. Do timing analysis and based on input arrival time,
I(t) = i(0)d(0) + i(0+Ts)d(0+Ts) + the current waveforms are shifted along time axis.
i(0+2*Ts)d(0+2*Ts) + … N Samples The purpose behind timing analysis is to establish
Where, temporal correlation between various nodes of the
‘Ts’ is sampling frequency – in this case design i.e. even though 2 or more nodes have same
13.33 GHz toggle frequency; this will not switch all instances in
i(t) is current value at time ‘t’ design simultaneously unless needed. In this work,
d(t) = 1 when t=n*Ts else 0. n ranges from we have chosen to work with toggle frequency and
1,…,N delay instead of timing window [18][19]. The
For computation efficiency N may be chosen as reasons,
power of 2… N = 2 ** n (n is integer) · Not all circuit nodes switch in all the clock cycles.
Now, the Fourier transform of the samples have been Average activity computation establishes relative
performed: amount of switching among various nodes. This is
I[k] = i[n]* possible because activity estimation techniques
consider circuit functionality. Average switching
B) Model the current waveform for each Boolean activity for most of nodes is believed at 20% of the
gate at computed toggle frequency. controlling clock frequency. In certain solutions, the
· A compression factor (M) is defined to meet the average switching activity for non clock signals is
targeted frequency of the cell under consideration. assumed to be 10% only.
M = targeted frequency/cell characterized · Timing window method uses classical path
frequency (10MHz in this work) sensitization to identify the interval of switching.
· Transformation allows preserving base of the Inherent assumption of STA that all activity on a path
current transients. This would not have been possible should finish within 1 clock period (unless specified
in a time domain while we scale frequency. Hence, explicitly using multi-cycle path), the timing intervals
the need of frequency domain transformation. for all nodes will lie within a clock period. This
· Current data is compressed by compression factor. makes whole approach of pseudo dynamic simulation
· When the data was transformed to frequency pessimistic.
domain and the frequency spectrum was seen, the · During timing analysis, we collected 2 sets of data.
notable point was that we had a good chunk of lower One, sensitization edge of the node i.e. whether the
frequency components -signifying the approximate node is rising or falling at that time and second, delay
triangles of SPICE waveform and most of the of the node from reference node. It can be seen that
medium to high frequency components were zero - any frequency higher than 1 MHz will have at least
signifying the zero or low-leakage portion of the some repetition in its current signature i.e. a node is
power waveform. switching at 50 MHz (20ns) will have 50 repetitions
of its current signature in 1000 ns simulation. By
C) Attach the current waveform at a PG node where changing the minimum frequency, we can change the
this cell’s power or ground pin is connected. simulation time considerably. For example, by
changing minimum frequency to 50 MHz, we can
D) Compute the total simulation time ensure that all the current sources with less than 50
· If all instances in the design are applied with MHz do not contribute (or contributes an average
respective waveforms, metrics solver gives peak current) to dynamic V drop analysis and in that case
voltage drop value from 0 to LCM (period of all maximum simulation time can become only 20 ns. In
gates) all our analysis we have assumed 1 MHz as minimum
· Computing lowest common multiplier (LCM) is frequency [16].
computationally intensive for most designs. Even if

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 International Journal of Advanced Computational Engineering and Networking, ISSN: 2320-2106 Volume- 1, Issue- 6,Aug-2013

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