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Figure 1: 6T Cell

This document discusses the design and operation of a 6T SRAM cell. It begins with an introduction to SRAM and how decreasing MOSFET sizes have led to faster operation. It then provides details on the basic components and operational modes of SRAM cells. The document presents the circuit diagram and layout of a 6T SRAM cell and describes its read and write operations. It also briefly discusses a 4T SRAM cell design but notes that the 6T cell provides better stability and is more commonly used. In the end, it mentions generating the layout of a 6T SRAM cell in Microwind software.

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Shehryar
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42 views

Figure 1: 6T Cell

This document discusses the design and operation of a 6T SRAM cell. It begins with an introduction to SRAM and how decreasing MOSFET sizes have led to faster operation. It then provides details on the basic components and operational modes of SRAM cells. The document presents the circuit diagram and layout of a 6T SRAM cell and describes its read and write operations. It also briefly discusses a 4T SRAM cell design but notes that the 6T cell provides better stability and is more commonly used. In the end, it mentions generating the layout of a 6T SRAM cell in Microwind software.

Uploaded by

Shehryar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Introduction:

As we watch, that with the advancement of innovation, technology are downsizing every
occasionally, which leads to decrease in the length of the channel of the MOSFET, offering
significance to speed of activity. This paper comprise of structuring 6T SRAM cell, alongside
its READ and WRITE operations, which works at, fast. We uses Microwind software for
making layout and graphs for analyse result

The static RAM:


Random Access Memory (RAM) is allowed data bits or group of bits to store in it.Basicaaly
RAM allow us read and write operation at a time and have unique quality other than ROM
read only memory.
Static Random Access Memory (SRAM) cell have bistable circuit which is use to read and
write and hold data bit. Main function of RAM is to store data bit for long time. It has three
operational modes
1. Hold state
2. Write operation
3. Read operation
In hold mode, no data bit read and write and value stored for further use and in write
operation 0 and 1 feed to stored and in read operation data bit appearing in output.
Circuit diagram

Figure 1: 6T Cell
This circuit is divided by sub circuit as the main memory part of cell is located at the middle
of the circuit which is consist of pair of cross-coupled inverters provide the storage. While the
other access transistors at right and left of the circuit provide read and write operation and
this transistor is controlled by word line signal, which control this operation as when did it
turns off and on. This word line signal hold the circuit and give control to read and write
mode.
When WL has value 0 than it means that both FETs are off and cell in hold mode. This is
called hold state mode. When WL is one then access transistor work and connecting to BL
(bit line) and bit bar line, which define, write and read operation and act as input and output
for read and write operation. This output are fed into the sensor amplifier that determine the
stored state at the operation of read and stored value at the time of write.

4T SRAM cell:
We have two types of SRAM structure one is 6T transistor, which is, show above and other
is 4T transistor, which uses resistors as load device in an nMOS circuit. The complexity of
the 4T cell is to make a resister load high value (in gaga ohms) to minimize the current due to
which this resistor must not give us good functionality. It has small size than 6T.it is 20
percent less in the size compare with 6T.  Power consumption of the 4T SRAM Cell is reduce
up to 36% as compare to 6T SRAM Cell. However, due to a lot of limitation in it, speed of
4T SRAM cell has slow. This is not use practically as each cell has current flowing in one
resistors and cell is sensitive to noise and have many small error. We are working on 6T
SRAM cell.

Figure 2: 4T cell with poly resistors


This is 4T cell Circuit has low area and less power consumption but has low speed and need
high value of resistance for controlling current.
Stability of device is more important so we choice 6T cell which uses nFETs and pFETs for
storage purpose. Stability of 6T SRAM cell depends upon the functionality of cross-coupled
invertor cell.

Read Operation:
In SRAM, for activation voltage of the word line WL=one to be high. To perform read
activity, at first memory ought to have some value. Understand these lines let us consider
memory has Q=1 and Qbar =0. Increase the WL voltage to high, to play out the read
activity. Bit and bit bar goes about as output lines, and these bit lines are at first pre-charged
for example there will be a node voltage Vdd at bit and bit bar. As Q and bit are high, there
will be no voltage in the circuit. As Bar is zero, there will be a voltage distinction between the
Bar and the node voltage at bit bar, thus bit bar voltage diminishes. Along these lines, there
will be release in the circuit and current streams. Bit and bit bar are associated with the sensor
amplifier, this sensor act as a comparator, so when bit bar is zero the output will be one.
Henceforth input Q is one and we got the one, read activity confirmed. Similarly consider Q
is zero and Qbar one in the memory. There will be a release in the circuit at Q and bit, since
there is voltage distinction. The transistors must have proportion with the end goal that Q lies
underneath the limit area of P2/D2. This is called read operation. As bit voltage diminishes
the output will be 0.when input Q is zero, we get is zero. In this way in both the cases read
activity is confirmed.

Write operation:
Consider the memory bits comprises of Q is zero and Qbar=1. At first WL=1 is high and
hence write operation activity can be performed. In this operation bit and bit' are input lines.
As we have control on the bit lines, at first make the bit_b attached with Vss so we can have
the voltage distinction among Q' and bit_b. To compose one into the SRAM cell. Thus, Q
will be one. At first Q is zero after the all process and operation we have Q is one in the
memory, henceforth we compose effectively into the memory and write data in the memory.

SRAM layout in Microwind


We have 6T SRAM cell layout by design 4 nMOS and 2 pMOS. The nMOS have 1um width
and
0.200um length and pMOS have 4.32um width and 0.20 um length. we connected nMOS
with ground and pMOS transistor with Vdd voltage.
Access transistor connected with the WL for read and write operation and BL and BL bar act
as input and output..

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