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PEEL™ 18CV8 -5/-7/-10/-15/-25

CMOS Programmable Electrically Erasable Logic Device
Features Architectural Flexibility
- Enhanced architecture fits in more logic
■ Multiple Speed Power, Temperature Options - 74 product terms x 36 input AND array
- VCC = 5 Volts ±10% - 10 inputs and 8 I/O pins
- Speeds ranging from 5ns to 25 ns - 12 possible macrocell configurations
- Power as low as 37mA at 25MHz - Asynchronous clear
- Commercial and industrial versions available - Independent output enables
■ CMOS Electrically Erasable Technology -- 20 Pin DIP/SOIC/TSSOP and PLCC
- Superior factory testing
- Reprogrammable in plastic package ■ Application Versatility
- Reduces retrofit and development costs - Replaces random logic
■ Development / Programmer Support - Super sets PLDs (PAL, GAL, EPLD)
- Third party software and programmers - Enhanced Architecture fits more logic than ordinary
- ICT PLACE Development Software and PDS-3 PLDs
programmer
- PLD-to-PEEL JEDEC file translator

General Description
The PEEL18CV8 is a Programmable Electrically Erasable The PEEL18CV8 architecture allows it to replace over 20
Logic (PEEL) device providing an attractive alternative to standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
ordinary PLDs. The PEEL18CV8 offers the performance, vides additional architecture features so more logic can be
flexibility, ease of design and production practicality needed put into every design. ICT’s JEDEC file translator instantly
by logic designers today. converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC programming support for the PEEL18CV8 is provided by
and TSSOP packages with speeds ranging from 5ns to popular third-party programmers and development software.
25ns with power consumption as low as 37mA. EE-Repro- ICT also offers free PLACE development software and a
grammability provides the convenience of instant repro- low-cost development system (PDS-3).
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.

Figure 1 Pin Configuration Figure 2 Block Diagram

I/CLK 1 20 VCC
I 2 19 I/O
I 3 18 I/O
I 4 17 I/O
I 5 16 I/O
I 6 15 I/O
I 7 14 I/O
I 8 13 I/O
I 9 12 I/O
GND 10 11 I

DIP TSSOP

PLCC SOIC

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Figure 3 PEEL18CV8 Logic Array Diagram

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Function Description array. (Note that PEEL device programmers automatically

program all of the connections on unused product terms so
The PEEL18CV8 implements logic functions as sum-of- that they will have no effect on the output function).
products expressions in a programmable-AND/fixed-OR
logic array. User-defined functions are created by program-
ming the connections of input signals into the array. User- Programmable I/O Macrocell
configurable output structures in the form of I/O macrocells The unique twelve-configuration output macrocell provides
further increase logic flexibility. complete control over the architecture of each output. The
ability to configure each output independently permits
Architecture Overview users to tailor the configuration of the PEEL18CV8 to the
precise requirements of their designs.
The PEEL18CV8 architecture is illustrated in the block dia-
gram of Figure 2. Ten dedicated inputs and 8 I/Os provide
up to 18 inputs and 8 outputs for creation of logic functions. Macrocell Architecture
At the core of the device is a programmable electrically- Each I/O macrocell, as shown in Figure 4, consists of a D-
erasable AND array which drives a fixed OR array. With type flip-flop and two signal-select multiplexers. The config-
this structure, the PEEL18CV8 can implement up to 8 sum- uration of each macrocell is determined by the four
of-products logic expressions. EEPROM bits controlling these multiplexers. These bits
determine output polarity, output type (registered or non-
Associated with each of the 8 OR functions is an I/O mac- registered) and input-feedback path (bidirectional I/O, com-
rocell which can be independently programmed to one of binatorial feedback). Refer to Table 1 for details.
12 different configurations. The programmable macrocells
allow each I/O to create sequential or combinatorial logic Equivalent circuits for the twelve macrocell configurations
functions of active-high or active-low polarity, while provid- are illustrated in Figure 5. In addition to emulating the four
ing three different feedback paths into the AND array. PAL-type output structures (configurations 3,4,9, and 10),
the macrocell provides eight additional configurations.
AND/OR LOGIC ARRAY When creating a PEEL device design, the desired macro-
cell configuration generally is specified explicitly in the
The programmable AND array of the PEEL18CV8 (shown
design file. When the design is assembled or compiled, the
in Figure 3) is formed by input lines intersecting product
macrocell configuration bits are defined in the last lines of
terms. The input lines and product terms are used as fol-
the JEDEC programming file.
lows:
■ 36 Input Lines: Output Type
- 20 input lines carry the true and complement of the
signals applied to the 10 input pins The signal from the OR array can be fed directly to the out-
- 16 additional lines carry the true and complement val- put pin (combinatorial function) or latched in the D-type flip-
ues of feedback or input signals from the 8 I/Os flop (registered function). The D-type flip-flop latches data
on the rising edge of the clock and is controlled by the glo-
■ 74 product terms: bal preset and clear terms. When the synchronous preset
- 64 product terms (arranged in groups of 8) are used term is satisfied, the Q output of the register will be set
to form sum of product functions HIGH at the next rising edge of the clock input. Satisfying
- 8 output enable terms (one for each I/O) the asynchronous clear will set Q LOW, regardless of the
- 1 global synchronous preset term clock state. If both terms are satisfied simultaneously, the
- 1 global asynchronous clear term clear will override the preset.

At each input-line/product-term intersection, there is an Output Polarity

EEPROM memory cell that determines whether or not Each macrocell can be configured to implement active-high
there is a logical connection at that intersection. Each prod- or active-low logic. Programmable polarity eliminates the
uct term is essentially a 36-input AND gate. A product term need for external inverters.
that is connected to both the true and complement of an
input signal will always be FALSE and thus will not affect
the OR function that it drives. When all the connections on Output Enable
a product term are opened, a “don’t care” state exists and The output of each I/O macrocell can be enabled or dis-
that term will always be TRUE. abled under the control of its associated programmable
output enable product term. When the logical conditions
When programming the PEEL18CV8, the device program- programmed on the output enable term are satisfied, the
mer first performs a bulk erase to remove the previous pat- output signal is propagated to the I/O pin. Otherwise, the
tern. The erase cycle opens every logical connection in the output buffer is switched into the high-impedance state.
array. The device is configured to perform the user-defined
function by programming selected connections in the AND Under the control of the output enable term, the I/O pin can

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function as a dedicated input, a dedicated output, or a bi- Registered Feedback

directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and Feedback also can be taken from the register, regardless of
yield a dedicated output. Conversely, if every connection is whether the output function is to be combinatorial or regis-
intact, the enable term will always be logically false and the tered. When implementing a combinatorial output function,
I/O will function as a dedicated input.
registered feedback allows for the internal latching of states
without giving up the use of the external output.
Input/Feedback Select
The PEEL18CV8 macrocell also provides control over the Design Security
feedback path. The input/feedback signal associated with
each I/O macrocell may be obtained from three different The PEEL18CV8 provides a special EEPROM security bit
locations; from the I/O input pin, from the Q output of the that prevents unauthorized reading or copying of designs
flip-flop (registered feedback), or directly from the OR gate programmed into the device. The security bit is set by the
(combinatorial feedback). PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set it is impossible to
Bi-directional I/O verify (read) or program the PEEL until the entire device
The input/feedback signal is taken from the I/O pin when has first been erased with the bulk-erase function.
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output func- Programming Support
tion with a bi-directional I/O.)
ICT’s JEDEC file translator allows easy conversion of exist-
ing 20 pin PLD designs to the PEEL18CV8, without the
Combinatorial Feedback need for redesign. ICT supports a broad range of popular
The signal-select multiplexer gives the macrocell the ability third party design entry systems, including Data I/O Synario
to feedback the output of the OR gate, bypassing the out- and Abel, Logical Devices CUPL and others. ICT also
put buffer, regardless of whether the output function is reg- offers (for free) its proprietary PLACE software, an easy-to-
istered or combinatorial. This feature allows the creation of use entry level PC-based software development system.
asynchronous latches, even when the output must be dis-
abled. (Refer to configurations 5,6,7 and 8 in Figure 5.) Programming support includes all the popular third party
programmers; Data I/O, Logical Devices, and numerous
others. ICT also provides a low cost development program-
Figure 4 Block Diagram of the PEEL18CV8 mer system, the PDS-3.
I/O Macrocell

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Configuration
Input/Feedback Select Output Select
# A B C D
1 1 1 1 1 Bi-directional I/O Register Active Low
2 0 1 1 1 Bi-directional I/O Register Active High
3 1 0 1 1 Bi-directional I/O Combinatorial Active Low
4 0 0 1 1 Bi-directional I/O Combinatorial Active High
5 1 1 1 0 Combinatorial Feedback Register Active Low
6 0 1 1 0 Combinatorial Feedback Register Active High
7 1 0 1 0 Combinatorial Feedback Combinatorial Active Low
8 0 0 1 0 Combinatorial Feedback Combinatorial Active High
9 1 1 0 0 Register Feedback Register Active Low
10 0 1 0 0 Register Feedback Register Active High
11 1 0 0 0 Register Feedback Combinatorial Active Low
12 0 0 0 0 Register Feedback Combinatorial Active High

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This device has been designed and tested for the specified
operating ranges. Proper operation outside of these levels
is not guaranteed. Exposure to absolute maximum ratings
may cause permanent damage.
Absolute Maximum Ratings
Symbol Parameter Conditions Rating Unit
VCC Supply Voltage Relative to Ground -0.5 to + 6.0 V
VI, VO Voltage Applied to Any Pin2 Relative to Ground1 -0.5 to VCC + 0.6 V

IO Output Current Per Pin (IOL, IOH) ±25 mA

TST Storage Temperature -65 to +150 °C
TLT Lead Temperature Soldering 10 Seconds +300 °C

Operating Range
Symbol Parameter Conditions Min Max Unit
Commercial 4.75 5.25 V
Vcc Supply Voltage
Industrial 4.5 5.5 V
TA Commercial 0 +70 °C
Ambient Temperature
Industrial -40 +85 °C
TR Clock Rise Time See Note 3. 20 ns
TF Clock Fall TIme See Note 3. 20 ns
TRVCC VCC Rise Time See Note 3. 250 ms

D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)

Symbol Parameter Conditions Min Max Unit

VOH Output HIGH Voltage - TTL VCC = Min, IOH = -4.0 mA 2.4 V
VOHC Output HIGH Voltage - CMOS 12 VCC = Min, IOH = -10 µA VCC - 0.3 V

VOL Output LOW Voltage - TTL VCC = Min, IOL = 16mA/24mA 13 0.5 V

VOLC Output LOW Voltage - CMOS 12 VCC = Min, IOL = 10 µA 0.15 V

VIH Input HIGH level 2.0 VCC + 0.3 V

VIL Input LOW Voltage -0.3 0.8 V
Input, I/O Leakage Current LOW
IIL VCC = Max, VIN = GND, I/O = High Z -10 µA
Input and I/O pull-ups disabled
Input, I/O Leakage Current LOW
IIP VCC = Max, VIN = GND, I/O = High Z -100 µA
Input and I/O pull-ups enabled
IIH Input, I/O Leakage Current HIGH VCC = Max, VIN = VCC, I/O = High Z 0 (Typical) 40 µA
ISC9 Output Short Circuit Current VCC = 5V, VO = 0.5V, TA = 25°C -30 -135 mA
-5 90

VIN = 0V or VCC, -7 90
ICC10 VCC Current, f=1MHz f = 25 MHz -10 110/115 mA
All Outputs disabled4 -15 45/55
-25 37/50
CIN 7 Input Capacitance TA = 25°C, VCC = 5.0V 6 pF

COUT7 Output Capacitance @ f = 1 MHz 12 pF

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A.C. Electrical Characteristics

Over the operating range 8

-5 -7 -10/I-10 -15/I-15 -25/I-25

Symbol Parameter Units
Min Max Min Max Min Max Min Max Min Max
tPD Input5 to non-registered output 5 7.5 10 15 25 ns

tOE 5
Input to output enable 6 5 7.5 10 15 25 ns

tOD 5
Input to output disable 6 5 7.5 10 15 25 ns

tCO1 Clock to Output 4 7 7 12 15 ns

tCO2 Clock to comb. output delay

7.5 10 12 25 35 ns
via internal registered feedback
tCF Clock to Feedback 2.5 3.5 4 8 15 ns
tSC 5
Input or feedback setup to clock 3.5 5 5 12 20 ns
tHC Input5 hold after clock 0 0 0 0 0 ns
tCL, tCH Clock low time, clock high time 8 3 3.5 5 10 15 ns
tCP Min clock period Ext (tSC + tCO1) 7 12 12 24 35 ns
fMAX1 Internal feedback (1/tSC+tCF) 11 166.7 117.6 111 50 28.5 MHz
fMAX2 External Feedback (1/tCP) 11 133 83.3 83.3 41.6 28.5 MHz
fMAX3 No Feedback (1/tCL+tCH) 11 166.7 142.8 100 50 33.3 MHz
tAW Asynchronous Reset Pulse Width 5 7.5 10 15 25 ns
tAP 5 5 7.5 10 15 25 ns
Input to Asynchronous Reset
tAR Asynchronous Reset recovery time 5 7.5 10 15 25 ns
tRESET Power-on reset time for registers
5 5 5 5 5 µs
in clear state

Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset

Clock

Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs

Notes:
8. Test conditions assume: signal transition times of 3ns or less from the
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V
10% and 90% points, timing reference levels of 1.5V (Unless otherwise
for periods less than 20 ns.
specified).
2. VI and VO are not specified for program/verify operation.
9. Test one output at a time for a duration of less than 1 second.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10%
10. ICC for a typical application: This parameter is tested with the device
and 90% levels.
programmed as an 8-bit Counter.
4. I/O pins are 0V and VCC.
11. Parameters are not 100% tested. Specifications are based on initial
5. “Input” refers to an input pin signal.
characterization and are tested after any design process modification that
6. tOE is measured from input transition to VREF±0.1V, TOD is measured
might affect operational frequency.
from input transition to VOH -0.1V or V OL+0.1V; VREF=VL.
12. Available only for 18CV8 -15/I-15/-25/I-25 grades
7. Capacitances are tested on a sample basis.
13. 24mA available for 18CV8-5/-7. All other speeds are 16mA.

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PEEL Device and Array Test Loads

Standard 5V Thevenin VL
Load Equivalent

R1 RL
Output Output

CL R2 CL

Technology R1 R2 RL VL CL
12 480kΩ 480kΩ 228kΩ 2.375V 33 pF
CMOS
TTL -10/-15/-25 235Ω 159Ω 95Ω 2.02V 33 pF
TTL -5/-7 159Ω 118Ω 68Ω 2.129V 33 pF

Ordering Information
Part Number Speed Temperature Package
PEEL18CV8J-5 5 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8P-7 7.5 ns Commercial 20-pin Plastic 300 mil DIP
PEEL18CV8J-7 7.5 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8S-7 7.5 ns Commercial 20-pin SOIC
PEEL18CV8P-10 Commercial
10 ns 20-pin Plastic 300 mil DIP
PEEL18CV8PI-10 Industrial
PEEL18CV8J-10 Commercial
10 ns 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-10 Industrial
PEEL18CV8S-10 Commercial
10 ns 20-pin SOIC
PEEL18CV8SI-10 Industrial
PEEL18CV8T-10 Commercial
10 ns 20-pin TSSOP 170 mil
PEEL18CV8TI-10 Industrial
PEEL18CV8P-15 Commercial
15 ns 20-pin Plastic 300 mil DIP
PEEL18CV8PI-15 Industrial
PEEL18CV8J-15 Commercial
15 ns 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-15 Industrial
PEEL18CV8S-15 Commercial
15 ns 20-pin SOIC
PEEL18CV8SI-15 Industrial
PEEL18CV8T-15 Commercial
15 ns 20-pin TSSOP 170 mil
PEEL18CV8TI-15 Industrial
PEEL18CV8P-25 Commercial
25 ns 20-pin Plastic 300 mil DIP
PEEL18CV8PI-25 Industrial
PEEL18CV8J-25 Commercial
25 ns 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-25 Industrial
PEEL18CV8S-25 Commercial
25 ns 20-pin SOIC
PEEL18CV8SI-25 Industrial
PEEL18CV8T-25 Commercial
25 ns 20-pin TSSOP 170 mil
PEEL18CV8TI-25 Industrial

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Part Number

Device Suffix
PEEL18CV8 PI-25

Speed
–5 = 5ns tPD
Package –7 = 7.5ns tPD
P = 20-pin Plastic 300mil DIP –10 = 10ns tPD
J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC) –15 = 15ns tPD
S = 20-pin SOIC 300 mil Gullwing –25 = 25ns tPD
T = 20-pin TSSOP 170 mil
Temperature Range
(Blank) = Commercial 0 to +70°C
I = Industrial -40 to +85 °C

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