Developing Analytical Equations for Determining Power MOSFET Switching Transients

By Jess Brown Ph.D, Vishay Siliconix

Power Management DesignLine

(12/13/2004 10:34 AM EST)

This article explains the switching behavior of power MOSFETs in practical application circuits and show
reader/designer how to choose the right device for the application using the specifications typically provid
manufacturer datasheets. The article goes through several methods of assessing the switching performanc
power MOSFETs and compares these against practical results. The comparison shows that datasheet valu
be used to obtain a reasonable indication of the switching performance of a MOSFET as well as its switch
losses, but calculated switching transients will always be shorter than those actually achieved. Therefore,
maximum parameters from the datasheet should always be used to give realistic results.

Switching the MOSFET in isolation

Using capacitance
To get a fundamental understanding of the switching behavior of a MOSFET, it is best first to consider th
in isolation and without any external influences. Under these conditions, an equivalent circuit of the MOS
gate is illustrated in Figure 1, where the gate consists of an internal gate resistance (Rg
(Cgs and Cgd). With this simple equivalent circuit it is possible to obtain the output voltage response for a s
voltage.

Figure 1. An equivalent MOSFET gate circuit showing just Cgs, C

The voltage VGS is the actual voltage at the gate of the device, and it is this point that should be considered
analyzing the switching behavior of the device.

If a step input is applied at VGS_APP, then the following holds true:

(1)

(2)

(3) and since VDS is fixed

(4)

therefore:

(5) and

(6)

giving

(7)

(8)

@t=0, VGS =0, therefore

 (9)

This gives an indication of how long the actual gate voltage (VGS) takes to get to the threshold voltage.

When the MOSFET is considered with additional parasitics, it becomes increasingly difficult to manipula
equations manually for such a practical circuit. If these second-order, or parasitic, components are ignored
is possible to come up with formulas for the turn-on and turn-off time periods of the MOSFET. These are
in Equations 10 through to 15 and the resulting waveforms are shown in Figures 2 and 3
based on those developed by B J Baliga[1], where RG is the internal gate resistance, RG_APP
resistance, Vth is the MOSFET threshold voltage, and VGp is the gate plateau voltage.

[10]

[11]

[12]

VF is the voltage across the MOSFET when conducting full load current and VDS is the voltage across th
MOSFET when it is off.

This gives an accurate t1 and t2 when using datasheet values, but the time period t3 is difficult to calculat
Cgd changes with VDS.
 Figure 2. Turn-on transient of the MOSFET

Using the same principles for turn-off, the formulas for the switching transients are given below:

[13]

[14]

[15]

In this instance, t4 and t6 can be calculated accurately, but it is the formula for t5 which is more difficult to
since during this time period VDS will change, causing Cgs to also change. Therefore some method is requi
calculate t3 and t5 without using the dynamic Cgd.

Figure 3. Turn-off transient of the MOSFET

Using gate charge to determine switching time

Looking at the gate charge waveform[2] in Figure 4, Qgs is defined as the charge from the origin to the star
Miller Plateau (VGP); Qgd is defined as the charge from VGP to the end of the plateau; and Q
charge from the origin to the point on the curve at which the driving voltage VGS equals the actual gate vo
the device.
 Figure 4. Sketch showing breakdown of gate charge

The rise in VGS during t2 (Figure 2) is brought about by charging Cgs and Cgd. During this time V
change and as such Cgd and Cds stay relatively constant, since they vary as a function of V
generally larger than Cgd and therefore the majority of drive current flows into Cgs rather than into C
current, through Cgd and Cds, depends on the time derivative of the product of the capacitance and its volta
gate charge can therefore be assumed to be Qgs.

The next part of the waveform is the Miller Plateau. It is generally accepted that the point at which the ga
charge figure goes into the plateau region coincides with the peak value of the peak current. However, the
the gate charge actually depends on the product1 (CgdVGD) with respect to time. This means if there is a sm
value of drain current and large value of output impedance, then IDS can actually reach its maximum valu
the left knee occurs. However, it can be assumed that the maximum value of the current will be close to th
point and throughout this application note it is assumed that the gate voltage at the knee point corresponds
load current, IDS.

The slope of the Miller Plateau is generally shown to have a zero, or a near-zero slope, but this gradient d
on the division of drive current between Cgd and Cgs. If the slope is non-zero then some of the drive curren
flowing into Cgs. If the slope is zero then all the drive current is flowing into Cgd. This happens if the C
product increases very quickly and all the drive current is being used to accommodate the change in volta
across Cgd. As such, Qgd is the charge injected into the gate during the time the device is in the Miller Plate

It should be noted that once the plateau is finished (when VDS reaches its on-state value), C
again and the bulk of the current flows into Cgs again. The gradient is not as steep as it was in the first per
because Cgd is much larger and closer in magnitude to that of Cgs.

Combination of gate charge and capacitance to obtain switching times

The objective of this note is to use datasheet values to predict the switching times of the MOSFET and he
allow the estimation of switching losses. Since it is the time from the end of t1 to the end of t
on loss, it is necessary to obtain this time (Figure 2). Combining 10 and 11 it is possible to obtain the rise
the current (tir=t2-t1) and because VDS stays constant during this time then it is possible to use the specified
datasheet value of Ciss at the appropriate VDS value. Assuming the transfer characteristic is constant, then V
be substituted for Vth + IDS/gfs, hence:
 [16]

It is difficult to use a value of Cgd for the fall time period of VDS (tvf=t3). Therefore if the data sheet value o
charge is used (Qgd_d) and divided by the voltage swing seen on the drain connection (V
effectively gives a value for Cgd based on the datasheet transient.

[17]

Similarly for the turn-off transition, the voltage rise time (tvr=t5) is:

[18] and the current fall time (tif=t6) is:

[19]

Comparing equations with datasheet values

The definition of the turn-on and turn-off times given in the datasheet can be seen in Figure 5
can be equated to the equations described above and are shown here:

[20]

[21]

[22]

[23]
Figure 5. Sketch showing definition of turn-on and turn-off times

Calculations Min Typical Max

Rg 0.6 0.8 1 Ω
Rg_app 5.4 6 6.6 Ω
Ciss@Vds 620 775 930 pF
Ciss@0V 880 1100 1320 pF
gfs 21.6 27 32.4 S
VGS_APP 9 10 11 V
Vth 0.8 1.4 1.8 V
IDS 0.9 1 1.1 A
Qgd_d 2.8 3.5 4.2 nC
VDS_D 13.5 15 16.5 V
IDS_D 11.2 12.4 13.6 A
rDS(on) 0.008 0.01 0.012 Ω
VF 0.0072 0.01 0.0132 V
VF_D 0.09 0.12 0.16 V
VDS 13.5 15 16.5 V
t1 (Eqn 10) 0.28 0.79 1.6 ns
tir (Eqn 16) 0.01 0.02 0.05 ns
tvf (Eqn 17) 1.4 2.8 5.5 ns
t4 (Eqn 13) 8.4 14.5 26.0 ns
tvr (Eqn 18) 7.5 16.7 47.7 ns
tif (Eqn 19) 0.06 0.14 0.44 ns
td(on) 0.29 0.81 1.7 ns
tr 1.4 2.8 5.5 ns
td(off) 8.4 14.5 26 ns
tf 7.5 16.7 47.7 ns
Datasheet
td(on) 10 20 ns
 tr 11 20 ns
td(off) 24 50 ns
tf 10 20 ns

Table 1. Worked example for switching transients: Si4892DY

The minimum switching transients were calculated using the appropriate value of the parameters, which r
in producing the shortest switching transient value. In some circumstances this meant that the maximum v
a parameter was used to calculate the minimum switching transient and vice versa for the maximum switc
transients.

Comparing equations with measured switching transients

The datasheet switching transients are measured with a resistive load and are not truly representative of a
practical circuit. As such the device will not behave according to the ideal operation described above. The
actual switching waveforms were measured, and these are shown in Figures 6 and 7. These switching tra
are for the Si4892DY implemented on the high side of a buck converter configuration. The circuit parame
were: VDS = 5V, IDS = 5 A, VGS_APP = 5 V, and Rg_app = 10Ω

Figure 6. Measured current and voltage turn-on switching transient

Figure 7. Measured current and voltage turn-off switching transient

Calculations Min Typical Max

tir (Eqn 16) 0.18 0.44 1.1 ns
tvf (Eqn 17) 1.6 3.7 8.4 ns
 tvr (Eqn 18) 3.5 7.9 22 ns
tif (Eqn 19) 0.95 1.0 1.5 ns
Measured
tir 16 20 24 ns
tvf 8.8 11 13.2 ns
tvr 10.4 13 15.6 ns
tif 28 35 42 ns

Table 2. Measured versus calculated

Limitations of the driving circuit

Table 2 shows the comparison between the calculations and the measured transients. It can be seen that th
voltage transients are relatively close. However, the switching times of the MOSFET are affected not only
parasitic elements, but also by the driving circuit. Under the conditions described above, the author has as
that the gate circuit does not limit the switching performance of the power MOSFET. For example, with a
MOSFET p-channel and n-channel driver, it is possible that the theoretical current into the gate will be lar
than that which the driver is able to supply. There are several ways in which a MOSFET driver can be rea
and this goes beyond the study of this application note. The formulas described in the text are used to gau
switching times and therefore estimate the switching losses without navigating complex formulas, models
expensive simulation software. The major discrepancy is between the calculated and actual current transie
These calculations are an order of magnitude less than the actual transients. Therefore, further considerati
to be taken for the current rise and fall times and this is described below.

Current transients
The discrepancy between the calculated and the measured occurs because the calculations assume an idea
situation. One major parameter that can be considered into the equations is the package inductance of the
MOSFET. This will slow the current transient and can be taken into account with relative ease if a few
assumptions are made.

Since the load current will generally be much larger than the gate current, it is assumed that all the curren
through the package inductance will be IDS. Therefore it can be shown that the voltage across the packag
inductance of the MOSFET during turn-on will be:

[24]

This is the voltage that occurs from the current transient and as such subtracts from the gate voltage and h
slows down the current transient. If Equation 24 is subtracted from VGS and solved for t, the tir transient

[25]
Applying the same principle for tif results in a current transient as follows:

[26]

Calculations Min Typical Max

tir (Eqn 25) 4.7 8.1 13.2 ns
tvf (Eqn 17) 1.6 3.7 8.4 ns
tvr (Eqn 18) 3.5  7.9  22  ns 
tif (Eqn 26) 8.1  17.9  32.8  ns 
Measured        
tir   16  20  24  ns 
tvf   8.8  11  13.2  ns 
tvr   10.4  13  15.6  ns 
tif   28  35  42  ns 

Table 3. Measured versus calculated with package inductance

Conclusion
The rise and fall times for power MOSFETs can be approximated with relative ease when evaluated in iso
By plugging in datasheet values into the formulas derived above, we can get a reasonable indication of the
switching performance of the MOSFET as well as the switching losses. However, since second order para
are not included the analytical equations will always be shorter than those actually achieved. Hence the m
parameters from the datasheet should always be used to give realistic results.

Author Information
Dr. Jess Brown is DC/DC Applications Manager at Vishay Siliconix. Before joining the company, he spen
previous eight years in power electronics research. His areas of expertise include switchmode power supp
applications, brushless ac and dc three-phase permanent magnet motor drives, and power loss measurem
2004, he delivered papers at Power Systems World (Chicago), PCIM Europe, and APEC. He holds a Bac
Engineering degree and a Doctor of Philosophy (Ph.D) in Power Electronics. He is a Chartered Member
Institute of Electrical Engineers (MIEE, CEng).

References
[1]. B J Baliga, Power Semiconductor Devices.
[2]. Gate Charge Principles and Usage, Power Electronics Europe, Issue 3 2002, Technology