Performance of a DC/AC/DC VSC System

to Interconnect HVDC Systems

T Lüth*, M M C Merlin*, T C Green*,
C D Barker†, F Hassan†, R W Critchley†, R W Crookes†, K Dyke†

*Imperial College London, UK, {thomas.luth06, michael.merlin07, t.green}@ic.ac.uk, †Alstom grid, UK, {carl.barker,
fainan.hassan}@alstom.com

Keywords: HVDC, VSC, DC/DC conversion, fault isolation, demand for DC/DC converters in the MW application range
multi-level converter. so far.
Another approach to achieving a DC to DC conversion is the
Abstract “front-to-front” connection of two AC/DC Voltage Source
Interconnection of High Voltage Direct Current (HVDC) Converters (VSC) forming an internal AC-link. This is
links into networks is key to a future HVDC grid spanning illustrated in Figure 1 and was proposed in [4]. An advantage
large regions. Various factors including the evolution of cable of this design is that existing and standard VSC technologies
technology will lead to a variety of DC voltages and a need to that have been proven for the megawatt and kilovolt ranges,
provide a DC/DC step up/down at high power ratings (beyond can be used. The AC/DC converters could be of any topology
but the low switching loss of modular multi-level designs are
ͷͲͲ‫)ܹܯ‬. This paper analyses a High Voltage (HV) DC/DC
attractive. An example is the so-called ‘Alternate Arm
converter utilising an intermediate AC link between two
modular multi-level converters (MMC) based on the Converter’ (AAC) [5,6]. This converter is an alternative to the
MMC [7]. The AAC however allows for smaller cell stacks,
Alternate Arm Converter (AAC) topology. System operation
reducing footprint, as the AC voltage for each converter phase
is demonstrated using a detailed Simulink simulation. Power
leg is only generated by one arm for each half-cycle. The
loss estimates derived from the simulation are used to
other arm is disconnected by use of series connected Director
illustrate the dependence of efficiency on design choices and
Switches (DS) during this time. Current is commutated
operating point. Furthermore, the system is shown to block a
between the alternate arms at the end of each half-cycle.
DC-side fault and prevent its affect propagation through the
system.

1 Introduction
The utilisation of offshore wind and the growing electrical
interconnection of the countries surrounding the North Sea
have provoked much interest in voltage source HVDC
transmission and the possible interconnection of DC point-to-
point connections into multi-terminal systems. It becomes Figure 1: Front-to-front connection of two DC/AC VSCs.
apparent that some connections will require DC to DC
conversion where links built with different generations of 2 Schematic and Principles
cable technology are rated and operated at different voltages.
Technological development continues to raise link voltage 2.1 Operating principles
further. The absence of a standard transmission voltage is one
impediment to the interconnection of DC systems [1]. The proposed ‘front-to-front’ topology utilises an AC
Further, DC to DC conversion may be required as part of intermediate conversion step to provide an interconnection
future wind farm interfaces and even as a separation device in between two different DC voltage levels. Using AACs we
networks [2]. propose to connect both DC links to a shared AC connection.
Each phase of an AAC consists of director switches and two
DC/DC conversion is a well studied area for low voltage stacks of cells, one per arm as shown in Figure 2, which are
applications with a range of topologies to suit different used to generate the AC voltage waveforms and control the
voltage step ratios and power ratings. Such designs, however, converter currents. As shown in the schematic (Figure 2), the
do not lend themselves very well to scaling to typical HVDC cells used in the arms can be of either the half- or full-bridge
voltage levels due to a range of voltage stress problems and type. The choice of bridge depends on the AC voltage relative
inefficient use of the semiconductor’s power ratings, as to the respective DC link voltage.
discussed in [3]. One proposition for HV DC/DC conversion
is a resonant DC/DC converter using thyristor valves [3]. To
date no dominant topology has yet emerged because of little

1
 Figure 2: Schematic of DC/AC/DC system using AACs.

The cell stack can be controlled to generate a voltage which ߨܸ෠஺஼ ‫ܫ‬መ஺஼
either subtracts from (both half- and full bridges) or adds to ‫ܧ‬஺஼ ൌ …‘•ሺȰ஺஼ ሻ
ʹ߱଴
the DC link voltage (only full bridges) as seen from the AC
terminal. Each AAC has an operating point, so called ‘sweet- Equation 2: Energy transferred to cell stack per cycle from
spot’, at which each stack experiences a Zero Net Energy AC side.
(ZNE) exchange. The sweet-spot is at the optimal AC voltage Furthermore the energy exchange between the cell stacks and
defined by Equation 1. the DC link is dictated by the DC link voltage and the AC
ʹܸ஽஼ current, shown in Equation 3.
ܸ෠஺஼௢௣௧௜௠௔௟ ൌ
ߨ ܸ஽஼ ‫ܫ‬መ஺஼
Equation 1: Optimal AC voltage for AAC sweet-spot ‫ܧ‬஽஼ ൌ …‘•ሺȰ஺஼ ሻ
߱଴
When operating at the sweet-spot, an AAC will have to over- Equation 3: Energy transferred per cycle out of cell stack to
modulate, meaning that the peak AC voltage is higher than DC link.
half the DC link voltage. Thus the cell stack in each arm has
to have positive and negative voltage generating capabilities. At the aforementioned sweet-spot ‫ܧ‬஺஼ ൌ ‫ܧ‬஽஼ . At all other
This in turn requires the use of full-bridge cells. Neither AAC operating points however there exists an energy imbalance in
is restricted to the use of one or the other type of cell. each cell stack which has to be counteracted to maintain the
voltages of the cell capacitors.
We chose to investigate a conventional three-phase
arrangement for the AC-link, but the number of phases is not One energy balancing technique, which has previously been
restricted to this. Rather it is a design trade-off between the employed with the AAC, is the introduction of an overlap
device number and their necessary space and investment current [6]. To accomplish this, the arm inductances are used
requirements, which is of particular relevance for off-shore to control a DC current flowing through both arms of the
applications. same AAC to exchange energy between the stacks and the
DC link. For this to occur an overlap period is defined during
2.2 Energy Balance which both Director Switches are closed.

The energy exchange between an AAC and the AC-link is 2.3 AC Link Parameters
dictated by the AC current and voltage as given by Equation 2
(Ȱ஺஼ is the angle of the AC current with respect to the Because the AC-link is exclusively internal to the DC/DC
voltage). converter, there are no relevant grid codes that must be

2
applied. Thus the AC voltage magnitude and frequency can ܸ஽஼ Ȱ௢௩௘௥௟௔௣
෡௦௧௔௖௞ ൌ
ܷ ൅ ܸ෠஺஼ ‫ ‹• ڄ‬൬ ൰
be varied to suit the implementation. Using the AC voltage ʹ ʹ
level we can trade-off a lower AC current magnitude against a
Equation 4: maximum under-modulation voltage to be
larger stack size to support a higher AC voltage. Furthermore,
generated by stack.
we can choose the voltage to achieve an operating point at
which the energy imbalance and the losses associated with the If the AC voltage has a peak magnitude of greater than that of
balancing currents are optimised. half the DC connection voltage, the stack will also have to be
able to over-modulate. Extra cells for this however are only
A higher AC voltage implies a lower current magnitude for a
required if the maximum over-modulation voltage, as given in
given power transfer. This is advantageous for the conduction
Equation 5, is greater than the maximum under-modulation
losses as they increase quadratically with current magnitude.
voltage.
In addition, the energy imbalance experienced by the cell
stacks each cycle is affected by the AC voltage. The ܸ஽஼
෡௦௧௔௖௞ைெ ൌ ܸ෠஺஼ െ
ܷ 
necessary balancing current magnitudes can thus be ʹ
influenced. Owing to the nature of the conduction losses, it
Equation 5: maximum over-modulation voltage required of
may be advantageous to share the energy imbalance burden
stacks.
between both AACs rather than operate at a sweet-spot of
either AAC. Each director switch contains a number of series-connected
IGBTs which are each rated at a nominal steady-state voltage
The AC frequency can be adjusted to trade-off between
stress of ͳǤͺܸ݇. The maximum blocking voltage of the
switching losses and passive component sizing. Increasing the
director switch is given in Equation 6.
frequency allows the cell level capacitance to be reduced
whilst keeping the same voltage fluctuation. It also allows for Ȱ
෡ௗ௜௥௘௖௧௢௥ ൌ ܸ෠஺஼ ‫ ڄ‬൬ͳ െ •‹ ൬ ௢௩௘௥௟௔௣ ൰൰
ܷ
significantly reduced arm and phase inductance ratings ʹ
thereby reducing the capital cost. Such reductions might be
very desirable for applications where physical space is a Equation 6: Maximum director switch blocking voltage.
restricting factor, such as on an off-shore platform. In this paper we show results for an AC peak voltage of
ʹͷܸ݇ and the corresponding stack parameters can be found
3 Simulation in Table 1.

3.1 Model parameters AAC ࡺ࢕ cells Cell type ࡺ࢕ IGBT in DS

A simulation model has been developed in Simulink to verify
HV1 side 19 Half-bridge 10
the operation and control of the system. Although this
converter topology is suitable for very high voltage
HV2 side 14 Full-bridge 10
applications in the hundreds of kilovolts, the model was made
for significantly lower voltages to keep the model complexity
(principally the number of cells) low to allow a reasonable Table 1: Cell stack and director switch parameters per arm of
simulation time. The model parameters are listed below: simulated system for ܸ෠஺஼ ൌ ʹͷܸ݇.

 ±30 MW power transfer capability 3.2 Control Structure

 HV1 DC link voltage: ±25 kV
 HV2 DC link voltage: ±15 kV The controller is an extension to the previously developed
 DC/DC step ratio: 1.67 control method for the stand-alone AAC [6] and is shown in
 Phase inductance: 0.2 PU Figure 3. Current references for all system currents are
 Arm inductance: 0.02 PU combined with relevant overlap current reference magnitudes
 Cell capacitance: 7mF at 1.8 kV in the top level controller.
 Overlap period: ʹߨൗͻ ‫݀ܽݎ‬ The difference of these current references compared to the
measured currents are used in a proportional plus resonant
The number of cells in each arm stack is dependent on the DC (P+R) compensator to provide a set of voltages as a reference
voltage and activation angle settings as well as the overlap vector, ܸ௃ [8].These voltages control the system currents and
angle. A larger overlap angle will require each arm to support are combined with the AC voltage reference in the
the AC voltage for a longer period. Similarly each stack has intermediate level controller to form a desired voltage
to support at least half of the DC link voltage to generate the waveform at the AC-side of each AAC, (at the converter side
zero crossing of the AC voltage. of the phase interface inductor) This voltage is translated into
The equation for the maximum under-modulation stack an equivalent set of cell voltage commands for each cell of an
voltage is provided in Equation 4. arm in the low level controller. A cell rotation algorithm
ensures that all cells are used equally to prevent any one cell
from experiencing extreme voltage deviations.

3
 required to over-modulate and thus requires full-bridge cells.
The two AACs experience energy imbalances of similar size.
3 Phase AC Currents
1000

Current [A]
0

-1000
0.4 0.405 0.41 0.415 0.42 0.425 0.43
3 Phase AC Voltages (HV AAC side)

20

Voltage [kV]
0

-20
0.4 0.405 0.41 0.415 0.42 0.425 0.43
HV DC Link Currents (unfiltered)

1000
Figure 3: Control Structure of entire system. Current [A]

0
3.3 Normal Operation
-1000
The system was tested under normal operation to verify its
ability to transfer power in either direction and maintain 0.4 0.405 0.41 0.415 0.42 0.425 0.43

nominal cell capacitor voltages. The results in Figure 4 show LV DC Link Currents (unfiltered)
the AC voltages and currents as well as the unfiltered DC link 1000
currents for a peak AC voltage of ʹͷܸ݇. The harmonic
Current [A]

distortions seen in the link currents are a typical feature of the 0

AAC.
At ܸ෠஺஼ ൌ ʹͷܸ݇ both AACs require overlap currents to -1000

maintain the energy balance in the cells. The HV1 side AAC 0.4 0.405 0.41 0.415 0.42 0.425 0.43
Time [s]
requires around െʹͷͲ‫ ܣ‬and the HV2 side AAC around
െ͵ͷͲ‫ܣ‬. The peaks and troughs seen in the link currents, Figure 4: Voltage and current waveforms of system under
Figure 4, at six times fundamental frequency are largely the normal operation at ܸ෠஺஼ ൌ ʹͷܸ݇ and ͵Ͳ‫ ܹܯ‬power
results of these balancing currents. transfer (from HV1 to HV2 side).

3.4 Electrical Losses Loss Category ࢌ࡭࡯ ൌ ૞૙ Hz ࢌ࡭࡯ ൌ ૞૙૙ Hz

HV1 AAC [kW] 152.8 362.6
As this topology essentially entails two conversion steps, Conduction Loss 129.2 126.0
power losses may become a problem. At an AC frequency of Switching Loss 23.6 236.7
ͷͲ‫ݖܪ‬, the conduction losses in the cells and director switches HV2 AAC [kW] 219.9 577.8
are dominant. They are heavily affected by two factors: the Conduction Loss 181.4 181.3
number of devices in the conduction path and the magnitude Switching Loss 38.5 396.5
of the current that flows through them. Total Losses [kW] 372.7 940.4
A full-bridge has an additional IGBT in the conduction path System Efficiency (%) 98.8 96.9
compared to a half-bridge cell. Thus an AC voltage that
Table 2: Semiconductor loss breakdown from Simulink
requires neither or only one of the AACs to over-modulate
(and thus require full-bridge cells) can be advantageous. simulation for system operated at ܸ෠஺஼ ൌ ʹͷܸ݇.
These voltages are different for each AAC due to the different A breakdown of the losses is given in Table 2 using post-
DC voltages which may lead to different choices in the two processing of the time-domain simulation to calculate power
converters. The different DC voltages means that some losses. The post-processing algorithms review the switching
energy balancing will always have to take place. of the cells to determine what kind of switching losses were
An AC peak voltage of ʹͷܸ݇ has been found to yield the incurred. Current and voltage samples are used to calculate
lowest losses for the DC voltages of 15 kV and 25 kV used in switching energy losses in individual devices using equations
this study. This is the highest voltage at which the HV1 side derived from the manufacturer’s data-sheet (based on
can operate with half-bridge cells. The HV2 side AAC is Toshiba’s MG1200FXF1US53 module). Results are shown
for two AC frequencies. The switching losses can be seen to

4
scale linearly with AC frequency. This intuitively makes match closely with an error of ͹ǤͷΨ for ͷͲ‫ ݖܪ‬and ͳʹǤʹΨ
sense as the switching of cells is dominated by the generation for ͷͲͲ‫ݖܪ‬. The switching losses are overestimated because
of the step-wave approximation of the sine wave with some of simplifying assumptions about the overlap current control
additional commutation for control of the balancing current switching frequency. Also the switching events due to the cell
and to provide cell rotation. The cell rotation frequency rotations are difficult to predict accurately and are thus over-
cannot be lowered with higher AC frequency as a minimum estimated in the analytical method. This is most notable at
number of cell rotations are required per AC cycle to maintain higher AC frequencies where the switching losses dominate
the cell voltages. due to a higher switching frequency.
LV DC Link Currents (unfiltered)
3.5 DC Side Fault Response
1,000
During a fault on one of the DC connections, the system

Current [A]
works to prevent the fault current from travelling through the 0
system and affecting the other DC connection. This is done
by effectively shutting down the AC-link, keeping control of -1,000
the AC currents, and opening the Director Switches on the 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
unaffected side as soon as the arm currents have been HV DC Link Currents (unfiltered)
regulated down to an acceptable level.
1000
Following fault detection, the AC current reference is set to
zero and all energy balancing mechanisms are disabled until Current [A] 0
the fault is cleared. The latter is done as there cannot be an
energy exchange between the stacks and the DC connection if -1000
the link voltage has collapsed. The non-faulty side’s energy 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
balancing is also disabled to help keep the AC side stable and 3 Phase AC Currents
switched off. In the simulation a detection time of ͷ݉‫ ݏ‬and a 1000
fault clearance time of ͳͺͲ݉‫ ݏ‬is assumed. At ͲǤʹ‫ ݏ‬the HV2
Current [A]

DC link voltage is shorted to ground (Ͳܸ݇) and is only

0
brought back to its original voltage after the fault is cleared.
The resulting DC and AC link currents can be seen in Figure
-1000
5 in the top three graphs. The controller always keeps the AC 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
side under control as the stack commands are calculated using Valve voltage range of one arm in LV side AAC
live DC side voltage measurements. This prevents the 2000
currents from running away before the fault is detected as the mean min. max.
Voltage [V]

cell stacks work to follow the currents references.

1800
The maximum, mean and minimum of the cell voltages of
one typical cell stack are shown in the bottom graph in Figure
5. To avoid a large unbalance between the cells, the current is 1600
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
slowly ramped up (over ͳͲͲ݉‫ )ݏ‬after the fault is cleared (at Time [s]
ͲǤ͵ͺ‫ )ݏ‬and a short zero current-reference pause (for ͲǤʹ‫)ݏ‬.
Figure 5: Current and cell voltage waveforms of system under
The reference pause was added to allow the stacks to be
equally balanced before the power was ramped up again. HV2 side DC fault condition at ܸ෠஺஼ ൌ ʹͷܸ݇ and ͵Ͳ‫ܹܯ‬
power transfer (from HV1 to HV2 side).
4 Scaled up system Loss Category ࢌ࡭࡯ ൌ ૞૙ Hz ࢌ࡭࡯ ൌ ૞૙૙ Hz
HV1 AAC [kW] 154.8 365.3
To investigate the losses of a full-scale system, an analytical Conduction Loss 127.1 127.1
loss model was developed and verified against the Simulink Switching Loss 27.7 238.2
loss results for the smaller system. The model is based upon HV2 AAC [kW] 246.1 689.5
estimating the number and type of switching events that Conduction Loss 181.2 181.2
would typically occur over one AC cycle in a converter arm. Switching Loss 64.9 508.3
Loss curves with respect to the current magnitude, derived Total Losses [kW] 400.9 1054.8
from the datasheet of the switching devices, are used to
System Efficiency (%) 98.7 96.5
calculate the energy lost in each switching event and to
provide conduction loss profiles. Table 3: Semiconductor loss breakdown from analytical loss
To verify this method the same scaled down system estimation for system operated at ܸ෠஺஼ ൌ ʹͷܸ݇.
previously presented was analysed using the analytical The analytical model was used to estimate the semiconductor
method. The loss results are shown in Table 3 and should be losses of a full-scale system operating at ʹͲ times the DC
compared with those in Table 2. It can be seen that the results connection voltages of the system modelled in Simulink.

5
Such a system was not built in Simulink as the cell stacks suggesting it may be a feasible option for the interconnection
become prohibitively large (Table 4) to simulate effectively of HVDC system. Further work will also investigate different
using a detailed model. application areas of this circuit with varying step-ratios.
AAC ࡺ࢕ Cells Cell type ࡺ࢕ IGBT in DS
6 Acknowledgement
HV1side 373 Half-bridge 183
HV2 side 262 Full-bridge 183 The authors gratefully acknowledge the permission from
Alstom Grid to publish this paper and the financial support
Table 4: Cell stack and director switch parameters per arm of
provided by them. The authors also acknowledge the support
scaled up system for ܸ෠஺஼ ൌ ͷͲͲܸ݇.
of the EPSRC (www.epsrc.ac.uk) under grant number
Loss Category ࢌ࡭࡯ ൌ ૞૙ Hz ࢌ࡭࡯ ൌ ૞૙૙ Hz EP/G066477/1 for some of the analytical work on which this
HV1 AAC [MW] 2.754 5.526 study was based.
Conduction Loss 2.442 2.442
Switching Loss 0.312 3.084 References
HV2 AAC [MW] 4.090 10.412
Conduction Loss 3.372 3.372 [1] D. Jovcic, D. van Hertem, K. Linden, J.P. Taisne, W.
Switching Loss 0.718 7.040 Grieshaber. “Feasibility of DC Transmission Networks”,
Total Losses [MW] 6.844 15.938 International Conference and Exhibition on Innovative
System Efficiency (%) 98.9 97.4 Smart Grid Technologies (ISGT Europe), 2nd IEEE
PES,(2011)
Table 5: Analytical semiconductor losses for scaled up system
[2] D. van Hertem, M. Ghandhari, M. Delimar. „Technical
at ܸ෠஺௖ ൌ ͷͲͲܸ݇.
Limitations Towards a Supergrid, a European
The losses shown in Table 5 are for a system with the Prospective”, Energy Conference and Exhibition
following parameters: (EnergyCon), IEEE International, (2010)
 +600 MW power transfer capability [3] D. Jovcic. “Bidirectional, High-Power DC
 HV1 DC link voltage: ±500 kV Transformer”, IEEE Transactions on Power Delivery,
 HV2 DC link voltage: ±300 kV 24, (4), pp. 2276-2283 (2009)
 DC/DC step ratio: 1.67 [4] C.D. Barker, C.C. Davidson, D.R. Trainer, R.S.
 Phase inductance: 0.2 PU Whitehouse. “Requirements of DC-DC Converters to
 Arm inductance: 0.02 PU facilitate large DC Grids”, Cigre, SC B4 HVDC and
 Cell Capacitance: 7mF at 1.8 kV Power Electronics, (2012)
 Overlap period: ʹߨൗͻ ‫݀ܽݎ‬ [5] D.R. Trainer, C.C. Davidson, C.D.M. Oates, N.M.
 ܸ෠஺஼ ൌ ͷͲͲܸ݇ Macleod, D.R. Critchley, R.W. Crookes. “A new Hybrid
Voltage-Sourced Converter for HVDC Power
5 Conclusion Transmission”, Cigre, B4-111, HVDC and Power
Electronics, (2010)
This paper has introduced an HV DC/AC/DC system suitable
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nominal DC voltages. A scaled-down sample system was Trainer, D.R. Critchley, R.W. Crookes. “A New Hybrid
modelled in Simulink to test its operation under normal and Multi-Level Voltage-Source Converter with DC Fault
DC-side fault conditions. The importance of a carefully Blocking Capability”, 9th IET International Conference
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the system’s efficiency. The system is also capable of [7] A. Lesnicar, R. Marquardt. “An Innovative Modular
preventing the affects of a DC side pole-to-pole fault from Multilevel Converter Topology Suitable for a Wide
spreading to the other DC link. Power Range”, Power Tech Conference Proceedings,
Furthermore, a scaled-down Simulink model was used to IEEE Bologna, (2003)
verify the accuracy of an analytical loss model for full scale [8] R. Theodorescu, F. Blaabjerg, M. Liserre, P.C. Loh,
systems. The error between the two approaches was ͹ǤͷΨ at “Proportional-resonant controllers and filters for grid-
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switching losses in the analytical method has been identified – Electric Power Applications, 153, pp. 750-762, (2006)
as a main source for the error. Further work will aim to fix
this and reduce the error of the analytical method, particularly
at higher AC frequencies to improve the accuracy of loss
estimates for to scale systems.
The analytical model shows that such a system for a step ratio
of ͷǣ ͵ can be operated with an efficiency of ͻͺǤ͹Ψ at ͷͲ‫ݖܪ‬