Binary Arithmetic and Arithmetic Circuits-2

Lesson: Binary Arithmetic and Arithmetic Circuits-2

Lesson Developer: Dr. Divya Haridas

College/ Department: Keshav Mahavidyalaya,

University of Delhi

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Arithmetic Circuits-2
Table of Contents

Chapter 2 Arithmetic Circuits

2.1 Chapters Objective
2.2 Introduction
2.3 Arithmetic Circuits
2.4 Adder
2.4.1 Half Adder
2.4.2 Full Adder
2.5 Subtractor
2.5.1 Half Subtractor
2.5.2 Full Subtractor
2.6 Adder/Subtractor
2.6.1 4 bit parallel Adder/Subtractor
2.7 Summary
2.8 Exercises
2.8.1 Subjective Questions
2.8.2 Fill in the Blanks
2.8.3 Multiple Choice Questions
2.9 Glossary
2.10 References

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2.1 Chapter Objectives

 Introduction to combinational logic circuits.
 Design Half adder and understand it’s working.
 Design Full adder and to understand it’s working. To implement Binary addition using
Full adder
 Design Half Subtractor and understand it’s working.
 Design Full Subtractor and to understand it’s working. To implement Binary
Subtraction using Full Subtractor.
 Use full adders to implement four bit adder/subtractor

2.2 Introduction

Logic circuits in digital systems are broadly classified as A) Combinational logic circuits B)
Sequential logic circuits. A combinational circuit is one whose output at any time is
determined from the present combination of inputs whereas the outputs of sequential
circuits at any time depend not only on present value of inputs but also on the past inputs.
Arithmetic circuits are the examples of combinational circuits.

I/P Combinational O/P I/P Sequential Circuits O/P

circuits

Feedback

Figure 1: Block diagram of combinational and sequential circuits

2.3 Arithmetic circuits

Arithmetic circuits are the circuits that perform arithmetic operations such as addition and
subtraction, examples of arithmetic circuit are adders and subtractors. Adders are important
in digital systems in which numerical data are processed. In this section adders, subtractor
and adder/subtractor are introduced.

2.4 Adder

2.4.1 Half Adder

The half adder accepts two binary digits on its input and provides two binary digits on its
outputs, a sum bit and a carry bit. The logic symbol of half adder is given in figure 2.

A Σ Sum
Input bits Output bits
B Cout Carry

Figure 2: Logic symbol of Half Adder

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The truth table for half adder is given as

A B Cout Σ
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Σ Sum
Cout=Carry
A & B are the input variables

Tip to memorize
Whenever odd number of 1 is present in truth table then sum will be high.
When both inputs are 1 then only carry will be high.

From the above truth table the Boolean expression for sum and carry are

S  AB  AB  A  B
C  AB
A half adder can therefore be realized by using one X-OR gate (for sum operation) and one
AND gate (for carry operation). The logic circuit for half adder is shown in figure 3

Figure 3: Circuit diagram of Half Adder

The logic circuit for half adder can be implemented using only NAND gates and is shown in
figure 4

Figure 4: Circuit diagram for half adder implemented using NAND gates only

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The Boolean expression for sum and carry is given as:

Sum  A AB  B AB
 A  AB  B  AB
 A  ( A  B)  B  ( A  B)
 A A  AB  B A  B B
 AB  AB

Carry  AB  AB

Try yourself

Draw logic circuit for half adder using only NOR gates only.

Solution:

2.4.2 Full Adder

A half adder has only two inputs and there is no provision to add a carry coming from the
lower bits even in the case of 4 bit addition operation. For this another circuit is required
which can add three bits simultaneously. A full adder is a combinational logic circuit that
performs the arithmetic addition of three input bits. The full adder accepts two input bits
and input carry and generates a sum output and an output carry. So a full adder has three
inputs and two outputs. The logic symbol of full adder is given in figure 5

Input bits A Σ Sum

B Output bits
Input Carry Cin Cout Carry

Figure 5: Logic symbol of full adder

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Two of the input variables denoted by A and B represent the two significant bits to be
added. The third input Cin represents the carry from the previous lower significant position.
Table 2 shows the truth table for a full adder.

A B Cin Cout Σ
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Σ Sum
Cin=Input Carry
Cout=Output Carry
A, B & Cin are the input variables

Tip to memorize
When the number of 1’s in truth table is odd then the output for sum would be high. i.e it will follow a three
input XOR gate function. Whenever the number of 1’s in truth table appear more than once, then carry will be
high.
When both inputs are 1 then only carry will be high.

Karnaugh Map simplification for Full Adder

Karnaugh Map for Sum

C C

0 1
AB

AB 1 0

AB 0 1

1 0
AB

Boolean expression for sum = ABC  ABC  ABC  ABC

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Karnaugh Map for Carry

C C

AB 0 0

AB 1
0

1
AB 1

AB 0 1

Boolean expression for Carry = AB  BC  AC

From the above Boolean expression we can design the logic circuit for full adder. Students
are advised to first design the circuit on their own and then verify their results. Figure 6
shows the simplified circuit diagram of Full adder

Figure 6: Logic circuit for Full adder

Full adder can also be designed using two half adders. Logic circuit of Full adder using two
half adders is given in figure 7

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Figure 7: Logic circuit of Full adder using two half adders

Complete logic circuit of figure 7 is given in figure 8.

Figure 8: Complete logic circuit of Full adder using two half adders

The sum output of the first half adder is the exclusive OR (X-OR) of two input variables
A  B . This output is fed as input for the second half adder. The second input variable for
the second half adder is Cin (carry input). Therefore this input carry Cin must be exclusive
ORed with A  B , yielding the equation for the sum

Sum,   A  B  Cin
   
 AB  AB Cin  AB  AB C in
  
 A  B  A  B Cin  ABC in  ABC in

 
 AB  AB Cin  ABC in  ABC in
 ABC in  ABCin  ABC in  ABC in

The output carry is a 1 when both inputs to the first XOR gate are 1s or when both inputs to
the second XOR gate are 1s. The output carry of the full adder is therefore produced by the
inputs A ANDed with B and A  B ANDed with Cin. These two terms are ORed and the
expression is given as

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COut  AB   A  B Cin

 AB  AB  AB Cin 
 AB  ABC in  ABCin
 
 A B  BCin  ABC in
 AB  Cin   ABC in
 AB  AC in  ABC in

 AB  A  AB Cin 
 AB   A  B Cin
 AB  AC in  BC in

Try Yourself

Design Full Adder using universal NAND gate only.

Design Full Adder using universal NOR gate only.

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Value Addition
More complex adders
Ripple-carry adder

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each
full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called
a ripple-carry adder, since each carry bit "ripples" to the next full adder. The first (and only
the first) full adder may be replaced by a half adder (under the assumption that Cin = 0).

The layout of a ripple-carry adder is simple, which allows for fast design time; however, the
ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be
calculated from the previous full adder.

Carry-lookahead adder

4-bit adder with carry look ahead

A carry-look ahead adder (CLA) is a type of adder used in digital logic. A carry-look
ahead adder improves speed by reducing the amount of time required to determine carry
bits. It can be constructed with the simpler, but usually slower, ripple carry adder for which
the carry bit is calculated alongside the sum bit, and each bit must wait until the previous
carry has been calculated to begin calculating its own result and carry bits. The carry-look
ahead adder calculates one or more carry bits before the sum, which reduces the wait time
to calculate the result of the larger value bits. The Kogge-Stone adder and Brent-Kung
adder are examples of this type of adder.
Gerald Rosenberger of IBM filed for a patent on a modern binary carry-look ahead adder in
1957.
From Wikipedia, the free encyclopedia:
http://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder

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2.5 Subtractor

Trivia

Half Subtractor: The circuit which will subtract two bits and produce a borrow and difference.

Full Subtractor: The circuit which will subtract three bits and produce a borrow and difference.

2.5.1 Half Subtractor:

The half subtractor needs two inputs a minuend and a subtrahend bit and output bits are
borrow and difference. The logic symbol of the half subtractor is given in figure 9.

A Borrow
Input bits Output bits
B Difference

Figure 9: Logic symbol of Half subtractor

The truth table of half subtractor is given as

A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
A & B are the input variables

The Boolean expression for difference and borrow can be written as

Difference  AB  AB  A  B
Borrow  AB

Students are advised to design logic circuits using the above Boolean expression and verify
their diagram (see figure 10)

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Figure 10: Logic circuit for Half subtractor

Half subtractor can be realized using NAND gates only and is given in figure 11

Figure 11: Logic circuit for Half subtractor using NAND gates only

Difference  A AB  B AB
 A  AB  B  AB
  
 A A B  B A B 
 AB  B A


Borrow  B AB  B AB  B A  B  AB 

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Try Yourself

Design half subtractor using NOR gates only and obtain Boolean expression for difference &
borrow

Difference  A  A  B  B  A  B
 A A B  B  A B
 A A  B   B A  B 
 AB  AB

Borrow  A  A  B  A( A  B)  AB

2.5.2 Full Subtractor

The half subtractor can be used only for LSB subtraction. If there is a borrow during the
subtraction of the LSBs, it affects the subtractions in the next higher column; the
subtrahend bit is subtracted from the minuend bit, considering the borrow from that column
used for the subtraction in the preceding column. Such a subtraction is performed by a full
subtractor. It subtracts one bit (B) from another bit (A), when already there is a borrow B in
from the column for the subtraction in the preceding column, and outputs the difference bit
and the borrow bit required from the next column. The block diagram and the truth table of
a full subtractor are shown below:

A B Bin Bout Difference

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0

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1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Bin=Input Borrow
Bout=Borrow
A, B & Bin are the input variables

A Difference
Input bits
B Output bits

Input Borrow
Bin Bout Borrow

Figure 12: Logic symbol of Full Subtractor

The difference and borrow for full subtractor are evaluated as:

Difference  ABBin  AB Bin  AB Bin  ABB in

 
 Bin AB  AB  B in AB  AB  
 Bin A  B   B in A  B
 A  B  Bin

Borrow  ABBin  AB B in  ABBin  ABB in


 AB  A  B Bin 
The logic diagram of a full subtractor, using two half subtractor is shown in figure 12

Figure 12: Block diagram of Full subtractor using two half subtractors

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The complete circuit diagram of Full subtractor is given in figure 13.

Figure 13: Complete circuit diagram of Full subtractor

The full subtractor can also be realized in Universal logic using either only NAND gates and
is shown in figure 14.

Figure 14: Complete circuit diagram of Full subtractor

2.6 Adder/Subtractor

2.6.1 4-bit Parallel Adder/subtractor

The 4-bit parallel Adder/Subtractor can perform the operation of addition and subtraction.
The logic circuit is given in Figure 15

The circuit is used for addition or subtraction of 4 bit inputs A 3A2A1A0 and B3B2B1B0.

A3 A2 A1 A0

B3 B2 B1 B0
8s 4s 2s 1s

The circuit can either do addition or can do subtraction which is controlled by a control line,
but both the operation can not be performed simultaneously.

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Figure 15: 4-bit parallel Adder/Subtractor

The truth table for the operation can be summarized as

Control A B Y

0 0 0 0

0 1 1

1 1 0 1

1 1 0

When the control line is low i.e 0, then when a 0 is placed in input A of the XOR gates, the
bits pass through the XOR gate with no change. This can be verified from the truth table
that when A is 0 the output is the same as that of the input present at the input B. With the
control at 0, the inputs available at the Full Adders (FA) are A3A2A1A0, B3B2B1B0 and Cin. The
AND gate is disabled as one of the input is zero. Since the output of the AND gate is zero

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so there is no end carry Cin input for FA (1s). Thus with the control at 0 the units add the
binary number A3A2A1A0 to B3B2B1B0. The result appears at the output indicators.

When the control bit is in 1 position this causes the XOR gate to act as an inverter for the B
inputs to the full adders. From the truth table it can be verified that when control is in 1
position. The output is complement of B input. The 1 at the control bit also activates the
AND gate so that the information from the 8s Full adder can take the end around carry line
back to the 1s full adder. This subtractor, subtracts the binary input number B 3B2B1B0 from
A3A2A1A0. With 2’s complement method.

Taking an example as

Decimal Subtraction Binary Subtraction

10 1010

-6 -0110
4 0100

With the control line at 1, the inputs at FA as A3A2A1A0 and B3B2B1B0. i.e. 1’s complement of
input B3B2B1B0 first take place.

1010
After 1’s complement of Minuend
and finally adding Minuend and 1001
Subtrahend.
10011
End around carry + 1
0100(difference)

The difference appears in binary form on the output indicators.

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Adding machine

An adding machine was a class of mechanical calculator, usually specialized

for bookkeeping calculations. In the United States, the earliest adding machines were
usually built to read in dollars and cents. Adding machines were ubiquitous office
equipment until they were phased out in favor of calculators in the 1970s and by personal
computers beginning in about 1985. The older adding machines were rarely seen in
American office settings by the year 2000.

Blaise Pascal and Wilhelm Schickard were the two original inventors of the mechanical
calculator in 1642; For Pascal this was an adding machine that could perform additions and
subtractions directly and multiplication and divisions by repetitions, whilst Schickard's
machine, invented several decades earlier was less functionally efficient but was supported
by a mechanized form of multiplication tables. These two were followed by a string of
inventors and inventions leading to those ofThomas de Colmar who launched the
mechanical calculator industry in 1851 when he released his simplified arithmometer (it
took him thirty years to refine his machine, patented in 1820, into a simpler and more
reliable form). However, they didn't gain widespread use until Dorr E. Felt started
manufacturing his comptometer (1887) and Burroughs started the commercialization of
differently conceived adding machines (1892)

Adding machine for the Australian pound c.1910,

note the complement numbering, and the
columns set up forshillings and pence

An adding machine

Older adding machine. Its mechanism is

similar to a car odometer. A manual adding machine manufactured in the 1950s.
https://en.wikipedia.org/wiki/Adding_machine
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2.7 Summary

Summary

 A combinational circuit is one whose output at any time is determined from the
present combination of inputs with no storage or memory capability.
 The truth table for half adder is summarized as

A B Cout Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

 The truth table for full adder is summarized as

A B Cin Cout Sum

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

 The truth table for half subtractor is summarized as

A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

 The truth table for fullsubtractor is summarized as

A B Bin Bout Difference

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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 A 4-bit parallel Adder/Subtractor can be designed using full adders only and can
perform both addition and subtraction operation.

2.8 Exercises
2.8.1 Subjective Questions

1) Draw the circuit diagram of Half Adder using NAND gate only. Describe the operation
performed by Half adder.
2) Draw a block diagram of a full adder labeling all the inputs and outputs. Write the truth table
for full adder.
3) Draw the circuit diagram of Half Subtractor using NAND gate only. Describe its operation.
4) Draw a block diagram of a full Subtractor labeling all the inputs and outputs. Write the truth
table for full Subtractor.
5) Draw the Half Adder circuit using two input NOR gate.
6) Draw the Full Adder circuit using two input NOR gate.
7) Draw the Half Subtractor circuit using two input NOR gate.
8) Draw the Half Subtractor circuit using two input NOR gate.
9) Draw a logic circuit that has three inputs A, B and C and whose output will be high only
when majority inputs are high.

2.8.2 Fill in the blank

1) A half adder circuit is used for adding only the ………………. (1s, 2s, 4s, 8s) column of a
binary addition problem.
2) Adder circuits are widely used in ………………. Section of microprocessor.
3) The output of full adder is Σ = 1, Cout =1 when the inputs are ………………. .
4) The input of the full subtractor is A=B=Bin=1 then the output is given as ………………. .

Answers to the questions:

1) 1s
2) Arithmetic logic unit (ALU)
3) 1,1,1
4) Difference = 1 & Borrow = 1

2.8.3 Multiple Choice Questions

1) Full subtractor has ………………. Inputs and ………………. Outputs

A) 2,3 B) 2, 2

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C) 3, 2 D) 3, 3

2) An Adder/Subtractor can perform

A) only addition B) both addition and subtraction

C) only subtraction D) only multiplication

3) The sum of a Full adder can be represented by

A) 2 input X-OR gate B) 2 input NAND gate

C) 3 input NAND gate D) 3 input X-OR gate

4) The control line should be kept ………………. For performing subtraction using 4 bit
adder/subtractor

A) 0 B)1

C) 11 D) 10

Answers to multiple choice questions

1) 3,2
Justification: Full Subtractor has 3 inputs A, B, Bin and 2 outputs namely difference
and Borrow output

2) Both addition and subtraction

Justification: An Adder/Subtractor is designed to add two numbers as well as
subtract two numbers using 2’s complement method.

3) 3 input X-OR gate

Justification: Sum = ABC

4) 1
Justification: With Control line at 1, the Adder/subtractor subtracts two number using
2’s complement method.

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2.9 Glossary

Combinational Logic Circuit A combinational logic circuit is one whose output at any time
is determined from the present combination of inputs

Half Adder A digital circuit that adds two bits and produces a sum and a carry.

Full Adder A digital circuit which adds two bits and an input carry to produce a sum and an
output carry

Half Subtractor A digital circuit that subtracts two bits and produces difference and a
borrow if any.

Full Subtractor It subtracts one bit (B) from another bit (A), when already there is a
borrow Bin from the column for the subtraction in the precedingcolumn, and outputs the
difference bit and a borrow bit.

2.10 Reference Books:

 Digital Principles & Applications, A.P.Malvino, D.P.Leach & Saha, 7th Ed., 2011, Tata
McGraw
 Fundamentals of Digital Circuits, A. Anand Kumar, 2nd Edition, 2009, PHI Learning
Pvt. Ltd.
 Digital Electronics, Principles and applications, Roger L Tokheim, 2003, Tata McGraw
Hill.
 Digital Systems: Principles and Applications, R.J. Tocci, N.S.Widmer, 2001, PHI
Learning.
 Digital Electronics, An introduction to theory and practice, W H Gothmann, 1982, PHI
Learning.

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