Received April 9, 2019, accepted April 22, 2019, date of publication May 3, 2019, date of current version May

16, 2019.
Digital Object Identifier 10.1109/ACCESS.2019.2914430

A New Multilevel Inverter Topology

With Reduce Switch Count
MARIF DAULA SIDDIQUE1 , (Student Member, IEEE),
SAAD MEKHILEF 1,2 , (Senior Member, IEEE),
NORAISYAH MOHAMED SHAH1 , ADIL SARWAR3 ,
ATIF IQBAL 4 , (Senior Member, IEEE), AND
MUDASIR AHMED MEMON 1
1 Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia
2 Centerof Research Excellence in Renewable Energy and Power Systems, King Abdulaziz University, Jeddah 21589, Saudi Arabia
3 Department of Electrical Engineering, Aligarh Muslim University, Aligarh 202002, India
4 Department of Electrical Engineering, Qatar University, Doha 2713, Qatar

Corresponding authors: Saad Mekhilef ([email protected]) and Atif Iqbal ([email protected])

This work was supported by the Qatar University through the QU High Impact Grant QUHI-CENG-19/20-2. The statements made herein
are solely the responsibility of the authors. The publication charges are funded by the Qatar National Library, Doha, Qatar.

ABSTRACT Multilevel inverters are a new family of converters for dc–ac conversion for the medium and
high voltage and power applications. In this paper, two new topologies for the staircase output voltage
generations have been proposed with a lesser number of switch requirement. The first topology requires
three dc voltage sources and ten switches to synthesize 15 levels across the load. The extension of the first
topology has been proposed as the second topology, which consists of four dc voltage sources and 12 switches
to achieve 25 levels at the output. Both topologies, apart from having lesser switch count, exhibit the merits
in terms of reduced voltage stresses across the switches. In addition, a detailed comparative study of both
topologies has been presented in this paper to demonstrate the features of the proposed topologies. Several
experimental results have been included in this paper to validate the performances of the proposed topologies
with different loading condition and dynamic changes in load and modulation indexes.

INDEX TERMS Asymmetric, hybrid inverter, inverter topology, multilevel inverter, MLI, nearest level
control, power electronics, single-phase inverter, reduce switch count.

I. INTRODUCTION Flying Capacitor (FC) and Cascade H-Bridge (CHB) are the
Over the last few decades, multilevel inverter (MLI) topolo- three basic and popular MLI topologies used in commercial
gies have gained popularity in industrial application because application since last few decades. Although there are few
of the superior power quality compared to its conventional issues with the conventional MLI like a higher number of
two-level counterpart. Lower harmonic distortion and better source requirement, voltage balancing of the capacitor and
wave quality resembling a sinusoidal wave and lesser volt- large switch requirement in CHB topology, FC topology
age stress on the switches have added to its popularity. For and NPC topology respectively [4], [5]. Still, their advan-
low and medium voltage/power applications, MLI find their tages in terms of power quality supersede the shortcomings.
applications in almost every field of electrical engineering Researchers have been trying to solve and mitigate the issues
including renewable energy systems, HVDC applications, with MLI and have published a large number of papers over
distributed generation (DG) system, industrial drive applica- the last few years. They have mainly focused on reducing
tions, uninterruptible power supplies, etc [1]–[3]. They are the switch count, source count and voltage balancing control
widely used in drives and other allied areas in industries. of MLI. The design of MLI mainly depends upon the number
MLI’s are an assembly of power semiconductor devices along of levels required at the output, number of semiconductor
with different dc links to achieve staircase waveform close devices used, number of dc voltage sources and capacitors
to sinusoidal at the output. Neutral Point Clamped (NPC), utilized, modularity of topology and the total standing volt-
age (TSV) of topology, etc. Based on these aspects, a number
The associate editor coordinating the review of this manuscript and of MLI topologies have been presented and analyzed in the
approving it for publication was Tariq Masood. literature [2]–[7].

This work is licensed under a Creative Commons Attribution 3.0 License. For more information, see http://creativecommons.org/licenses/by/3.0/
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M. D. Siddique et al.: New MLI Topology With Reduce Switch Count

Another aspect of MLI has been the selection of magnitude together to create a new structure which produces 17 levels
of dc voltage sources used in the topology. Based on this, without the H-Bridge circuitry for voltage polarity reversal.
MLIs have been classified as symmetrical and asymmet- It utilizes 12 switches. The modules can be cascaded to pro-
rical. Symmetrical MLIs uses identical dc voltage sources duce a higher number of voltage level. An improved H-bridge
whereas asymmetrical MLIs employs dc voltage sources based high step-up multilevel converter has been presented
having unequal magnitude. Symmetrical MLIs have more in [17]. The basic unit consists of two unidirectional switches,
redundant states i.e. more number of switching combina- a capacitor, a power diode, and a dc voltage source. Control
tion are available to get same voltage level. This improves of switching devices ensures that the capacitor is charged to
the performance of MLI in terms of balancing the voltage twice the voltage of dc source thereby developing output volt-
across capacitors and fault tolerant capabilities. However, age higher than the input voltage. Two basic units along with
at the same time symmetrical configured MLIs requires more the improved H-bridge unit constitutes the high step-up MLI.
number of switches, gate driver circuits, and dc voltage links. The topology proposed in [18] suggested another basic unit
This increases the inverter size, cost and control complexity structure composed of four unidirectional switches, two bidi-
for a higher number of levels. Asymmetrical configuration rectional switches, and two dc sources. A modified H-Bridge
increases the number of levels generated at the output com- is sandwiched between two such basic units forming a module
pares to the symmetrical configuration using the same num- with two dc sources on left of modified H-bridge and the
ber of components and dc voltage sources [6], [7]. remaining two are on the right side. The cascaded structure
Various variants of conventional MLI have been reported has also been presented. Various graphical representation of
in the literature to overcome the shortcomings while others performance analysis points towards attractive features of
have mentioned the shortcoming of a conventional multilevel the proposed multiple level converter. Similarly, some other
inverter [8]. A higher number of switches are required to upgraded topologies have been proposed in [19]–[29].
generate a staircase multilevel waveform. Moreover, even In this paper, work has been carried out with the aim of
low rating switches require separate driver circuit along with reducing the number of power semiconductor devices and dc
necessary protective circuitry which adds to the complex- voltage sources, while achieving a higher number of levels at
ity of the system. Authors of [8] have compared the work the same time. This paper is organized as follows: Section II
with several topologies. The results presented show that the describes the proposed topology with its extension for a
number of IGBT required to realize a similar voltage level is higher number of level. To set the benchmark of the proposed
lesser [8]. Moreover, the standing voltages are also lesser on topology, Section III gives a quantitative comparison of the
the bidirectional switch. The topology of [8] has also been proposed topologies employing the same number of switches.
experimentally verified with a suitable design example. Section IV elaborates the various experimental results and
The topology proposed in [9] utilized two novel cascaded Section V summarizes the paper.
multilevel inverters which contain five-level sub-module
architecture. The proposed topology has been realized in
both the asymmetrical and symmetrical mode of operation.
The result shows the structure has advantages in levels of
voltage generated for a given number of switches. The topol-
ogy proposed in [10] requires eight switches to produce
15 level output. But the same voltage level can be achieved
by PUC converter proposed in [11] and later in [12] with
the lesser standing voltage on the switching devices. The
proposed application of topology presented in [10] includes
D-STATCOM, hybrid electric vehicle, and PV system.
Modular expendables symmetric and asymmetric struc-
tures with staircase cascading are reported in [13]. The
topology has been compared with [14] and results presented
claims to require lesser installation space and cost because
of the reduced number of switching devices, switching and
FIGURE 1. Proposed 3S-15L topology.
conduction losses and total standing voltage. The authors
of [13] have also presented the simulation results which are
validated by the experimental formulation of its prototype. II. PROPOSED MULTILEVEL INVERTER
The topologies of [15], [16] pointed out the disadvantage of A. PROPOSED THREE SOURCE
H-bridge based multilevel converters topologies because of 15 LEVEL (3S-15L) TOPOLOGY
higher switching stress and total standing voltage. The ST The proposed topology is depicted in Fig. 1. It consists of
topology is proposed in [16] contain two back to back con- eight unidirectional switches from S1 - S8 along with one
nected T type switching arrangements (each T-section have bidirectional switch S9 . The switches S3 - S6 along with S9
two unidirectional and two bidirectional switches) joined forms the inner part of the topology with two dc voltage

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 M. D. Siddique et al.: New MLI Topology With Reduce Switch Count

sources with a magnitude of V2 . The remaining four switches

i.e., S1 – S2 and S7 – S8 and one dc voltage source with mag-
nitude of V1 forms the outer portion of the proposed topol-
ogy. The switches (S1 –S2 ), (S3 –S4 ), (S5 –S6 ), and (S7 –S8 )
need to operate in a complementary fashion to avoid short-
circuiting of dc voltage sources.
The number of levels depends upon the magnitude of the
dc voltage source, i.e., V1 and V2 the selection can be done
in two ways as:
1) SYMMETRICAL CONFIGURATION
In this configuration, each dc voltage source has the same
magnitude, i.e., V1 = V2 = Vdc . With such configuration,
seven levels at the output are achieved.
2) ASYMMETRICAL CONFIGURATION
In the asymmetrical configuration, the magnitude of dc volt-
age sources have different magnitude, i.e., V1 and V2 have a
different magnitude. For the proposed topology with asym-
metrical configuration, the magnitude of dc voltage sources
are chosen in tertiary mode, i.e., V1 = Vdc , and V2 = 3Vdc
(3S-15L Topology). With the tertiary configuration, the pro-
posed topology generates 15 output voltage levels, i.e., zero,
±Vdc , ±2Vdc , ±3Vdc , ±4Vdc , ±5Vdc , ±6Vdc , and ±7Vdc .
The switching table for the proposed topology with the ter-
tiary mode is given in Table 1. Furthermore, the different
switching states for the proposed topology with tertiary mode
are shown in Figs. 2 (a)-(h).
TABLE 1. Switching state for the proposed 3S-15L topology.

FIGURE 2. Different switching states of the proposed 3S-15L topology in

positive half cycle. (a) Vo = 0. (b) Vo = Vdc . (c) Vo = 2Vdc . (d) Vo = 3Vdc .
(e) Vo = 4Vdc . (f) Vo = 5Vdc . (g) Vo = 6Vdc . (h) Vo = 7Vdc .

be the same. Therefore,


VS1 = VS2 = V1 = Vdc  
VS3 = VS4 = 2V2 = 6Vdc

(2)
VS5 = VS6 = 2V2 = 6Vdc 

VS7 = VS8 = V1 = Vdc


The voltage stress across each unidirectional switch of the

bidirectional switch S9 is given as:
With tertiary mode, the maximum output voltage (Vo,max) VS9 = V2 = 3Vdc (3)
of the proposed topology is:
As two unidirectional switches are used for the bidirectional
Vo,max = (V1 + 2V2 ) = 7Vdc (1)
switch, each unidirectional switch needs to block the voltage
The total standing voltage (TSV) is an important factor for of 3Vdc . Therefore,
the selection of switches. TSV is the addition of the maximum

blocking voltage across each semiconductor device. The volt- TSV = 2 VS1 + VS3 + VS5 + VS7 + VS9
age stress across each pair of the complementary switch will = 4V1 + 10V2 = 34Vdc (4)
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M. D. Siddique et al.: New MLI Topology With Reduce Switch Count

FIGURE 3. Proposed 4S-25L topology.

FIGURE 4. Extension I (E-I) of the proposed topology.
TABLE 2. Switching state for the proposed 4S-25L topology.

The proposed topology can be extended in two different ways

as explained below.

1) EXTENSION WITH HIGHER NUMBER OF DC VOLTAGE

SOURCES WITH MAGNITUDE V1
In this method, the number of dc voltage sources with magni-
tude V1 are increased in the outer T-section as shown in Fig. 4.
For achieving higher number of levels, the selection of dc
voltage sources is according to asymmetrical configuration.
For the maximum number of levels, with k number of dc
voltage sources of V1 = Vdc , the magnitude magnitude of
V2 is selected as:
V2 = (2k + 1) Vdc (5)
The peak output voltage is given as
Vo,max = kV1 + 2V2 = kVdc + 2 (2k + 1) Vdc
= (5k + 2)Vdc (6)
The expression for number of switch requirement, gate driver,
number of dc supply as a function of output voltage level is
given by (7).
B. PROPOSED FOUR SOURCE 
Nsw = 2k + 8 
25 LEVEL (4S-25L) TOPOLOGY 
Ngd = k + 8

The proposed 3S-15L topology can be extended by replac- (7)
Ndc = k + 2 
ing the single dc voltage source of magnitude V1 with a Nl = 10k + 5


T-configured two dc voltage sources with same magnitude
V1 as shown in Fig. 3. With the addition of one dc voltage The TSV for the proposed extension can be divided into two
source with magnitude V1 and a bidirectional switch S10 , parts as:
there is an addition in the number of levels. Again, for the TSVE−I = TSVT + TSVV2 (8)
symmetrical configuration, the proposed topology can gen-
erate nine levels. However, for asymmetrical configuration, where TSVT is the TSV for the T-section of the proposed
the number of levels increases to 25. The 25 level output is extension which is given as:
achieved by selecting V1 = Vdc and V2 = 5Vdc . The different
switching combination for the proposed topology with four TSVT = (4k + M )V 1 (9)
dc voltage sources generating 25 levels is given in Table 2. where,

C. GENERALIZED STRUCTURE OF 3k 2 + 2k − 1
M= for odd number of k
THE PROPOSED TOPOLOGY 4
In both proposed topologies with asymmetrical configu- 3k 2 + 2k
M= for even number of k
ration, the magnitude of V2 is higher compared to V1 . 4

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TSVV2 is the TSV of the topology with dc voltage sources of A. COMPARISON OF PROPOSED 3S-15L TOPOLOGY
magnitude V2 and is given by Eq. (4) which is: The quantitative comparison among the topologies is given
in Table 3. From the table, it is shown that the proposed
TSVV2 = 10V2 (10) MLI generates higher voltage levels compared to [13], [19],
and [24] and have the same capability of voltage level gener-
Therefore, from (8)-(10), ation as of [28]. However, proposed topology uses lesser gate
driver circuits and have lower TSV and MBV than [28] which
TSVE−I = (4k + M )V1 + 10V2 (11) lower the cost of the MLI.
TABLE 3. Quantitative comparison of the proposed 3S-15L topology.
2) EXTENSION WITH HIGHER NUMBER OF DC VOLTAGE
SOURCES WITH MAGNITUDE V2
One main issue with the extension 1 (Ext-II) has been the
magnitude of dc voltage source V2 as its magnitude is depen-
dent on k as given in Eq. (5). This problem can be solved by
increasing the number of voltage source with magnitude V2 .
Fig. 5 shows the Ext. II of the proposed topology. For a
higher number of levels with asymmetrical configuration,
the magnitude of dc voltages are selected as V1 = Vdc , and
V2 = 5Vdc . TABLE 4. Quantitative comparison of the proposed 4S-25L topology.

B. COMPARISON OF PROPOSED 4S-25L TOPOLOGY

In this comparison, similar topologies have been considered
which have four dc voltage sources and configure in a sym-
metrical configuration. Table 4 gives a quantitative compar-
ison of the proposed topology with other topologies. From
the table, it can be deduced that the topologies presented
FIGURE 5. Extension II (E-II) of the proposed topology. in [15], [16], [27], and [25] generates fewer voltage levels
compared to the proposed topology. In addition, the proposed
The different equations for the Ext. II remains the same as topology utilizes a lesser number of gate driver circuits with-
Ext. I as given in (7). The equation for TSV modifies as: out any diodes compared to [28] which decreases the system
cost and improves the conversion efficiency.
TSVE−II = 10V1 + (4k + M )V2 (12)
C. COMPARISON OF THE PROPOSED GENERALIZED
III. COMPARATIVE STUDY STRUCTURE WITH OTHER TOPOLOGIES
In this section, a detailed comparative study is provided for Fig. 6 (a) shows the variation of number of power semi-
the proposed topologies. The topology with three dc voltage conductor switches required againstt the number of levels
source, four dc voltage source, and generalized structure have at the output. From Fig. 6 (a) it is shown that the proposed
been compared separately with similar topologies. The pro- MLI generates higher voltage levels compared to all other
posed topologies with three and four dc voltage sources have topologies with number of levels more than 15. Furthermore,
been compared in terms of number of switches, number of the proposed inverter utilized less number of driver circuits
gate driver circuit required, number of levels generated, num- than all other topologies when voltage level are greater than
ber of diodes, TSV, and maximum blocking voltage (MBV) 40 as shown in Fig. 6 (b). Moreover, with number of levels
of any individual switch. The generalized structure has been more than 22, only [29] requires less number of driver circuit
compared in terms of number of switches, number of gate compare to proposed topology. In addition, the variation of
driver circuit, number of dc voltage sources and TSV against the number of dc voltage sources against the number of levels
the number of levels at the output. is illustrated in Fig. 6 (c). The proposed inverter utilized a

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M. D. Siddique et al.: New MLI Topology With Reduce Switch Count

FIGURE 7. (a) Sampled reference voltage with NLC and

(b) Implementation of NLC.

FIGURE 6. Variation of (a) number of switches, (b) number of gate driver

circuit and (c) number of dc voltage sources with respect to number of
levels.

lesser number of voltage sources than all other topologies

when number of levels are higher than 28. The lower number
of switches, driver circuit and dc voltage sources shows the
superiority of the proposed topology with other topologies
used for the comparison.

IV. RESULTS AND DISCUSSION

To verify the performance of the proposed topology, a lab-
oratory prototype has been developed for the experimen-
tal results. In the experimental setup, TOSHIBA IGBT
GT50J325 is used as a power switch. For the gate pulse
generation of different switches, dSPACE 1104 controller
is used. The modulation techniques are divided into two FIGURE 8. Experimental results for (a) 15 level output voltage, (b) voltage
stress across switches S1 , S3 , S4 , and (c) voltage stress across switches
categories i.e. fundamental switching frequency techniques S5 , S7 , and S9 .
and high switching frequency techniques. The nearest level
control (NLC) and selective harmonic elimination pulse examples of high switching frequency technique. The funda-
width modulation (SHEPWM) are examples of fundamental mental switching frequency techniques are more preferable
switching frequency techniques. The sinusoidal pulse width than high switching frequency techniques due to its ability
modulation (SPWM) and space vector modulation are the of achieving higher energy conversion with less system cost.

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FIGURE 9. Experimental results for 15 levels output (a) output voltage and current waveform with different resistive load [scale: vo = 40V/div,
io =2A/div], (b) transient-state waveforms with change of load from R=0 to R=60 , [scale: vo = 40V/div, io =2A/div], (c) transient-state waveforms
with change of load from R=60  to R=30 , [scale: vo = 40V/div, io =2A/div], (d) transient-state waveforms with change of load from R=30  to
R=60 , [scale: vo = 40V/div, io =2A/div], (e) steady-state waveform with R=0  [scale: vo = 40V/div, io =1A/div], (f) steady-state waveform with
R=60  [scale: vo = 40V/div, io =1A/div], (g) steady-state waveform with R=30  [scale: vo = 40V/div, io =2A/div].

Among fundamental switching frequency techniques, the In this paper, the hardware results for the proposed
NLC is normally used due to its easy control and implemen- topology with 3S-15L and 4S-25L configuration have been
tation when working on high level inverter. presented.
In this paper, fundamental frequency modulation tech-
niques based nearest level control (NLC) is used for the A. EXPERIMENTAL RESULTS FOR PROPOSED
generation of gate pulse. With NLC, the sampled waveform is 4S-15L TOPOLOGY
generated by comparing the reference signal with the existing As shown in Fig. 8, the proposed topology with three dc
voltage level as shown in Fig. 7 (a). Fig. 7 (b) shows the voltage sources generates 15 levels at the output having
general control diagram for the NLC. in Fig. 8 (a). Moreover, the voltage stress across different

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FIGURE 10. Experimental results for 15 levels output (a) output voltage and current waveform with different
resistive-inductive load, (b) transient-state waveforms with change of load from Z=0 to Z=60  + 100 mH, (c) transient-state
waveforms with change of load from Z=60  + 100 mH to Z=60  + 50 mH, (d) steady-state waveform with Z=0 ,
(e) steady-state waveform with Z=60  + 100 mH, and (f) steady-state waveform with Z=60  + 50 mH. [Scales: vo = 40V/div,
io =1A/div].

FIGURE 11. Output voltage and current waveform with change of modulation index from 1.0 to 0.5 with (a) R = 100  [Scales:
vo = 40V/div, io =2A/div], and (b) R=100 , L=100mH, [Scales: vo = 40V/div, io =1A/div].

switches are also shown in Fig. 8 (b) and (c). All these voltage response of the proposed topology with change in the mag-
stresses are in consistence with equation (2) and (3). nitude of resistive load. Figs. 9 (b) - (d) gives the transient
Furthermore, the proposed topology is tested with different response i.e., showing the change of current as the load
types of loading conditions. Fig. 9 (a) shows the dynamic magnitude is changed. Furthermore, Fig. 9 (e) - (g) depicts
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FIGURE 12. Experimental results for (a) 25 level output voltage waveform, (b) zoomed view of output voltage, (c) output voltage and current
waveform with different resistive load [scale: vo = 100V/div, io =2A/div], (d) transient-state waveforms with change of load from R=0 to
R=100 , [scale: vo = 100V/div, io =2A/div], (e) transient-state waveforms with change of load from R=100  to R=50 , [scale: vo = 40V/div,
io =2A/div].

the steady-state response with the resistive load. A similar A change of modulation index has also been considered
test has been conducted with series connected the resistive- while validating the performance of the proposed topology.
inductive load. Fig. 10 (a) – (f) shows the different transient Fig. 11 (a) illustrate the output voltage and current waveform
and steady-state response for RL load. with a change of modulation indexes from 1.0 to 0.5 with a

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resistive load of 100 . With the change of modulation index [6] M. Vijeh, M. Rezanejad, E. Samadaei, and K. Bertilsson, ‘‘A general
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 M. D. Siddique et al.: New MLI Topology With Reduce Switch Count

[28] R. S. Alishah, S. H. Hosseini, E. Babaei, and M. Sabahi, ‘‘Optimal design ADIL SARWAR received the bachelor’s and mas-
of new cascaded switch-ladder multilevel inverter structure,’’ IEEE Trans. ter’s degrees in technology and the Ph.D. degree
Ind. Electron., vol. 64, no. 3, pp. 2072–2080, Mar. 2017. from Aligarh Muslim University, in 2006, 2008,
[29] G.-J. Su, ‘‘Multilevel DC-link inverter,’’ IEEE Trans. Ind. Appl., vol. 41, and 2012, respectively. He is currently an Assistant
no. 3, pp. 848–854, May 2005. Professor with the Department of Electrical Engi-
[30] M. D. Siddique and A. Sarwar, ‘‘Performance analysis of carrier based neering, Aligarh Muslim University, India. He has
PWM technique for three level diode clamped multilevel inverter with authored or coauthored more than 25 research
different reference signals,’’ in Proc. IEEE 7th Power India Int. Conf.
papers. He has coauthored a chapter in Power
(PIICON), Nov. 2016, pp. 1–6.
Electronics Handbook, Fourth Edition edited by
[31] G. Konstantinou, J. Pou, S. Ceballos, R. Darus, and V. G. Agelidis,
‘‘Switching frequency analysis of staircase-modulated modular multilevel M. H. Rashid. His research interests include
converters and equivalent PWM techniques,’’ IEEE Trans. Power Del., power electronic converters, solar photovoltaic systems, and metaheuristic
vol. 31, no. 1, pp. 28–36, Feb. 2016. algorithms.
[32] M. S. A. Dahidah, G. Konstantinou, and V. G. Agelidis, ‘‘A review
of multilevel selective harmonic elimination PWM: Formulations, solv-
ing algorithms, implementation and applications,’’ IEEE Trans. Power
Electron., vol. 30, no. 8, pp. 4091–4106, Aug. 2015.
[33] M. A. Memon, S. Mekhilef, and M. Mubin, ‘‘Selective harmonic elimi- ATIF IQBAL (M’09–SM’11) received the B.Sc.
nation in multilevel inverter using hybrid APSO algorithm,’’ IET Power Engineering (Gold Medal) and M.Sc. Engineer-
Electron., vol. 11, no. 10, pp. 1673–1680, Aug. 2018. ing degrees in power system and drives from
Aligarh Muslim University (AMU), Aligarh,
India, in 1991 and 1996, respectively, and the
Ph.D. degree from Liverpool John Moores Univer-
MARIF DAULA SIDDIQUE (S’18) was born sity, Liverpool, U.K., in 2006.
in Chhapra, India, in 1992. He received the He is currently an Associate Professor in electri-
B.Tech. and M.Tech. degrees in electrical engi- cal engineering with Qatar University and a former
neering from Aligarh Muslim University (AMU), Full Professor in electrical engineering with AMU.
in 2014 and 2016, respectively. He is currently pur- He has been a Lecturer with the Department of Electrical Engineering,
suing the Ph.D. degree with the Power Electron- AMU, since 1991, where he served as Full Professor, until 2016. From
ics and Renewable Energy Research Laboratory 2009 to 2016, he was a Lecturer and then an Assistant Professor with
(PEARL), Department of Electrical Engineering, the Institute of Information and Communication Technology, University of
University of Malaya, Kuala Lumpur, Malaysia. Sindh, Jamshoro, Pakistan. He has published widely in international journals
His research interests include step-up power elec- and conferences, and his research findings are related to power electronics
tronics converters (dc/ac and dc/dc), multilevel inverter topologies, and their and renewable energy sources. He has authored or coauthored more than
control. 350 research papers, one book, and three chapters in two other books. He has
supervised several large R&D projects. His principal area of research interest
is modeling and simulation of power electronic converters, control of multi-
phase motor drives, and renewable energy sources. His research interests
SAAD MEKHILEF (M’01–SM’12) received the include multilevel inverters, power quality, and control strategies. He is a
B.Eng. degree in electrical engineering from the Fellow of IET, U.K., and IE, India. He was a recipient of the Outstanding
University of Setif, Setif, Algeria, in 1995, and Faculty Merit Award, from 2014 to 2015, and the Research Excellence Award
the master’s degree in engineering science and the at Qatar University, Doha, Qatar. He was a recipient of the Maulana Tufail
Ph.D. degree in electrical engineering from the Ahmad Gold Medal for standing first at B.Sc. Eng. Exams from AMU,
University of Malaya, Kuala Lumpur, Malaysia, in 1991. He has received best research papers award at IEEE ICIT-2013,
in 1998 and 2003, respectively, where he is cur- IET-SEISCON-2013, and SIGMA 2018. He is currently an Associate Editor
rently a Professor and the Director of the Power of the IEEE TRANSACTIONS ON INDUSTRY APPLICATION and the IEEE ACCESS and
Electronics and Renewable Energy Research Lab- the Editor-in-Chief of i’manager’s Journal of Electrical Engineering.
oratory, Department of Electrical Engineering.
He has authored or coauthored more than 400 publications in international
journals and conference proceedings. His current research interests include
power converter topologies, control of power converters, renewable energy,
and energy efficiency. MUDASIR AHMED MEMON received the B.E.
degree in electronics engineering and the M.E.
degree in electronic systems engineering from the
Mehran University of Engineering and Technol-
NORAISYAH MOHAMED SHAH received the ogy, Jamshoro, Pakistan, in 2009 and 2015, respec-
B.Eng. degree from the University of Malaya, tively. He is currently pursuing the Ph.D. degree in
in 1999, the M.Eng. degree from Oita University, power electronics with the University of Malaya,
Japan, in 2003, and the Ph.D. degree from George Malaysia.
Mason University, Fairfax, VA, USA, in 2014. She From 2009 to 2016, he was a Lecturer and then
is currently a Senior Lecturer with the Department an Assistant Professor with the Institute of Infor-
of Electrical Engineering, University of Malaya. mation and Communication Technology, University of Sindh, Jamshoro,
Her current research interests include signal pro- Pakistan. His research interests include multilevel inverters, power quality,
cessing and renewable energy. and control strategies.

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