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An Analysis of Program and Erase Mechanisms for Floating Channel Type

Surrounding Gate Transistor Flash Memory Cells

Article  in  IEICE Transactions on Electronics · September 2004

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 IEICE TRANS. ELECTRON., VOL.E87–C, NO.9 SEPTEMBER 2004
1628

PAPER
An Analysis of Program and Erase Mechanisms for Floating
Channel Type Surrounding Gate Transistor Flash Memory Cells
Masakazu HIOKI†∗a) , Hiroshi SAKURABA† , Tetsuo ENDOH† , and Fujio MASUOKA† , Members

SUMMARY This paper analyzes program and erase mechanisms for silicon pillar while erase is performed by FN tunneling of
Floating Channel type Surrounding Gate Transistor (FC-SGT) Flash mem- electrons from the floating gate to the source. Device op-
ory cells for the first time. In FC-SGT Flash memory cell, control gate,
eration of the cell is the same as in the conventional hot-
floating gate, drain and source is arranged vertically on the substrate. The
body region is isolated from the substrate by the bottom source region. The electron programmed NOR structure used in planar technol-
cell is programmed by applying a high positive voltage to the control gate ogy. This operation is not suitable for Flash memories for
electrode with drain and source electrodes grounded. Erasing is performed mass storage applications [5]. Therefore, Flash memory uti-
by applying a high positive voltage to the drain and source electrodes with lizing the 3-D PENCIL Flash EPROM cell cannot achieve
the control gate electrode grounded. The physical models for program and
erase operations in FC-SGT Flash memory cell are developed. Program
high-speed programming and low-power consumption re-
and erase operations based on the developed physical models are simulated quired for mass storage in portable computers and battery-
by utilizing a device simulator. Program and erase characteristics obtained powered systems. In other words, the 3-D PENCIL Flash
from the device simulation agree well with the results of analytical models. EPROM cell is not suitable for Flash memories with high-
The FC-SGT Flash memory cell can realize program and erase operation
speed programming and low-power consumption for mass
with a floating body structure.
key words: Flash memory, Surrounding Gate Transistor (SGT), floating storage applications. Therefore, conventional Flash memo-
body, program and erase operation ries cannot achieve high-density, high-speed programming
and low-power consumption simultaneously.
1. Introduction In order to overcome these drawbacks of conventional
Flash memories, a Floating Channel type Surrounding Gate
Transistor (FC-SGT) Flash memory has been proposed [6],
High-density Flash memories realizing high-speed pro-
[7]. In principle, FC-SGT Flash memory cell can over-
gramming and low-power consumption are attracting much
come the scaling issues in planar technology because FC-
interest as media for mass storage in portable computers
SGT Flash memory cell is a 3-D structured cell. Moreover,
and battery-powered systems. In these applications, Flash
program speed of FC-SGT Flash memory cell is twice as
memories are used to store personal data. Offering high-
fast as compared to planar NAND Flash memory cell. How-
speed programming and low-power consumption, program
ever, the program and erase mechanisms of FC-SGT Flash
and erase operation [1] is well suited for these portable ap-
memory cell has not been discussed in previous works [6],
plications [2]. Also, the amount of data to be stored is on
[7].
an upward trend. Recently, a high-density Flash memory
In this paper, program and erase mechanisms for FC-
with the cell size of 4.4F2 (F:feature size) has been reported
SGT Flash memory cell are analyzed for the first time, and
[3]. However, further scaling of Flash memory cells in pla-
it is clarified that FC-SGT Flash memory cell can realize the
nar technology is becoming increasingly difficult because
program and erase operations with the floating body struc-
of concerns related to punch through, reliability, process
ture. In Sect. 2, the device structure, program and erase
windows, read current, and isolation requirements between
operation methods for FC-SGT Flash memory cell are de-
cells.
scribed. In Sect. 3, the physical models for program and
To overcome above scaling issues in planar technology,
erase operations in FC-SGT Flash memory cell are devel-
a three-dimensional (3-D) structured Flash memory cell, 3-
oped. In Sect. 4, program and erase operations based on the
D Programmable Erasable Nonvolatile CylIndlicaL (PEN-
physical models developed in the previous section are sim-
CIL) Flash EPROM cell, has been reported [4]. In the 3-
ulated by utilizing two-dimensional device simulator, and
D PENCIL Flash EPROM cell, the body region is in elec-
the program and erase characteristics obtained with two de-
trical contact with the substrate. The cell is programmed
vice simulations are compared with the results of analytical
by channel hot-electron injection at the drain end of the
models. Finally, in Sect. 5, conclusions are given.
Manuscript received November 8, 2002.
Manuscript revised October 28, 2003. 2. Device Structure, Program and Erase Operation
†
The authors are with the Research Institute of Electrical Com- Methods
munication, Tohoku University, Sendai-shi, 980-8577 Japan.
∗
Presently, with Electroinfomatics Group, Nanoelectronics
Research Institute, National Institute of Advanced Industrial Sci- In this section, the device structure, program and erase oper-
ence and Technology. ation methods for FC-SGT Flash memory cell are described.
a) E-mail: [email protected] Figure 1 shows the bird’s eye view and cross sectional
HIOKI et al.: AN ANALYSIS OF PROGRAM AND ERASE MECHANISMS FOR FC-SGT FLASH MEMORY CELLS
1629

(a)

Fig. 1 Bird’s eye view and cross sectional view of FC-SGT Flash mem-
ory cell.

(b)
Fig. 3 The physical model (a) and the equivalent circuit (b) in program
operation.

3.1 Programming

The physical model in program operation is shown in

Fig. 2 (a) Program and (b) erase operation methods for FC-SGT Flash Fig. 3(a). In program operation, a high positive voltage is
memory cell. applied to the control gate, while drain and source elec-
trodes are set to 0 V. The body region is coupled to ground
through the pn-junction capacitances between p-type body
view of FC-SGT Flash memory cell. The FC-SGT Flash region and diffusion regions. Therefore, the potential of
memory cell has a three-dimensional (3-D) structure. The floating body region is determined by the capacitive cou-
FC-SGT Flash memory cell, whose source, gate and drain pling of interpoly insulator capacitance, tunnel oxide capac-
are arranged vertically, uses the sidewall of the silicon pillar itance, depletion region capacitance under tunnel oxide and
as surface channel. The control gate and floating gate elec- pn-junction capacitances. Until the body surface is inverted,
trodes surround the silicon pillar. The p-type body region is the potential of body region increases slightly, following the
floating because it is electrically isolated from the substrate control gate bias. Once the surface of floating body region
by the bottom source region. is inverted, the surface potential of floating body region is
Figure 2(a) shows the program operation for FC-SGT the same potential as of n-type drain and source because the
Flash memory cell [7]. The program operation is performed surface of p-type body region becomes n-type semiconduc-
by applying a high positive voltage (VP ) to the control gate, tor. Moreover, body potential is not affected by control gate
while drain and source electrodes are set to 0 V. Under these bias because the floating body region is effectively shielded
conditions, electrons are injected by FN tunneling to the from further penetration of the electric field by the inversion
floating gate, resulting in a positive threshold voltage shift. layer.
On the other hand, the erase operation for FC-SGT Figure 3(b) shows the equivalent circuit of FC-SGT
Flash memory cell is shown in Fig. 2(b). The erase opera- Flash memory cell in program operation. Ci is the interpoly
tion is performed by applying 0 V to the control gate, while insulator capacitance, Ct is the tunnel oxide capacitance and
setting drain and source to a high positive voltage (VE ). Un- JFN is the FN current flowing the tunnel oxide. Though the
der these conditions, electrons are emitted by FN tunneling body region is floating, the surface potential is fixed at drain
from the floating gate to floating channel. the threshold volt- and source voltage of 0 V because of the inversion layer
age of memory cell decreases as a function of the erasing formed at the surface of body region. Electrons are injected
time. by FN tunneling from the inversion layer, the gate-to-drain
and gate-to-source overlap regions to the floating gate over
3. Physical Models the whole channel region.
In this section, the physical models for program and erase
operations in FC-SGT Flash memory cell are developed.
 IEICE TRANS. ELECTRON., VOL.E87–C, NO.9 SEPTEMBER 2004
1630

floating gate-to-drain and floating gate-to-source overlap re-

3.2 Erasing gions because a high positive voltage is applied to the drain
and source, while the control gate is grounded. Electron-
The physical model in erase operation is shown in Fig. 4(a). hole pairs are generated by band-to-band tunneling. Holes
In erase operation, a high positive voltage is applied to the generated by the band-to-band tunneling accumulate at the
drain and source electrodes, while the control gate is set surface of the floating body region after being swept out by
to 0 V. Under these bias conditions, the two physical car- the electric field across the drain and source junction. Elec-
rier generation processes occur in FC-SGT Flash memory trons generated at the drain and source junctions are col-
cell: (1) impact ionization (II), (2) band-to-band tunneling lected by the drain and source electrodes, respectively. (3)
(BBT). Moreover, as a third component, the current from FN tunneling occurs through the tunnel oxide. During erase
the floating gate originates from (3) FN tunneling of elec- operation, electrons are emitted from the floating gate to the
trons (FN). The physical carrier generation processes during source, drain and floating body region by FN tunneling.
erase operation are explained as follows: (1) Impact ioniza- Figure 4(b) shows the equivalent circuit of FC-SGT
tion occurs in the depletion region between n-type diffusion Flash memory cell in erase operation. Cd is the pn-junction
region and p-type floating body region. During erase oper- capacitance between n-type diffusion regions and p-type
ation, a high positive voltage is applied to the n-type drain floating body region, Ct is the tunnel oxide capacitance,
and source regions, while the p-type floating body region Cto is the floating gate-to-diffusion region overlap capac-
is coupled to ground through the series capacitance, which itance and Ci is the interpoly insulator capacitance. The
consists of the tunnel oxide capacitance and interpoly insu- floating body region is charged up to the erase voltage be-
lator capacitance. Under these bias conditions, the electric cause the charge, which originates from generation currents
field across the depletion region increases during the ramp at pn-junctions (Jgen ) by the impact ionization and band-to-
up of the erase voltage. The carriers in the depletion region band tunneling, is accumulated in the floating body region
gain high energy by the high electric field. As a result, im- (Qbody ). Electrons are emitted by FN tunneling from the
pact ionization occurs, and electron-hole pairs are generated floating gate to the body region, the gate-to-drain and gate-
in the depletion region. The holes generated in the depletion to-source overlap regions over the whole channel region.
region drift to the floating body region by the electric field
across the pn-junction, where they accumulate at the surface 4. Simulation Results and Discussion
of floating body region. On the other hand, electrons gen-
erated at the drain and source junctions are collected by the The surface potential of the floating body region greatly in-
drain and source electrode, respectively. (2) Band-to-band fluences the program and erase characteristics of FC-SGT
tunneling occurs in the floating gate-to-diffusion overlap re- Flash memory cell with floating body structure because FN
gion. A deep depletion region is formed underneath the tunneling depends strongly on the difference between the
floating gate potential and the surface potential of the float-
ing body region. Therefore, in this section, the surface po-
tential of the floating body region during program operation
and erase operation is discussed in detail utilizing a two-
dimensional (2-D) device simulator [8].
Figure 5 shows the structure of FC-SGT Flash memory

(a)

(b)
Fig. 4 The physical model (a) and equivalent circuit (b) in erase Fig. 5 The structure of FC-SGT Flash memory cell used in the 2-D de-
operation. vice simulation. 2-D simulation is carried out in the cylindrical coordinate.
HIOKI et al.: AN ANALYSIS OF PROGRAM AND ERASE MECHANISMS FOR FC-SGT FLASH MEMORY CELLS
1631

Table 1 Device parameters.

Gate length 1.0 µm
Silicon pillar radius 0.2 µm
Tunnel oxide thickness 10 nm
Interpoly insulator thickness 20 nm
Coupling ratio 1

cell used in the 2-D device simulation. The 2-D device sim-
ulation is carried out in the cylindrical coordinate. The sur-
face potential of the floating body region as shown in Fig. 5
is extracted as a function of programming and erasing time.
The probe point is located at the middle between drain and
source. Device parameters are shown in Table 1. FN tun-
neling currents do not flow through the interpoly insulator (a)
in the device simulation. In the device simulation, physical
based models are utilized as follows [8],
1. Boltzmann carrier statistics model
2. Lombardi (CVT) mobility model
3. Shockley-Read-Hole recombination model
4. Selberrherr’s impact ionization model
5. Band-to-band tunneling model
6. Fowler-Nordheim (FN) tunneling model
Moreover, potential is defined as the intrinsic fermi level in
the device simulator.
Figure 6(a) shows the surface potential of floating body
region in FC-SGT Flash memory cell during program op-
eration. Program voltage is set to 18 V. As shown in
Fig. 6(a), the surface potential of floating body region in- (b)
creases slightly because the semiconductor surface of float- Fig. 6 Surface potential of the floating body region during (a) program
ing body region is depleted with increase of control gate and (b) erase operation.
bias. Moreover, at the programming times of 13 ps, the sur-
face potential is fixed at 0.5 V because strong inversion oc-
curs at the pillar surface in the floating body region during and “FN” stand for impact ionization, band-to-band tunnel-
program operation. For the programming times longer than ing and FN tunneling, respectively. The erase voltage of
13 ps, the surface potential of floating body region keeps the 18 V is indicated by the dotted line in Figs. 7(a)–(d).
constant value of 0.5 V even if the control gate bias increases Figure 7(a) shows the build-up of the surface potential
because the floating body region is effectively shielded from with erase time, taking only the capacitance network cou-
further penetration of the electric field by the inversion layer. pling into consideration in the simulation. Carrier statistics,
As a result, FC-SGT Flash memory cell can realize the in- mobility, recombination models only are used in this simu-
jection of electrons by FN tunneling over the floating gate- lation. In this case, the surface potential increases up to 8 V
to-drain overlap region, floating gate-source overlap region within 0.1 ns, and remains constant for longer erase times.
and whole channel area. Taking impact ionization (II) as additional carrier genera-
Figure 6(b) shows the surface potential of floating body tion process into account, the surface potential increases by
region in FC-SGT Flash memory cell during erase opera- 4 V to 12 V for erase times greater than 0.1 ns as plotted by
tion. Erase voltage is set to 18 V. During erase operation, the solid line in Fig. 7(b). The broken line indicates the
the surface potential of floating body region shows a com- surface potential taking only carrier statistics, recombina-
plex dependence on erasing time. tion and mobility models into consideration (c.f. Fig. 7(a)).
To clarify the time-dependence of the surface potential Holes generated by impact ionization at pn-junctions are ac-
of floating body region on the above-mentioned three carrier cumulated at the surface of the floating body region, result-
generation processes, the surface potential of floating body ing in the increase of surface potential by 4 V. Furthermore,
region in FC-SGT Flash memory cell is simulated consider- the surface potential of floating body region considering
ing stepwise impact ionization, band-to-band tunneling, and band-to-band tunneling (BBT) as additional carrier gener-
FN tunneling. ation process is shown in Fig. 7(c). Including band-to-band
Figure 7(a) to Fig. 7(d) show the time-dependence of tunneling gives rise to an additional increase in the surface
the surface potential of the floating body region on the three potential as shown in Fig. 7(c) compared with the surface
carrier generation processes. In these figures, “II,” “BBT,” potential which takes impact ionization, carrier statistics,
 IEICE TRANS. ELECTRON., VOL.E87–C, NO.9 SEPTEMBER 2004
1632

Fig. 7 Surface potential of floating body region during erase operation (a) neglecting impact ionization,
band-to-band tunneling and FN tunneling, (b) considering only impact ionization (II) as carrier generation
process, (c) taking impact ionization (II) and band-to-band tunneling (BBT) as additional carrier generation
processes into consideration, (d) taking impact ionization (II), band-to-band tunneling (BBT) and Fowler-
Nordheim tunneling (FN) as additional carrier generation processes into consideration.

recombination and mobility models into consideration (in-

dicated by the dotted line in Fig. 7(c)). The surface poten-
tial increases slowly for long erase times in the time domain
considered herein. However, the surface potential of floating
body region and erase voltage differ by 0.5 V for erase times
of 2 ms. Finally, the build-up of the surface potential consid-
ering impact ionization (II), band-to-band tunneling (BBT)
and FN tunneling (FN) as additional carrier generation pro-
cesses is shown in Fig. 7(d). Compared to the surface poten-
tial taking impact ionization, band-to-band tunneling, car-
rier statistics, recombination and mobility models into con-
sideration as indicated by the dotted line, the surface poten-
tial achieves the same potential as that of drain and source
for erase times of 2 ms. This increase of the surface poten-
Fig. 8 Floating gate potential and stored charge on the floating gate
tial between 0.3 µs and 2 ms occurs by capacitance coupling during erase operation.
of floating gate and floating body region.
The floating gate potential and the stored charge on
the floating gate during erase operation are shown in Fig. 8. into consideration. As shown in Fig. 8, positive charges are
The straight lines indicate the floating gate potential and stored on the floating gate because electrons are emitted by
the stored charge on the floating gate as a function of erase FN tunneling from the floating gate, resulting in the increase
time considering impact ionization, band-to-band tunneling of floating gate potential. This increase of floating gate po-
and FN tunneling as additional carrier generation processes. tential starts from 0.3 µs.
The broken lines indicate the floating gate potential and the On the other hand, based on the equivalent circuit for
stored charge on the floating gate as a function of erase times the FC-SGT device (cf. Fig. 5), the floating body potential
with impact ionization and band-to-band tunneling taken (Vbody ) as a function of floating gate potential (V f g ) can be
HIOKI et al.: AN ANALYSIS OF PROGRAM AND ERASE MECHANISMS FOR FC-SGT FLASH MEMORY CELLS
1633

Fig. 10 Program and erase characteristics compared between device

simulation results and results of analytical model.
Fig. 9 Dependence of surface potential of floating body region on
floating gate potential.

tunneling is considered as additional carrier generation pro-

expressed as follows:
cess. Moreover, device simulation results are compared to
Ct /2(V f g +VFB )+2Cd (VE +ΦB )+Qbody the results obtained by the analytical models [6] as shown
Vbody (V f g ) =
Ct /2+2Cd in Fig. 10. The analytical models are based on the three-
(1) dimensional structure. The device simulation results agree
with the results obtained with analytical model.
where VF B is the flat band voltage, and ΦB is the built-in po- In this study, FC-SGT Flash memory has a long chan-
tential of the pn-junction. Figure 9 shows the dependence of nel of 1 µs. Long channel SGT device results in high aspect
the potential of floating body region (Vbody ) on the floating ratio and difficulties of fabrication because SGT device is ar-
gate potential (V f g ) obtained with Eq. (1). Results from the ranged vertically on the substrate. Therefore, the influences
device simulation are plotted for comparison. From the de- of channel length scaling on program and erase operation
vice simulation, the charge accumulated in the floating body in FC-SGT Flash memory are discussed. In this discussion,
region (Qbody ) as described in Eq. (1) is determined as fol- it is assumed that gate length is shrunk setting the ratio of
lows: channel length and gate-to-diffusion overlap length of 0.5
Qbody = (Ct /2 + 2Cd )Vbody0 − Ct /2(V f g0 − VF B ) constant and setting gate length and diffusion height of 0.5,
and other parameters are fixed value.
− 2Cd (VE + ΦB ) (2) Programming is done by injection of electrons from the
where floating body potential (Vbody0 ) and floating gate po- inversion layer formed at the surface of the floating body re-
tential (V f g0 ) for erase time of 0.3 µs are about 17.1 V and gion to the floating gate. High positive voltage enough to
10.3 V, respectively. The charge accumulated in the float- invert the surface of floating body is applied to the control
ing body region (Qbody ) can be approximately set constant. gate. Forming inversion layer is dependent on gate voltage,
Moreover, the pn-junction capacitance is given as follows, oxide thickness and impurity concentration in the body, is

independent on gate length. Therefore, programming oper-
2 si NA + ND ation doesn’t have dependence on shrinking gate length.
Cd = ΦB (3) On the other hand, erasing is performed by emission
q NA ND
of electrons from the floating gate to the gate overlapped
where  si is the dielectric constant of silicon, q is the mag- diffusion region and the floating body which is the same
nitude of elementary charge, NA is the acceptor concentra- voltage as the diffusion region applied to the high positive
tion and ND is the donor concentration. The build-up of voltage. Potential of the floating body increases when the
the surface potential of the floating body region (Vbody ) as junction capacitances and the gate capacitance are charged
calculated by our simple model in the voltage range from by holes generated by impact ionization and band-to-band
10.3 to 11.4 V of the floating gate potential (V f g ) agrees tunneling. The gate capacitance becomes small by shrink-
well with the results obtained with the device simulation. ing gate length. On the other hand, the junction capacitance
This shows that capacitance coupling causes the increase of has constant value because the junction area and impurity
the floating body potential with erase time. Moreover, the concentration in the floating body region are assumed as
increase of the floating gate potential (V f g ) in that range is the fixed value. Therefore, it is expected that the floating
due to the emission of electrons by FN tunneling as shown body potential can achieve the same potential as of drain
in Fig. 9. Therefore, the surface potential achieves the same and source quickly by shrinking the gate length. Figure 11
value as of drain and source for erase time of 2 ms when FN shows the dependence of time for the floating body poten-
 IEICE TRANS. ELECTRON., VOL.E87–C, NO.9 SEPTEMBER 2004
1634

and erase characteristics obtained from the two dimensional

device simulation agree well with the results of analytical
models. The FC-SGT Flash memory cell can realize pro-
gram and erase operation with a floating body structure.

References

[1] T. Endoh, R. Shirota, S. Aritome, and F. Masuoka, “A study of high-

performance NAND structured EEPROMS,” IEICE Trans. Electron.,
vol.E75-C, no.11, pp.1351–1357, Nov. 1992.
[2] K. Imamiya, Y. Sugiura, H. Nakamura, T. Himeno, K. Takeuchi, T.
Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K. Shimizu,
K. Hatakeyama, and K. Sakui, “A 130-mm2 , 256-Mbit NAND flash
with shallow trench isolation technology,” IEEE J. Solid-State Cir-
cuits, vol.34, pp.1536–1543, Nov. 1999.
Fig. 11 The dependence of time for the floating body potential and the [3] F. Arai, N. Arai, S. Satoh, T. Yaegashi, E. Kamiyama, Y. Mat-
erase voltage to be in agreement on the gate length. sunaga, H. Kamata, A. Sihmizu, N. Ohtani, N. Kai, S. Takahashi,
W. Moriyama, K. Kugimiya, S. Miyazaki, T. Hirose, H. Meguro,
K. Hatakeyama, K. Simizu, and R. Shirota, “High-density (4.4F 2 )
tial and the erase voltage to be in agreement on the gate NAND technology using super-shallow channel profile (SSCP) engi-
neering,” ISSCC Dig. Tech. Papers, pp.775–778, 2000.
length. As indicated by Fig. 11, the time required for the
[4] H. Pein and J.D. Plummer, “Performance of the 3-D PENCIL flash
floating body potential and drain/source potential to achieve EPROM cell and memory array,” IEEE Trans. Electron Devices,
the equal value becomes faster by shrinking the gate length. vol.42, no.42, pp.1982–1991, Nov. 1995.
This phenomenon explains that FC-SGT Flash memory can [5] M. Momodomi, R. Kirisawa, R. Nakayama, S. Aritome, T. Endoh,
shift quickly to the mode of electron emission over the Y. Itoh, Y. Iwata, H. Oodaira, T. Tanaka, M. Chiba, R. Shirota, and
whole channel area by shrinking the gate length. In previous F. Masuoka, “New device technologies for 5 V-only 4 Mb EEPROM
with NAND structured cell,” IEDM Tech. Dig., pp.412–415, 1988.
work [1], it has been reported that injection and emission
[6] T. Endoh, M. Hioki, H. Sakuraba, M. Lenski, and F. Masuoka, “Float-
of electrons over the whole channel area make it possible ing channel type SGT Flash memory,” ECS, International Meeting,
to improve the endurance characteristic in Flash memory. vol.99-2, p.1323, 1999.
As mentioned above, by shrinking the gate length, FC-SGT [7] M. Hioki, T. Endoh, H. Sakuraba, M. Lenski, and F. Masuoka, “An
Flash memory can not only overcome the difficulty on fab- analysis of program and erase operation for FC-SGT Flash memory
rication but improve the endurance characteristic. cells,” International Conference on Simulation of Semiconductor Pro-
cesses and Devices, pp.116–117, 2000.
[8] SILVACO Int., Device Simulation Software, ATLAS 5.2.0.R.
5. Conclusions

This paper analyzes program and erase mechanisms for

Floating Channel type Surrounding Gate Transistor (FC-
SGT) Flash memory cells for the first time. In FC-SGT Masakazu Hioki received the B.S., M.S.
Flash memory cell, control gate, floating gate, drain and and Ph.D. degrees in electrical engineering from
source is arranged vertically on the substrate. The body Tohoku University in 1998, 2000 and 2003 re-
region is isolated from the substrate by the bottom source spectively. Since 2003, he has been a mem-
ber of the Electroinfomatics Group, Nanoelec-
region. The cell is programmed by applying a high positive
tronics Research Institute, AIST, Japan. His re-
voltage to the control gate electrode with drain and source search interests include reconfigurable systems,
electrodes grounded. Erasing is performed by applying a thier circuit technologies, circuit applicatoins
high positive voltage to the drain and source electrodes with of four-terminal XMOS transistors, and non-
the control gate electrode grounded. The physical models volatile memory devices.
for program and erase operations in FC-SGT Flash mem-
ory cell are developed. During programming, the surface
potential of the floating body region is at 0.5 V because an Hiroshi Sakuraba was born in Akita, Japan,
inversion layer builds up, resulting in FN injection of elec- in 1961. He received his B.E., M.E., and Ph.D.
degrees in electrical engineering from Tohoku
trons to the floating gate over whole channel area. During University in 1987,1989 and 1992 respectively.
erasing, the surface potential of the floating body region at- Since 1992, he had been a research associate of
tains the same potential as of drain and source because of the Faculty of Engineering of Tohoku Univer-
accumulation of holes at the surface of floating body region sity, where he had been engaged in the research
caused by impact ionization and band-to-band tunneling, re- of the surface reaction mechanism of the semi-
conductor crystal growth. Since 1996, he joined
sulting in FN emission of electrons from the floating gate
in Research Institute of Electrical Communica-
over the whole channel region. Program and erase opera- tion Tohoku University. His current concern is
tions based on the developed physical models are simulated the device and process technology of ULSI. Dr. Sakuraba is a member of
by utilizing the two dimensional device simulator. Program the Institute of Electrical and Electronics Engineers (IEEE).
HIOKI et al.: AN ANALYSIS OF PROGRAM AND ERASE MECHANISMS FOR FC-SGT FLASH MEMORY CELLS
1635

Tetsuo Endoh was born in Tokyo, Japan,

in 1962. He received the B.S. degree in physics
from the University of Tokyo, Tokyo, Japan, in
1987. He received the Ph.D. degree in electronic
engineering from Tohoku University, Sendai,
Japan in 1995. He joined the Research and De-
velopment Center, Toshiba Corporation, Kawa-
saki, Japan, in 1987, where he was engaged in
the research on CMOS device design. Since
1988, he was engaged in the research on high
density Flash Memory and the reliability of
Flash Memory at the ULSI Research Laboratories, the Research and Devel-
opment Center, Toshiba Corporation, Kawasaki, Japan. He was a lecturer
of the Research Institute of Electrical Communication, TOHOKU Univer-
sity, Sendai, Japan, in 1995. Since 1997, he has been an associate professor
at Research Institute of Electrical Communication (RIEC). He has been
engaged in the research on the CMOS device design, low power and high
speed logic technology, clean room technology. Dr. Endoh is a member of
the Institute of Electrical and Electronics Engineers (IEEE), and the Japan
Society of Applied Physics.

Fujio Masuoka was born on May 8, 1943

in Gunma, Japan. He received his B.E., M.E.
and Ph.D. degrees in electrical engineering from
Tohoku University in 1966, 1968, and 1971, re-
spectively. In 1971, he joined TOSHIBA re-
search and development center, where in 1972
he developed Stacked Gate Avalanche injection
type MOS READ Only Memory (SAMOS) for
the first time in the world. That is the origin
of current EPROM and Flash Memory. In 1976
he developed Dynamic memory cell with dou-
ble poly-Si structure. In 1977 he moved to TOSHIBA semiconductor busi-
ness division, where he developed 1Mbit DRAM and in 1980 he applied
Flash Memory patent for the first time. In 1984 he presented Flash Mem-
ory for the first time at IEDM, and in 1985 at ISSCC. In 1987 he returned
to TOSHIBA research and development center, where he began to develop
NAND structured Flash Memory, which was presented in 1987 at IEDM.
He moved to TOHOKU UNIVERSITY as a professor in 1994. Dr. Ma-
suoka is a fellow of the IEEE. He has 170 registered patents in U.S.A.,
Germany, France and Great Britain, 100 registered patents in Japan, and
71 pending patents. He authored and co-authored approximately 150 pa-
pers. He received the 1997 “IEEE Morris N. Liebmann Memorial Award,”
and the 2000 “The Ichimura Prizes in Industry—Main Prize” for the de-
velopment of Flash-Memory. Dr. Masuoka is a member of the Institute of
Electrical and Electronics Engineers (IEEE).

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