Design of Improved Phase Frequency Detector and Charge-Pump for

a 12-18 GHz CMOS PLL

Yupeng Fu1, Lianming Li1*, Dongming Wang1*
1
National Mobile Communication Research Lab, Southeast University, Nanjing 210096, China
* Email: [email protected], [email protected]

Abstract headroom purpose, respectively. As a result, a high speed

To improve the PLL in-band phase noise and setting time, LSF is needed in between the PFD and CP. To address
improved nonlinear phase frequency detector (PFD), in-band phase noise and setting time issues, as to be
charge-pump (CP) and level shifter (LSF) circuits are discussed shortly, a nonlinear PFD, a high speed LSF
proposed in this paper, achieving larger than 19V/ns and low noise CP structure are employed.
switching slew rate from 0.15 to 1.65V of LSF and less 2.1 A low power nonlinear PFD
than 2.2 pA/ Hz noise density at 1MHz offset of CP, In the PLL, PFD detects phase and frequency difference
respectively. With a 65nm CMOS process, a 12-18GHz between reference and feedback signal and produces up
phased-locked loop is designed, achieving in-band phase or down pulse signal for the CP. During the PLL locking
noise of -103.5dBc/Hz @100KHz, settling time of lower process, initially there is a large frequency and phase
than 4us, respectively. difference. With the traditional linear PFD, it cannot
contribute enough loop gain to fast track the reference
1. Introduction phase, as the PLL works in capture range instead of
To achieve better signal selectivity and low bit error rate, locking-in. Accordingly, the traditional linear PFD
the phase noise of the phased locked loop (PLL) should typically increases the PLL lock-in time. As shown in
be good enough. For high-order QAM modulation Fig. 2, in this design a nonlinear PFD structure is used[1],
communication and radar applications, a low in-band which modifies feedback reset signal of DFF1 with
phase noise is very important. Considering the PLL DN_1.2 and Fref, and that of DFF2 with UP_1.2 and Fdiv.
structure, its in-band phase noise is typically limited by D Q
UP_1.2 f ( )
several critical components, like PFD and CP. DFF1 1
In this paper, to address above issues and achieve good Fref
clk Q
UPB_1.2

A
in-band phase noise, considering Ku band (12-18GHz)
rst
0.5
communication and radar systems applications, the
design of a nonlinear low power PFD, a low noise -2 - O  2 
current steering CP and a high speed differential LSF are Fdiv
rst
DNB_1.2 B
elaborated. Together with a LC VCO and frequency
clk Q
-0.5
DFF2

divider, the PLL achieves a -103.5dBc/Hz @100KHz DN_1.2

in-band phase noise and lower than 4us settling time.

D Q
-1
The paper is organized as follows. Section 2 presents the Figure 2. Schematic and transfer function of the
design details of PFD, LSF and CP. Section 3 describes nonlinear PFD
the simulation results. The conclusions are drawn in With above characteristics, as a function of input signal
Section 4. (i.e. input signal Fref and the feedback signal Fdiv) phase
2. Circuit Design difference, the output voltage can be derived as follows:
1  2    
CP  1

Fin LPF VCO f ( )          (1)
 2
Fout
PFD LSF

1     2
MMD Prescaler
Clearly, as shown in Fig. 2, with such transfer function
when phase difference between reference and feedback
Figure 1. Structure of the integer-N PLL signal is larger than |π|, PFD’s gain is set to 1, driving CP
As shown in Fig. 1, the 12-18GHz Integer-N PLL to charge LPF in half period of reference and improving
consists of PFD, CP, low-pass filter (LPF), VCO and PLL phase locking time.
prescaler and MMD etc. Note the supply voltage of the Note that the above PFD characteristic is achieved with
PFD and CP is 1.2V and 1.8V for high speed and voltage an assumption that both the duty cycle of Fref and Fdiv

978-1-5386-4441-6/18/$31.00 ©2018 IEEE

signal is 50%. However, the signal intersection A and B Vb +1.2V. In contrast, during above operations, Vin is 0V
changes with the input signal duty cycle. With when Vip is 1.2V. Accordingly, transistor M1 is switched
simulations, it is proved this doesn’t affect the PLL off, and voltage at node A, Va, will be around 1.8V.
phase locking. When Vin and Vip reverse, node A will be pulled down to
2.2 High speed differential LSF Va-1.2V with M5 and C1. In brief, with this circuit
As discussed before, as an interface between the 1.2V structure, the pulling up and pulling down speed are
PFD and 1.8V CP, the LSF converts the complementary enhanced substantially, suppressing its phase noise
UP_1.2/UPB_1.2, DN_1.2/DNB_1.2 signals to drive the CP[4]. contribution.
In the traditional LSF[2], a common-source driving stage 2.3 Low-noise current steering CP
and a cross-coupled load stage are used, introducing For CP circuit, typically its charging sharing effect and
several disadvantages such as high static power noise contribute to the PLL reference spur and in-band
consumption, low speed and large output phase phase noise. In this design, to address above issues, as
difference. Accordingly, the switching speed and phase shown in Fig. 4, an improved low noise current steering
difference of the CP will be worsened, reducing PLL charge-pump circuit is presented, making its output
in-band phase noise and reference spur performance. To voltage stable in locking-in range to decrease the PLL
solve this issue, zener diode and bootstrap capacitor reference spur. To improve the matching of charging and
techniques are used [3]. However, for CMOS process, discharging current, two operational amplifiers and
the zener diode is not well supported. self-biasing current mirror are used[4]. Here to improve
1.8V the dynamic range of the output voltage and avoid the
current leakage, two high gain rail-to-rail input/output
1.2V
M5
M7 M8
M6
1.2V
error amplifiers, OPA1 and OPA2, are used to force
C1 C2
voltage V1, V0 and Vf equal. To be specific, the working
Vin
Inv1
A B

Inv2
Vip
current of OPA2 follows Id of CP, allowing OPA2 fast
M3 M4 charging the capacitor C0 to establish the feedback loop
of the CP at any start-up situations. In this way, the loop
Outp Outn
reliability is increased. Note with capacitor Cs, the
M2
M1
domain pole of the loop from Vf to the output of OPA1 is
introduced. In the conventional CP, a compensation
Figure 3. Schematic of the high-speed LSF capacitor is used to introduce a pole, however it should
As shown in Fig. 3, the purposed LSF consists of two be large. In this work, to avoid the Miller effect of
input pairs (M1/M3, M2/M4), a cross-coupled latch (M7 transistor M7, transistor M10 is reused as a
and M8), a diode connected pair (M5 and M6) and two compensation resistance, which satisfies the following
bootstrap capacitor pairs (C1 and C2). In particular, the relationship:
diode connected pair (M5/M6) works as variable 1
 Ron10 (2)
resistances, which provide charging or discharging gm7
current for the bootstrap capacitor. In this way, phase margin of the negative feedback loop
Below a brief introduction to the circuit working path is larger than that of the positive feedback path, thus
mechanism will be given. With the two input transistor improving the CP stability.
pairs, the input signal (Vin and Vip) from 1.2V voltage VDD

domain is sensed and amplified into output signal (Outp M7

Id
M5
and Outn) in 1.8V voltage domain. Then the Outp and Cs

Outn signal is pulled up with the cross-coupled latch. In M10

UPB UP
M1 M2
particular, when Vip is 1.2V (i.e. high logic in 1.2V GND OPA1

voltage domain), transistor M2 behaves a small Vf V0

OPA2
V1

resistance, while transistor M4 and M6 a large resistance. I_BIAS

M11
DNB DN Cl
C0 M3 M4
Accordingly, the circuit node B will be self-biased at a VDD

certain voltage level Vb (in between 1.2 and 1.8V). M9 M8

M6
Accordingly, the capacitor C2 will be charged with Cp

transistor M6, as the output voltage of inverter Inv2 is 0V, GND

establishing an initial operating voltage state. When Figure 4. Schematic of low-noise CP

input signal Vin and Vip reverse (i.e. Vin is 1.2V and Vip 3. Simulation Results
0V), capacitor C2 cannot be discharged through both M4 Together with a typical cross coupled LC-VCO, a
and M6 in a very short moment. Moreover, the output Ku-band 12-18GHz PLL is implemented in a 65-nm
voltage of inverter Inv2 becomes high (i.e. 1.2V), and the CMOS process. Fig. 9 shows the full PLL layout, its
voltage at node B will be bootstrapped by capacitor C2 to core area is only 0.7mm × 0.8mm. Thanks to the CMOS
logic operation, the nonlinear PFD consumes no static 0.8
power, while the LSF and CP consume 2~3.2mA from a 0.6

Vtune(V)
1.8V power supply with varying biasing current Id from 0.4
300 to 700uA. 0.2
Fig. 5 shows the post-layout simulation of the LSF. With 0.0

our proposed techniques, its phase delay is less than 0.0 4.0x10-78.0x10-71.2x10-61.6x10-6
Time(s)
200ps and the switching slew rate from 0.15 to 1.65V is
larger than 19V/ns. Figure 8. Simulated of VC and Phase noise of PLL
2.0 UP 2.0 UPB
SPB SP
1.5 1.5
Voltage(V)

Voltage(V)

1.0 1.0
0.5 0.5
0.0 0.0
10.0n 10.2n 10.4n 10.6n 10.8n 10.0n 10.2n 10.4n 10.6n 10.8n
Time(s) Time(s)

Figure 5. Input and output vlotage of LSF

Fig. 6 shows comparison between the simulated stability Figure 9. layout of the proposed PLL
information of the proposed CP (solid line) and that of 4. Conclusions
the conventional CP(dash line) with the same For Ku-band communication and radar applications, this
compensation capacitor. Clearly, when output voltage V1 paper presents design of a nonlinear PFD, a current
changes from 0.25 to 1.5V, its phase margin is always steering CP and a bootstrap capacitor based LSF
higher than 60 degree. Fig. 6 also shows the simulated circuits. To prove above techniques, a 12-18GHz PLL is
transient result of Vf, proving the proposed CP (solid line) realized in a 65nm CMOS process. Simulations
works more stably than the conventional one(dash line). indicate that a locking time of less than 4us, in-band
As shown in Fig. 7, when the output current of CP is phase noise of about -103.5dBc/Hz@100KHz are
varied from 300 to 700uA, its output noise density is realized. Clearly, the PLL achieves low in-band phase
increased linearly from 1 to 2.2 and from 0.9 to noise and fast locking performance.
1.4 pA/ Hz at 1MHz and 10MHz offset, respectivly. Acknowledgement
80 Proposed Proposed This work was supported by the National High-Tech
Phase Margin(Degree)

Conventional 0.6 Conventional

Project (863 Project) of China under Grant (No.
Voltage Vf(V)

60
0.4 2011AA010201 and No. 2011AA010202), National
40
0.2 Nature Science Foundation of China (No. 61306030,
20
0.0
61674037) and National Key R&D Program of China
0 (No. 2016YFC0800400).
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 100n 200n 300n 400n
Voltage V1(V) Time(s) References
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Figure 6. Phase-Margin and Voltage of Vf in CP
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