Anna University

Solved Question Papers

B.E./B.Tech. 5th Semester

Electrical and Electronics
Engineering

ECE_Semester-V_FM.indd iii 7/19/2012 10:32:36 AM

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 ACKNOWLEDGEMENTS

Ms H. Radhika
Department of Electronics and Communication
Engineering
Rajalakshmi Engineering College, Chennai

Mr R. Prasanna
Department of Electrical and Electronics Engineering
A. V. C College of Engineering, Mayiladuthurai

Mr A. Murugan
  Department of Electrical and Electronics Engineering
Adhiparasakthi College of Engineering, Chennai

Mr Vijay
Department of Information Technology
St. Joseph College of Engineering, Chennai
 
Ms Jayasree
Department of Electrical and Electronics Engineering
Rajalakshmi Engineering College, Chennai

Ms Vimala
Department of Electrical and Electronics Engineering
  St. Joseph College of Engineering, Chennai

Ms G. Jeyalakshmi
Department of Electronics and Communication
Engineering
DMI College of Engineering, Chennai
 

 
 Semester-V
Power
Electronics

EEE_Semester-V_Ch05.indd 1 4/19/2014 3:25:42 PM

 The aim of this publication is to supply information taken from sources believed to be valid and
reliable. This is not an attempt to render any type of professional advice or analysis, nor is it to
be treated as such. While much care has been taken to ensure the veracity and currency of the
information presented within, neither the publisher nor its authors bear any responsibility for
any damage arising from inadvertent omissions, negligence or inaccuracies (typographical or
factual) that may have found their way into this book.

EEE_Sem-VI_Chennai_FM.indd iv 12/7/2012 6:40:43 PM

 B.E./B.Tech. DEGREE EXAMINATION,
NOV/DEC 2013
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions
PART A (10 × 2 = 20 marks)
1. List the various forced communication techniques used to turn off SCR.

2. What is a snubber circuit?

3. Mention the disadvantages of dual converter with circulating current

mode of operation.

4. A single phase full converter feeds power to RLE load with R = 6Ω, and
E = 60 V. The load inductance value is very large so as to maintain the
load current continuous and ripple free. The ac source voltage is 230 V
and 50 Hz. Find the average value of the output voltage for a firing angle
delay of 50°.

5. What do you mean by time ratio control?

6. What is a dc chopper?

7. What is the advantage of 120° mode of inverter operation over 180°

mode?

8. List the various advantage of using PWM control to inverters?

9. What is the matrix converter?

10. Enumerate some of the industrial applications of a cycloconverter.

EEE_Semester-V_Ch05.indd 3 4/19/2014 3:25:42 PM

 5.4 B.E./B.Tech. Question Papers

PART B (5 × 16 = 80 marks)

11. (a) (i) Draw and explain the switching characteristics of SCR. (8)
(ii) Discuss the working of a complementary commutation circuit of
SCR with a neat circuit diagram and waveforms. (8)
Or
(b) Describe the basic structure of IGBT and explain its working.
Give its equivalent circuit and explain the turn ON and turn OFF
processes. (16)
12. (a) Describe the working of a single phase full converter in the rectifier
mode with RL load. Discuss how one pair of SCRs is commutated
by an incoming pair of SCRs. Illustrate your answer with the
waveforms of source voltage, load voltage and source current.
Assume continuous conduction. Also derive the expressions for
average and rms output voltage. (16)
Or
(b) (i) A 3 – phase full converter charges a battery from a three – phase
supply of 230 V, 50 Hz. The battery emf is 200 V and its internal
resistance is 0.5 Ω. On account of inductance connected in series
with the battery, charging current is constant at 20 A. Compute
the firing angle delay and supply power factor. (8)
(ii) Describe briefly the working of Dual converter with a neat
circuit diagram. (8)
13. (a) (i) A de battery is charged from a constant de source of 220 V
through a chopper. The de battery is to be charged from its
internal emf of 90 V to 122 V. The battery has internal resistance
of 1Ω. For a constant charging current of 10A, compute the
range of duty cycle. (8)
(ii) Explain with a neat circuit diagram one of the configurations of
SMPS. (8)
Or
(b) (i) Explain the principle of working of a step up chopper with neat
circuit diagram and necessary waveforms. Derive the expression
for its average output voltage. (10)
(ii) Write short note on resonant switching. (6)

EEE_Semester-V_Ch05.indd 4 4/19/2014 3:25:42 PM

 Power Electronics (Nov/Dec 2013) 5.5

14. (a) Discuss the principle of working of a three phase bridge inverter
with an appropriate circuit diagram. Draw the output phase and line
voltage waveforms on the assumption that each thyristor conducts
for 180° and resistive load is star connected. The sequence of firing
of various SCR should also be indicated. (16)
Or
(b) Write short note on the following:
(i) Sinusoidal pulse width modulation as applied to inverters
(ii) Current source inverters. (8 + 8)
15. (a) Describe the basic principle of working of 1ϕ – 1ϕ step down
cycloconverter for a bridge type converter. Assume both
discontinuous and continuous conduction and draw the load current
and load voltage waveforms for both the cases. Mark the conduction
of various thyristors. (16)
Or
(b) Write short note on the following:
(i) Integral cycle control
(ii) Multistage sequence control
(iii) Step up cycloconverter
(iv) Matrix converter. (4 + 4 + 4 + 4)

EEE_Semester-V_Ch05.indd 5 4/19/2014 3:25:42 PM

 Solutions
Nov-Dec 2013

PART B

14. b. ii. In the previous sections the inverters are fed from a voltage source and the load current is
forced to fluctuate from positive to negative, and vice versa. To cope with inductive loads, the power
switches with freewheeling diodes are required, whereas in a current-source inverter (CSI), the input
behaves as a current source. The output current is maintained constant irrespective of load on the inverter
and the output voltage is forced to change. The circuit diagram of a single-phase transistorized inverter is
shown in Figure 6.42a. Because there must be a continuous current flow from the source, two switches
must always conduct—one from the upper and one from the lower switches. The conduction sequence is
12, 23, 34, and 41 as shown in Figure 6.42b. The switch states are shown in Table 6.4. Transistors Q1, Q4 in
Figure 6.42a act as the switching devices S1, S4, respectively. If two switches, one upper and one lower,
conduct at the same time such that the output current is ± IL, the switch state is 1; whereas if these switches
are off at the same time, the switch state is 0. The output current waveform is shown in Figure 6.42c. The
diodes in series with the transistors are required to block the rever se voltages on the transistors.
When two devices in different arms conduct, the source current IL flows through the load. When two
devices in the same arm conduct, the source current is bypassed from the load. The design to the current
source is similar to Example 5.10. From Eq. (6.28), the load current can be expressed as


4I L n
i0  
n 1,3,5, n
sin
2
sin n(t ) (6.90)

Figure 6.43a shows the circuit diagram of a three-phase current-source inverter. The waveforms for gating
signals and line currents for a Y-connected load are shown in Figure 6.43b. At any instant, only two
thyristors conduct at the same time. Each device conducts for 120°. From Eq. (6.16a), the instantaneous
current for phase a of a Y-connected load can be expressed as


4I L n  
ia  
n 1,3,5, n
sin
3
sin n  t  
 6
(6.91)

From Eq. (6.21a), the instantaneous phase current for a delta-connected load is given by

4I L  n 
ia   sin   sin (nt ) for n = 1, 3, 5, … (6.92)
n 1 3n  3 

15. (b) (iv) The matrix converter uses bidirectional fully controlled switches for direct conversion from
ac to ac. It is a single-stage converter that requires only nine switches for three-phase to three-phase
conversion [5–7]. It is an alternative to the double-sided PWM voltage source rectifier inverter. The circuit
diagram of the three-phase to three-phase (3ø – 3ø) matrix converter is shown in Figure 11.24a [8, 9]. The
nine bidirectional switches are so arranged that any of three input phases could be connected to any output
phase through the switching matrix symbol in Figure 11.24b.Thus, the voltage at any input terminal may be
made to appear at any output terminal or terminals whereas the current in any phase of the load may be
drawn from any phase or phases of the input supply.An ac input LC filter is normally used to eliminate
harmonic currents in the input side and the load is sufficiently inductive to maintain continuity of the output
currents [10].The term matrix is due to the fact that it uses exactly one switch for each of the possible
connections between the input and the output.The switches should be controlled in such a way that, at any
time,one and only one of the three switches connected to an output phase must be closed to prevent short
circuiting of the supply lines or interrupting the load current flow in an inductive load.With these
constraints, there are 512(=29) possible states of the converter, but only 27 switch combinations are allowed
to produce the output line voltages and input phase currents.With a given set of input three-phase voltages,
any desired set of three-phase output voltages can be synthesized by adopting a suitable switching strategy
[11, 12].
The matrix converter can connect any input phase (A, B, and C) to any output phase (a, b, and c) at any
instant.When connected, the voltages van, vbn, vcn at the output terminals are related to the input voltages
vAN, vBN, vCN as

Van   S Aa S Ba SCa  VAN 

V    S S Bb SCb  VBN  (11.47)
 bn   Ab
Vcn   S Ac S Bc SCc  VCN 

vAN
iA A Matrix Converter
S Aa S Ab S Ac vAo van
vBN S Aa
iB B S Ab S Ba
N
S Ba S Bb S Bc
vCN
iC C S AcS Ca

S Ca S Cb S Cc vBo vbn
3 Input Input Filter S Bb
ia ib ic
a b c
3 S Cb S Bc
Inductive van vbn vcn S Cc
Load vCo vcn

n
( a) C onver ter ci r cui t ( b) S wi tchi ng matr i x

FIGURE 11.24
(a) Matrix (3ø – 3ø) converter circuit with input filter (b) Switching matrix symbol for converter.

where SAa through SCc are the switching variables of the corresponding switches. For a balanced linear Y-
connected load at the output terminals, the input phase currents are related to the output phase currents by

iA   S Aa S Ab S Ac  ia 
i    S S Bb S Bc  ib  (11.48)
 B   Ba
iC   SCa SCb SCc   ic 

where the matrix of the switching variables in Eq. (11.48) is a transpose of the respective matrix in Eq.
(11.47). The matrix converter should be controlled using a specific and appropriately timed sequence of the
values of the switching variables, which result in balanced output voltages having the desired frequency
and amplitude, whereas the input currents are balanced and in phase with respect to the input voltages.
However, the maximum peak-to-peak output voltage cannot be greater than the minimum voltage
difference between two phases of the input. Regardless of the switching strategy, there is a physical limit
on the achievable output voltage and the maximum voltage transfer ratio is 0.866.The control methods for
matrix converters must have the ability for independent control of the output voltages and input
currents.Three types of methods [12] are commonly used: (1) Venturini method that is based on a
mathematical approach of transfer function analysis [5], (2) PWM, and (3) space vector modulation [3].
The matrix converter has the advantages of (1) inherent bidirectional power flow, (2) sinusoidal input–
output waveforms with moderate switching frequency, (3) possibility of compact design due to absence of
dc-link reactive components and (4) controllable input PF independent of the output load current. However,
the practical applications of the matrix converters are very limited. The main reasons are (1) nonavailability
of the bilateral fully controlled monolithic switches capable of high-frequency operation (2) complex
control law implementation (3) an intrinsic limitation of the output–input voltage ratio and (4) commutation
and protection of the switches.With space vector PWM control using overmodulation, the voltage transfer
ratio may be increased to 1.05 at the expense of more harmonics and large filter capacitors [13].
 B.E./B.Tech. DEGREE EXAMINATIONS,
MAY/JUNE 2013
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions.
PART A (10 ×2 = 20 marks)
1. What is the limitation of high frequency operation of a power electronic
device?

2. What is the use of snubber circuit?

3. What is displacement factor for two pulse converter?

4. What is current turn-off time for single phase full converter?

5. What are the control strategies for chopper circuit?

6. What is the need for resonant converter?

7. In a CSI, if frequency of output voltage is ‘f’ Hz, what is the frequency

of voltage input to CSI?

8. What is space vector?

9. What are the types of ac voltage controllers?

10. What is matrix converter?

PART B (5 × 16 = 80 marks)

11. (a) (i) Snubber circuit for an SCR should primarily consists of
capacitor only. But in practice it resistor is used in series with
the capacitor. Why? Discuss. (8)

EEE_Semester-V_Ch05.indd 6 4/19/2014 3:25:42 PM

 Power Electronics (May/June 2013) 5.7

(ii) Sketch the dynamic characteristics of a thyristor during its

turn-ON and turn-OFF process. Discuss briefly the nature of
these curves. (8)
(or)
(b) Explain various types of commutation circuits for SCR. (16)
12. (a) (i) A single phase bridge converter is utilized to produce regulated
DC output voltage. The input voltage is 230V and the load
current is 8A for a firing and of 30°.
(1) Calculate the dc output voltage. (4)
(2) Calculate the dc output voltage and currents if a
freewheeling diode is used at the output for the same firing
angle as in (1). (4)
(ii) Explain single phase half wave rectifier circuit with RL. Load
and freewheeling diode. (8)
(or)
(b) (i) Discuss the effect of series inductance on the performance of
single phase full converter indicating clearly the conduction
of various thyristors during one cycle. (8)
(ii) Describe the working of 1ø dual converter in two modes. (8)
13. (a) (i) A type – ‘A’ Chopper has supply voltage Vs = 230 V and duty
cycle of (A) 0.4 and (B) 0.6. For these duty cycles, calculate.
(1) average and rms value of output voltage (3)
(2) output power for R load (3)
(3) ripple factor (2)
(ii) Explain the operation of stepup chopper and derive an expression
for its output voltage. (8)
(or)
(b) (i) Draw and explain the block schematic of SMPS and mention its
advantages over linear power supply. (8)
(ii) Draw the power circuit diagram of a buck regulator and explain
its operation with equivalent circuit for different modes and
waveforms. (8)

EEE_Semester-V_Ch05.indd 7 4/19/2014 3:25:42 PM

 5.8 B.E./B.Tech. Question Papers

14. (a) With heat diagram and waveforms explain 3ϕ VSI using transistors
operating in 120° conduction made. Also obtain the expression for
rms value of output voltage. (16)
(or)
(b) (i) Explain Multiple Pulse Width Modulation. (8)
(ii) Explain Sinusoidal Pulse Width Modulation. (8)
15. (a) (i) Explain about multi-stage sequence control of voltage
controllers. (8)
(ii) Explain Multiple Pulse Width Modulation. (8)
(or)
(b) (ii) Explain the principle of integral cycle control. (8)
(ii) A single phase voltage controller has input voltage oυ 230V, 50
Hz and a load of R = 15Ω. For 6 cycles ON and 4 cycles OFF,
determine.
(1) rms output voltage (3)
(2) input pf and (3)
(3) average and rms thyristor currents (2)

EEE_Semester-V_Ch05.indd 8 4/19/2014 3:25:42 PM

 Solutions
May/June 2013

PART B

11. (a) (i) S1 t = 0, T1 dv/dt

dv/dt
Cs, T1 Rs,
With an RC circuit known as a snubber circuit, the voltage across the thyristor rises exponentially as
shown in Figure 7.33c and the circuit dv/dt can be found approximately from

dv 0.632Vs 0.632Vs
  (7.15)
dt  Rs Cs

The value of snubber time constant τ = Rs Cs can be determined from Eq. (7.15) for a known value of dv/dt.
The value of Rs is found from the discharge current ITD.

Vs
Rs  (7.16)
ITD

It is possible to use more than one resistor for dv/dt and discharging, as shown in Figure 7.33d. The dv/dt is
limited by R1 and Cs. (R1 + R2) limits the discharging current such that
Vs
ITD  (7.17)
R1  R2

vAK
Vs
A
S1 S1 0.632V s
Cs
Cs T1 T1
Vs vAK Vs
Rs

k t
0 t
(a) (b) (c)

Ls

S1 S1 Cs
Ds R2 T1
Rs
T1
Vs Vs
R
R1

Cs L

(d) (e)

FIGURE 7.33
dv/dt protection circuits.
The load can form a series circuit with the snubber network as shown in Figure 7.33e. From Eqs. (2.40) and
(2.41), the damping ratio δ of a second-order equation is

 Rs  R Cs
  (7.18)
0 2 Ls  L

where Ls is the stary inductance, and L and R are the load inductance and resistance, respectively.

To limit the peak voltage overshoot applied across the thyristor, the damping ratio in the range of 0.5
to 1.0 is used. If the load inductance is high, which is usually the case, Rs can be high and Cs can be small
to retain the desired value of damping ratio. A high value of Rs reduces the discharge current and a low
value of Cs reduces the snubber loss. The circuits of Figure 7.33 should be fully analyzed to determine the
required value of damping ratio to limit the dv/dt to the desired value. Once the damping ratio is known, Rs
and Cs can be found. The same RC network or snubber is normally used for both dv/dt protection and to
suppress the transient voltage due to reverse recovery time. The transient voltage suppression is analyzed in
section 18.6.

11. (a) (ii) Cj2

d (q j 2 ) d dC j 2 dV j 2
ij2   (C j 2V j 2 )  V j 2  C j2
dt dt dt dt
<??> Cj2 Vj2 J2, qj2
dv/dt
ij2
ICBO1 ICBO2.
ICBO1 ICBO2
(α1 + α2)
dv/dt

THYRISTOR TURN-ON

A thyristor is turned on by increasing the anode current. This can be accomplished in one of the following
ways.

Thermals. If the temperature of a thyristor is high, there is an increase in the number of electron–
hole pairs, which increases the leakage currents. This increase in currents causes α1 and α2 to increase. Due
to the regenerative action, (α1 + α2) may tend to be unity and the thyristor may be turned on. This type of
turn-on may cause thermal runaway and is normally avoided.

Light. If light is allowed to strike the junctions of a thyristor, the electron–hole pairs increase; and
the thyristor may be turned on. The light-activated thrystiros are turned on by allowing light to strike the
silicon wafers.

High voltage. If the forward anode-to-cathode voltage is greater than the forward breakdown
voltage VBO, sufficient leakage current flows to initiate regenerative turn-on. This type of turn-on may be
destructive and should be avoided.

dv/dt. It can be noted from Eq. (7.6) that if the rate of rise of the anode–cathode voltage is high, the
charging current of the capacitive junctions may be sufficient enough to turn on the thyristor. A high value
of charging current may damage the thyristor; and the device must be protected against high dv/dt. The
manufacturers specify the maximum allowable dv/dt of thyristors.
 Gate current. If a thyristor is forward biased, the injection of gate current by applying positive gate
voltage between the gate and cathode terminals turns on the thyristor. As the gate current is increased, the
forward blocking voltage is decreased, as shown in Figure 7.7.

Figure 7.8 shows the waveform of the anode current, following the application of gate signal. There is
a time delay known as turn-on time ton between the application of gate signal and the conduction of a
thyristor. ton is defined as the time interval between 10% of steady-state gate current (0.1IG) and 90% of the
steady-state thyristor on-state current (0.9IT). ton is the sum of delay time td and rise time tr.td is defined as
the time interval between 10% of gate current (0.1IG) and 10% of thyristor on-state current (0.1IT). tr is the
time required for the anode current to rise from 10% of on-state current (0.1IT) to 90% of on-state current
(0.9IT). These times are depicted in Figure 7.8.
The following points should be considered in designing the gate control circuit:

1. The gate signal should be removed after the thyristor is turned on. A continuous gating signal would
increase the power loss in the gate junction.
2. Although the thyristor is reversed biased, there should be no gate signal; otherwise, the thyristor may
fail due to an increased leakage current.

IT

I G3 I G2 I G1
I G3 I G2 I G1
IL IG 0
IH
V AK
0
V3 V2 V1 V BO
V1 V2 V3

FIGURE 7.7
Effects of gate current on forward blocking voltage.

iT
IT
0.9 I T

0.1 I T
0 t
iG
IG

0.1 I G
0 t
td tr

ton
FIGURE 7.8
Turn-on characteristics.

3. The width of gate pulse tG must be longer than the time required for the anode current to rise to the
holding current value IH. In practice, the pulse width tG is normally made more than the turn-on time ton
of the thyristor.
<??>J2 CJ2 = 20 pF
dv/dt

Cj2 = 20 pF iJ2 = 16mA. d(CJ2)/dt = 0, dv/dt

dv i j 2 16  103
   800 V/ s
dt C j 2 20  1012
THYRISTOR TURN-OFF

A thyristor that is in the on-state can be turned off by reducing the forward current to a level below the
holding current IH. There are various techniques for turning off a thyristor. In all the commutation
techniques, the anode current is maintained below the holding current for a sufficiently long time, so that
all the excess carriers in the four layers are swept out or recombined.
Due to two outer pn-junctions, J1 and J3, the turn-off characteristics would be similar to that of a diode,
exhibiting reverse recovery time trr and peak reverse recovery current IRR. IRR can be much greater than the
normal reverse blocking current IR. In a line-commutated converter circuit where the input voltage is
alternating as shown in Figure 7.9a, a reverse voltage appears across the thyristor immediately after the
forward current goes through the zero value. This reverse voltage accelerates the turn-off process, by
sweeping out the excess carriers from pn-junctions J1 and J3. Equations (7.6) and (7.7) can be applied to
calculate trr and IRR.
 v
T 1 on
Vm

0 t
2
iT
Leakage
T1 current
iT
0 t

V AK I RR
vAK trr tr
v
RL 0 t
2

tq
(a) Line-commutated thyristor circuit

v T 2 on
Vs

0 t
iT V0 di
Im Im
Lm dt

0 t
vAK Leakage
current
iT T 1 vAK Vs

Lm Im
L 0 t
Vs V0 T2 o
a
Dm d Vo
C trr trc

tq
(b) Forced-commutated thyristor circuit
FIGURE 7.9
Turn-off characteristics.

The inner pn-junction J2 requires a time known as recombination time trc to recombine the excess
carriers. A negative reverse voltage would reduce this recombination time. trc is dependent on the
magnitude of the reverse voltage. The turn-off characteristics are shown in Figure 7.9a and b for a line-
commutated circuit and forced-commutated circuit, respectively.
The turn-off time tq is the sume of reverse recovery time trr and recombination time trc. At the end of
turn-off, a depletion layer develops across junction J2 and the thryistor recovers its ability to withstand
forward voltage. In all the commutation techniques, a reverse voltage is applied across the thyristor during
the turn-off process.
Turn-off time tq is the minimum value of time interval between the instant when the on-state current
has decreased to zero and the instant when the thyristor is capable of withstanding forward voltage without
turning on. tq depends on the peak value of on-state current and the instantaneous on-state voltage.

Reverse recovered charge QRR is the amount of charge that has to be recovered during the turn-off
process. Its value is determined from the area enclosed by the path of the reverse recovery current. The
value of QRR depends on the rate of fall of on-state current and the peak value of on-state current before
turn-off. QRR causes corresponding energy loss within the device
12. (a) (ii)

v vL
Vm
vR iL R

vR
0 t
t2 2
vD

D1 io
Vm
R vR
vD
vp vs V m sin t vo 0 t
Dm 2
L vL D 1 conducts
Vm
(a) Circuit diagram (b) Waveforms

v vL
Vm
vR iL R

vR
0 t
2

D 1 conducts
Vm
vD D m conducts
0 t
2

Vm
(c) Waveforms

FIFUGRE 3.3
Half-wave rectifier with RL load.

Let us consider the circuit of Figure 3.1a with an RL load as shown in Figure 3.3a. Due to inductive
load, the conduction period of diode D1 will extend beyond 180° until the current becomes zero at ωt = π +
σ. The waveforms for the current and voltage are shown in Figure 3.3b. It should be noted that the average
vL of the inductor is zero. The average output voltage is

 
Vm   Vm
Vdc 
2 0
sin t d (t ) 
2
[ cos t ]
0

2Vm
 [1  cos(   )] (3.16)
2

The average load current is Idc = Vdc/R.

It can be noted from Eq. (3.16) that the average voltage (and current) can be increased by making σ =
0, which is possible by adding a freewheeling diode Dm as shown in Figure 3.3a with dashed lines. The
effect of this diode is to prevent a negative voltage appearing across the load; and as a result, the magnetic
stored energy is increased. At t = t1 = π/ω, the current from D1 is transferred to Dm and this process is called
commutation of diodes and the waveforms are shown in Figure 3.3c. Depending on the load time constant,
the load current may be discontinuous. Load current i0 is discontinuous with a resistive load and continuous
with a very high inductive load. The continuity of the load current depends on its time constant τ = ωL/R.
If the output is connected to a battery, the rectifier can be used as a battery charger. This is shown in
Figure 3.4a. For vs > E, diode D1 conducts. The angle α when the diode starts conducting can be found from
the condition

n :1 R D1

io

vp vs E

(a) Circuit

vs v m sin t

0
2 t

vs E
Vm E

0
t

Vm E

io
Vm E
R
0
2 t
(b) Waveforms
FIGURE 3.4
Battery charger.

14. b. (i) The harmonic content can be reduced by using several pulses in each half-cycle of out-put
voltage. The generation of gating signals (in Figure 6.13b) for turning on and off of transistors is shown in
Figure 6.13a by comparing a reference signal with a triangular carrier wave. The gate signals are shown in
Figure 6.13b. The frequency of reference signal sets the output frequency fo, and the carrier frequency fc
determines the number of pulses per half-cycle p. The modulation index controls the output voltage. This
type of modulation is also known as uniform pulse-width modulation (UPWM). The number of pulses per
half-cycle is found from

fc mf
 p (6.30)
2 fo 2
where mf = fc/fo is defined as the frequency modulation ratio.
 The instantaneous output voltage is vo = Vs(g1 – g4). The output voltage for single-phase bridge
inverters is shown in Figure 6.13c for UPWM.

14. b. (ii) δ


d t – t  MTs (6.35c)
 m 1 m

Ts = T/2p.
Ts vcr

Instead of maintaining the width of all pulses the same as in the case of multiple-pulase modulation, the
width of each pulse is varied in proportion to the amplitude of a sine wave evaluated at the center of the
same pulse [2]. The DF and LOH are reduced significantly. The gating signals as shown in Figure 6.15a
generated by comapring a sinusoidal reference signal with a triangular carrier wave of frequency fc. This
sinusoidal pulse-width modulation (SPWM) is commonly used in industrial applications. The frequency of
referenece signal fr determines the inverter output frequency fo; and its peak amplitude Ar controls the
modulation index M, and hen in turn the rms output voltage Vo. Comparing the bidirectional carrier signal
vcr with two sinusoidal reference signals vr and –vr shown in Figure 6.15a produces gating signals g1 and g4,
respectively, as shown in Figure 6.15b. The output voltage is vo = Vs(g1 – g4). However, g1 and g4 cannot be
released at the same time. The number of pulses per half-cycle depends on the carrier frequency. Within the
constraint that two transistors of the same arm (Q1 and Q4) cannot conduct at the same time, the
instantaneous output voltage is shown in Figure 6.15c. The same gating signals can be generated by using
unidirectional triangular carrier wave as shown in Figure 6.15d. It is easier to implement this method and is
preferable. The algorithm for generating the gating signals is similar to that for the uniform PWM in
Section 6.6.2, except the reference signal is a sine wave vr = Vr sin ωt, instead of a dc signal. The output
voltage is vo = Vs(g1 – g4).
 v Carrier signal vr
Ac
vcr
Ar
Reference
signal

(a) t
2

1
g1 fc

0 t
2
g4
(b) 0 t
2
vo
m
Vs

(c) 0 t
m 2
Vs

v
Ac
Ar
Ar
M
Ac
(d) 2 t
0

FIGURE 6.15
Sinusoidal pulse-width modulation.

The rms output voltage can be varied by varying the modulation index M. It can be observed that the
area of each pulse corresponds approximately to the area under the sine wave between the adjacent
midpoints of off periods on the gating signals. If δm is the width of mth pulse, Eq. (6.31) can be extended to
find the rms output voltage

1/ 2
 2p  
Vo  Vs   m  (6.36)
 m 1  
 B.E./B.Tech. DEGREE EXAMINATION,
NOV/DEC 2012
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A (10 × 2 = 20 marks)
1. Differentiate the ordinary transistors and power transistors.

2. Define GTO.

3. Why we need three phase controlled rectifiers?

4. What is the input power factor value of single phase semi-converters?

5. Draw the power circuit of step-down chopper with RL load.

6. What is meant by time ratio control?

7. Mention the limitation of the series inverters.

8. What are the different types of PWM techniques?

9. What is the necessity of the UPS and draw its block diagram?

10. What are the requirements of microcontroller based system?

PART B (5 × 16 = 80 marks)
11. (a) (i) A series thyristor strings with ratings 3 KV and 750 A uses
thyristors with 800 V and 175 A rating. Find the number of SCRs
to be connected in series and in parallel. Use a derating factor
of 30%. Determine the value of R and C of static and dynamic
equalizing circuits. Take the maximum forward blocking current
and maximum difference in recovery charge as 8 mA and 30 μ
Coulombs respectively. (10)

EEE_Semester-V_Ch05.indd 9 4/19/2014 3:25:42 PM

 5.10 B.E./B.Tech. Question Papers

(ii) Explain how a power MOSFET is turned-on and turned-off. (6)

Or
(b) Explain the circuit arrangements that are necessary for proper
operation of series connected thyristors. (16)
12. (a) Explain the operation of any one of the three phase cyclo converters.
Draw and explain the trigger circuit of the cyclo converters. (16)
Or
(b) A single-phase voltage controller controls the power input to a load
circuit consisting of R = 3 Ω and ωL = 4 Ω. If the supply voltage is
230 V at 50 Hz, Calculate (16)
(i) Control range of firing angle
(ii) Maximum value of rms load current
(iii) Maximum power factor
(iv) Maximum value of average and rms thyristor current
13. (a) A DC chopper is connected to an inductive load with resistance of
5 Ω and an input voltage of 300 V. The on-time and off-time of the
chopper of 20 ms and 10 ms respectively. Estimate the duty ratio,
chopping frequency, average load voltage and current. (16)
Or
(b) Draw the power circuit for step-down DC chopper and explain its
operation for inductive load. What is the role of the free-wheeling
diode in such choppers? (16)
14. (a) A star connected Load of 15 Ω/phase is fed from 420 V dc source
through a three phase bridge inverter. Determine (16)
(i) RMS value of load current
(ii) RMS value and average value of thyristor currents
(iii) Power delivered to the load.
Assume 120° mode of conduction.
Or
(b) With the necessary explanation and equations, write the notes on
following items:

EEE_Semester-V_Ch05.indd 10 4/19/2014 3:25:42 PM

 Power Electronics (Nov/Dec 2012) 5.11

(i) Voltage source invertors. (8)

(ii) Current source invertors. (8)
15. (a) Explain in detail about the PLCs with microcontroller in the generation
of control signals for single phase AC to DC converters. (16)
Or
(b) Discuss the operation of HVDC system and explain how the power
flow can be easily controlled in both directions and also elaborate
its merits. (16)

EEE_Semester-V_Ch05.indd 11 4/19/2014 3:25:43 PM

 B.E./B.Tech. DEGREE EXAMINATION,
MAY/JUNE 2012
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL Questions.
PART A (10 × 2 = 20 marks)
1. Why IGBT is called voltage controlled device?

2. What is snubber circuit?

3. What is the function of freewheeling diodes in controlled rectifiers?

4. What is called as overlap angle?

5. What are the advantages of current commutated chopper?

6. Define duty cycle.

7. Write the differences between CSI and VSI.

8. What are the methods to reduce harmonic content?

9. Give some disadvantages of half wave AC voltage controller.

10. What is the control range of firing angle in ac voltage controller with RL
load?

PART B (5 × 16 = 80 marks)

11. (a) Explain briefly about the static and dynamic characteristics of SCR.
Or
(b) (i) Explain the basic structure and V-I characteristics of power
diodes with neat diagram.

EEE_Semester-V_Ch05.indd 12 4/19/2014 3:25:43 PM

 Power Electronics (May/June 2012) 5.13

(ii) Explain the construction and V-I characteristics of TRIAC with

neat diagram.
12. (a) Explain briefly with circuit diagram, waveforms and working of
series and parallel inverters.
Or
(b) Explain with necessary circuit diagrams, waveforms and working of
a 3 phase fully controlled converter. Derive the expressions for load
voltage and load current.
13. (a) Explain with necessary circuit diagrams and waveforms of a single
phase bridge type cycle converter.
Or
(b) Classify the basic topologies of switching regulators and explain
the operation of buck regulator with continuous load current using
suitable waveform.
14. (a) What is DC chopper? Describe various types of chopper configuration
with appropriate diagrams.
Or
(b) What is AC regulator and draw the configuration of a single phase
AC regulator and explain the operation?
15. (a) Explain briefly about the three phase bidirectional delta connected
controllers with neat diagrams.
Or
(b) Explain briefly about the three phase full wave controller with neat
diagrams.

EEE_Semester-V_Ch05.indd 13 4/19/2014 3:25:43 PM

 Solutions
May/June 2012

PART A

1. HF is a measure of the distortion of a waveform and is also known as total harmonic distortion (THD).

6. Dc–dc converter (or simply chopper) drives are widely used in traction applications all over the world.
A dc–dc converter is connected between a fixed-voltage dc source and a dc motor to vary the armature
voltage. In addition to armature voltage control, a dc–dc converter can provide regenerative braking of the
motors and can return energy back to the supply.This energy-saving feature is particulary attractive to
transportation systems with frequent stops such as mass rapid transit (MRT). Dc–dc converter drives are
also used in battery electric vehicles (BEVs).

PART B

11. (a)

I DS 0 1 3
2 4
[mA]

6
V GS
600

400
15

20

25
200

V DS

200 400 600 800 [V]

FIGURE 4.28
Typical characteristics of SITs. [Ref. 18, 19]

IGBTs

An IGBT combines the advantages of BJTs and MOSFETs. An IGBT has high input impedance, like
MOSFETs, and low on-state conduction losses, like BJTs. However, there is no second breakdown
problem, as with BJTs. By chip design and structure, the equivalent drain-to-source restistance RDS is
controlled to behave like that of a BJT [13–14].
The silicon cross section of an IGBT is shown in Figure 4.29a, which is identical to that of an
MOSFET except the p+ substrate. However, the performance of an IGBT is closer to that of a BJT than an
MOSFET. This is due to the p+ substrate, which is responsible for the minority carrier injection into the n-
region. The equivalent circuit is shown in Figure 4.29b, which can be simplified to Figure 4.29c. An IGBT
is made of four alternate PNPN layers, and could latch like a thyristor given the necessary condition: (αnpn +
αpnp) > 1. The n+-buffer layer and the wide epi base reduce the gain of the NPN-terminal by internal design,
thereby avoiding latching. IGBTs have two structures of IGBTs: punch-through (PT) and nonpunch
through (NPT). In the PT IGBT structure, the switching time is reduced by use of a heavily doped n-buffer
layer in the drift region near the collector. In the NPT structure, carrier lifetime is kept more than that of a
PT structure, which causes conductivitiy modulation of the drift region and reduces the on-state voltage
drop. An IGBT is a voltage-controlled device similar to a power MOSFET. Like an MOSFET, when the
gate is made positive with respect to the emitter for turn-on, n carriers are drawn into the p-channel near the
gate region; this results in a forward bias of the base of the npn-transistor, which thereby turns on. An
IGBT is turned on by just applying a positive gate voltage to open the channel for n carriers and is turned
off by removing the gate voltage to close the channel. It requires a very simple driver circuit. It has lower
switching and conducting losses while sharing many of the appealing features of power MOSFETS, such as
ease of gate drive, peak current, capability, and ruggedness. An IGBT is inherently faster than a BJT.
However, the switching speed of IGBTs is inferior to that of MOSFETs.
 Collector

p substrate

n - Buffer layer

n epi

p
p p

n p n

Gate Gate

Emitter
(a) Cross section

C C

R MOD R MOD
PNP PNP

NPN
G G R BE

R BE

E E
(b) Equivalent (c) Simplified
circuit circuit

FIGURE 4.29
Cross section and equivalent circuit for IGBTs.

The symbol and circuit of an IGBT switch are shown in Figure 4.30. The three terminals are gate,
collector, and emitter instead of gate, drain, and source for an MOSFET. The typical output characteristics
of iC versus vCE are shown in Figure 4.31a for various gate-emitter voltage vGE. The typical transfer
characteristic of iC versus vGE is shown in Figure 4.31b. The parameters and their symbols are similar to
that of MOSFETs, except that the subscripts for source and drain are changed to emitter and collector,
respectively. The current rating of a single IGBT can be up to 1200 V, 400 A, and the switching frequency
can be up to 20 kHz. IBGTs are finding increasing applications in medium-power applications such as dc
and ac motor drives, power supplies, solid-state relays, and contractors.
 IC
Gate signal C
RD
Rs G

V CC
VG R GE E

FIGURE 4.30
Symbol and circuit for an IGBT.

iC iC
7 3
V GE 10 V
6
Collector Current (A)

Collector Current (A)

5
2
9V
4
3 8V
1
2
7V
1 6V
0 vCE 0 vGE
0 2 4 6 8 10 12 0 2 4 6
Collector – emitter voltage Gate – emitter voltage
FIGURE 4.31
Typical output and transfer characteristics of IGBTs.

As the upper limits of commercially available IGBT ratings are increasing (e.g., as high as 6500 V and
2400 A), IGBTs are finding and replacing applications where BJTs and conventional MOSFETs were
predominantly used as switches.

11. (b) (i) A thyristor is a four-layer semiconductor device of pnpn structure with three pn-junctions. It
has three terminals: anode, cathode, and gate. Figure 7.1 shows the thyristor symbol and the sectional view
of three pn-junctions. Thyristors are manufactured by diffusion.

A Anode
A
p
J1
n
G J2
G p
K Gate J3
n

K Cathode
FIGURE 7.1
Thyristor symbol and three pn-junctions.

The cross section of a thyristor is shown in Figure 7.2a, which can be split into two sections of npn and
pnp as shown in Figure 7.2b.
When the anode voltage is made positive with respect to the cathode, the junction J1 and J3 are forward
biased. The junction J2 is reverse biased, and only a small leakage current flows from anode to cathode.
The thyristor is then said to be in the forward blocking, or off-state, condition and the leakage current is
known as off-state current ID. If the anode-to-cathode voltage VAK is increased to a sufficiently large value,
the reverse-biased junction J2 breaks. This is known as avalanche breakdown and the corresponding
voltage is called forward breakdown voltage VBO. Because the other junctions J1 and J3 are already forward
biased, there is free movement of carriers across all three junctions, resulting in a large forward anode
current. The device is then in a conducting state, or on-state. The voltage drop would be due to the ohmic
drop in the four layers and it is small, typically, 1 V. In the on-state, the anode current is limited by an
external impedance or a resistance, RL, as shown in Figure 7.3a. The anode current must be more than a
value known as latching current IL to maintain the required amount of carrier flow across the junctino;
otherwise, the device reverts to the blocking condition as the anode-to-cathode voltage is reduced. Latching
current IL is the minimum anode current required to maintain the thyristor in the on-state immediately after
a thyristor has been turned on and the gate signal has been removed. A typical v–i characteristic of a
thyristor is shown in Figure 7.3b [1].

Anode (A) Anode (A)

p p

n n n

p p
p
n n

Cathode (K) Gate (G) Cathode (K) Gate (G)

(a) Cross section of pnpn structure (b) Split sections of npn and pnp
FIGURE 7.2 Cross section of a thyristor.

iT

Forward volt-drop
(conducting)
Latching
current
Gate Forward
Reverse triggered breakover
breakdown Holding voltage
voltage current I
L

IH
A
V BO V AK
V AK
Forward
Reverse leakage
K leakage
Vs current
current
RL

iT

(a) Circuit (b) v – i Characteristics

FIGURE 7.3 Thyristor circuit and v–i characteristics.

 Once a thyristor conducts, it behaves like a conducting diode and there is no control over the device.
The device continues to conduct because there is no depletion layer on the junction J2 due to free
movements of carriers. However, if the forward anode current is reduced below a level known as the
holding current IH, a depletion region develops around junction J2 due to the reduced number of carriers
and the thyristor is in the blocking state. The holding current is on the order of milliamperes and is less than
the latching current IL. That is IL > IH. Holding currnt IH is the minimum anode current to maintain the
thyristor in the on-state. The holding current is less than the latching current.
When the cathode voltage is positive with respect to the anode, the junction J2 is forward biased but
junctions J1 and J3 are reverse biased. This is like two series-connected diodes with reverse voltage across
them. The thyristor is in the reverse blocking state and a reverse leakage current, known as reverse current
IR, flows through the device.
A thyristor can be turned on by increasing the forward voltage VAK beyond VBO, but such a turn-on
could be destructive. In practice, the forward voltage is maintained below VBO and the thyristor is turned on
by applying a positive voltage between its gate and cathode. This is shown in Figure 7.3b by dashed lines.
Once a thyristor is turned on by a gating signal and its anode current is greater than the holding current, the
device continues to conduct due to positive feedback, even if the gating signal is removed. A thyristor is a
latching device.

A
IA IT
I B1 I C2
A 1
IT Q1

p Q2
J1 I C1
n n
J2 J2 G Q2
G 2
p p IG I B2
IG J3
Q1 n IK
IK
K K

(a) Basic structure (b) Equivalent circuit

FIGURE 7.4 Two-transistor model of thyristor.

11. (b) (ii) A TRIAC can conduct in both directions and is normally used in ac-phase control (e.g., ac
voltage controllers in Chapter 11). It can be considered as two SCRs connected in antiparallel with a
common gate connection as shown in Figure 7.13a. The v–i characteristics are shown in Figure 7.13c.
Because a TRIAC is a bidirectional device, its terminals cannot be designated as anode and cathode. If
terminal MT2 is positive with respect to terminal MT1, the TRIAC can be turned on by applying a positive
gate signal between gate G and terminal MT1. If terminal MT2 is negative with respect to terminal MT1, it is
turned on by applying a negative gate signal between gate G and terminal MT1. It is not necessary to have
both polarities of gate signals, and a TRIAC can be turned on with either a positive or a negative gate
signal. In practice, the sensititives vary from one quadrant to another, and the TRIACs are normally
operated in quadrant I+ (positive gate voltage and gate current) or quadrant III– (negative gate voltage and
gate current).
 MT 1

MT 1
G
T1 T2
G

MT 2

MT 2
(a) Equivalent of TRIAC (b) TRIAC symbol

I
On-state
Quadrant II
Quadrant I (MT 2 v e)
Triggered,
IG
V
V
0
Off-state

Triggered,
IG
Quadrant III (MT 2 v e) Quadrant IV
On-state I
(c) v –i characteristics

FIGURE 7.13 Charateristics of a TRIAC.

12. (b) (ii) α = π/2. Vdc = 0.1592Vm Idc = 0.1592Vm/R. Vn = 0.5. From Vrms = 0.3536Vm Irms = 0.3536Vm/R.
Pdc = VdcIdc = (0.1592Vm)2/R Pac = Vrms Irms = (0.3536Vm)2/R.

Pdc (0.1592Vm ) 2
   20.27%
Pac (0.3536Vm ) 2

Vrms 0.3536Vm
FF    2.221 or 222.1%
Vdc 0.1592Vm
RF  FF 2  1  2.2212 – 11/ 2  1.983 or 198.3%
Vs  Vm / 2  0.707Vm .
Is = 0.3536Vm/R.
VA = VsIs = 0.707Vm × 0.3536Vm/R.

Pdc 0.15922 1
TUF    0.1014 and  9.86
Vs I s 0.707  0.3536 TUF
PF = 0.1014.

PIV = Vm.
α.
απ
Vm/π

The circuit arrangement of a single-phase full converter is shown in Figure 10.2a with a highly inductive
load so that the load current is continuous and ripple free [10]. During the positive half-cycle, thyristors T1
and T2 are forward biased; and when these two thyristors are fired simultaneously at ωt = α, the load is
connected to the input supply through T1 and T2. Due to the inductive load, thyristors T1 and T2 continue to
conduct beyond ωt = π, even though the input voltage is already negative. During the negative half-cycle of
the input voltage, thyristors T3 and T4 are forward biased; and firing of thyristors T3 and T4 applies the
supply voltage across thyristors T1 and T2 as reverse blocking voltage. T1 and T2 are turned off due to line
or natural commutation and the load current is transferred from T1 and T2 to T3 and T4. Figure 10.2b shows
the regions of converter operation and Figure 10.2c shows the waveforms for input voltage, output voltage,
and input and output currents.

T 3,T 4 T 1, T 2 T 3, T 4
is On v
R s
T1 T3 Vm
v V m sin t
vp vs vo
L
0 t
T4 T2 2
io Ia
E
vo
(a) Circuit

vo
V dc 2
0 t

io
0 I dc
io
Ia
V dc Load current
0 t
(b) Quadrant 2
is
Ia
2
0 t

Ia
(c) Waveforms

FIGURE 10.2 Single-phase full converter.

During the period from α to π, the input voltage vs and input current is are positive; and the power
flows from the supply to the load. The converter is said to be operated in rectification mode. During the
period from π to π + α, the input voltage vs is negative and the input current is is positive; and reverse power
flows from the load to the supply. The converter is said to be operated in inversion mode. This converter is
extensively used in industrial applications up to 15 kW [1]. Depending on the value of α, the average output
voltage could be either positive or negative and it provides two-quadrant operation.
The average output voltage can be found from

2   2V
Vdc 
2 
Vm sin t d (t )  m [ cos t ] 
2
(10.5)
2Vm
 cos 

14. (b) (i) <??>T1
t1 = t1m T1
T2 T2

The series resonant circuit formed by L, C, and load (assumed resistive) must be underdamped. That is,

4L
R2  (8.1)
C

Mode 1. This mode begins when T1 is fired and a resonant pulse of current flows through T1 and the
load. The instantaneous load current for this mode is described by

di1 1
L  Ri1   i1dt  vc1 (t  0)  Vs (8.2)
dt C

with initial conditions i1(t = 0) = 0 and vc1(t = 0) = –Vc. Because the circuit is underdamped, the solution of
Eq. (8.2) yields

i1 (t )  A1e tR / 2 L sin r t (8.3)

where ωr is the resonant frequency and

1/ 2
 1 R2 
r    2 (8.4)
 LC 4 L 
 T1

L1 L
io
Vs
C
L1 L
vo(t) R
T2

(a) Circuit

g1

0 t
i1 L To
T1 Vc g2
C
Vs 0 t
R To To
io i1 2
Mode 1
t3m i1
C tm
L i2 0 0 t
V c1
R t1m t1 i3
vc to
Mode 2 V c1

C Vs Vc
L
V c1 V c2
0 t
T2 t1m
R
2
Vc
i3
Mode 3
( b) E qui val ent ci r cui ts ( c) W avef or ms

FIGURE 8.1
Basic series resonant inverter.

The constant A1 in Eq. (8.3) can be evaluated from the initial condition:

di Vs  Vc
  A1
dt t 0 r L

and

Vs  Vc  t
i1 (t )  e sin r t (8.5)
r L

where
 R
 (8.6)
2L

The time tm when the current i1(t) in Eq. (8.5) becomes maximum can be found from the condition

di1
 0 or r e  tm cos r tm   e tm sin r tm  0
dt
and this gives

1 r
tm  tan 1 (8.7)
r 

The capacitor voltage can be found from

vc1 (t ) 

= –(Vs + Vc)e–αt (α sin ωrt + ωr cos ωrt)/ ωr + Vs (8.8)

This mode is valid for 0 ≤ t ≤ t1m (= π/ωr) and ends when i1(t) becomes zero at t1m. At the end of this mode,

i1(t = t1m) = 0

and

vc1 (t  t1m )  Vc1  (Vs  Vc )e  / ,  Vs (8.9)

Mode 2. During this mode, thyristors T1 and T2 are off. Redefining the time origin, t = 0, at the
beginning of this mode, this mode is valid for 0 ≤ t ≤ t2m.

i2(t) = 0, vc2(t) = Vc1 vc2(t = t2m) = Vc2 = Vc1

Mode 3. This mode begins when T2 is switched on and a reverse resonant current flows through the
load. Let us redefine the time origin, t = 0, at the beginning of this mode. The load current can be found
from

di3 1
L  Ri3   i3 dt  vc 3 (t  0)  0 (8.10)
dt C

with initial conditions i3(t = 0) = 0 and vc3(t = 0) = –Vc2 = –Vc1. The solution of Eq. (8.10) gives

Vc1
i3 (t )  e  t sin r t (8.11)
r L

The capacitor voltage can be found from

 1 t
C 0
vc 3 (t )  i3 (t )dt  Vc1
(8.12)
 Vc1e  t ( sin r t  r cos r t )/r

This mode is valid for 0 ≤ t ≤ t3m = π/ωr and ends when i3(t) becomes zero. At the end of this mode,

and in the steady state,

vc 3  (t  t3m )  Vc 3  Vc  Vc1e  /r (8.13)

Equations (8.9) and (8.13) yield

1  e z ez  1 V
Vc  Vs z
 Vs 2 z  s (8.14)
e e
z
e 1 ez  1

1  ez e z (1  e z ) Vs e z
Vc1  Vs z
 Vs 2 z  z (8.15)
e e
z
e 1 e 1

where z = απ/ωr. Adding Vc from Eq. (8.14) to Vs gives

Vs  Vc  Vc1 (8.16)

Equation (8.16) indicates that under steady-state conditions, the peak values of positive current in Eq. (8.5)
and of negative current in Eq. (8.11) through the load are the same.
The load current i1(t) must be zero and T1 must be turned off before T2 is fired. Otherwise, a short-
circuit condition results through the thyristors and dc supply. Therefore, the available off-time t2m( = toff),
known as the dead zone, must be greater than the turn-off time of thyristors, tq.

 
 t t (8.17)
o r off q

where ωo is the frequency of the output voltage in rads per second. Equation (8.17) indicates that the
maximum possible output frequency is limited to

1
f o  f max  (8.18)
2(tq   /r )

15. (a) It has been shown in Section 11.8 that the input PF of controlled rectifiers can be improved by the
pulse-width-modulation (PWM) type of control. The naturally commutated thyristor controllers introduce
lower order harmonics in both the load and supply side and have low-input PF. The performance of ac
voltage controllers can be improved by PWM control [4]. The circuit configuration of a single-phase ac
voltage controller for PWM control is shown in Figure 11.22a. The gating signals of the switches are
shown in Figure 11.22b. Switches S1 and S2 are turned on and off several times during the positive and
negative half-cycles of the input voltage, respectively. S1 and S 2 provide the freewheeling paths for the
load current, whereas S1 and S2, respectively, are in the off-state. The diodes prevent reverse voltages from
appearing across the switches.
 The output voltage is shown in Figure 11.23a. For a resistive load, the load current resembles the
output voltage.With an RL load, the load current rises in the positive or negative direction when switch S1
or S2 is turned on, respectively. Similarly, the load current falls when either S1 or S 2 is turned on. The load
current is shown in Figure 11.23b with an RL load.

D1 S1

io
S2
D2
R S1 0
D 2
S 1 S2 0
vs vo
S 2 S
D 1 0
1 L
S 2 0

( a) C i r cui t ( b) G ati ng si gnal s

FIGURE 11.22
Ac voltage controller for PWM control.

15. (b) Single-Phase Cycloconverters

The principle of operation of single-phase/single-phase cycloconverters can be explained with the help of
Figure 11.17a.The two single-phase controlled converters are operated as bridge rectifiers. However, their
delay angles are such that the output voltage of one converter is equal and opposite to that of the other
converter. If converter P is operating alone, the average output voltage is positive and if converter N is
operating, the output voltage is negative. Figure 11.17b shows the simplified equivalent circuit of the dual
converter. Figure 11.17c shows the waveforms for the output voltage and gating signals of positive and
negative converters, with the positive converter on for time T0/2 and the negative converter operating for
time T0/2. The frequency of the output voltage is fo = 1/T0.
If αp is the delay angle of the positive converter, the delay angle of the negative converter is αn = π –p.
The average output voltage of the positive converter is equal and opposite to that of the negative converter.
Vdc2 = –Vdc1 (11.40)

Similar to dual converters in Sections 10.4 and 10.7, the instantaneous values of two output voltages
may not be equal. It is possible for large harmonic currents to circulate within the converters.
The circulating current can be eliminated by suppressing the gate pulses to the converter not delivering
load current. A single-phase cycloconverter with a center connection transformer as shown in Figure 11.18
has an intergroup reactor, which maintains a continuous current flow and also limits the circulating current.

Gating sequence. The gating sequence [1] is as follows:

1. During the first half period of the output frequency To/2, operate converter P as a normal controlled
rectifier (in Section 10.3) with a delay angle of αp = α, that is, by gating T1 and T2 at α, and gating T3 and T4
at π + α.
2. During the second half period To/2, operate converter N as a normal controlled rectifier with a delay
angle of αN = π – α, that is, by gating T1 and T2 at π – α, and gating T3 and T4 at 2π – α.
 is P-converter in N-converter

io
ip T1 T3 T2 T4

Load
vs

vo1 vo2 T3 T1
T4 T2

(a) Circuit

iP iN

io

Ac
vo
load
vP V m sin ot vN V m sin ot

P-Converter N-Converter

Control circuit

er E r sin ot

(b) Equivalent circuit

vs fs 60 Hz
2V s

0 st
2 3
vo
To fo 20 Hz
2
4 5 6
0 ot
2 3
p n To
2
n
P-converter on
0 ot
N-converter on
0 ot

(c) Waveforms for resistive load

FIGURE 11.17
Single-phase/single-phase cycloconverter.

Three-Phase Cycloconverters

The circuit diagram of a three-phase/single-phase cycloconverter is shown in Figure 11.19a. The two ac–dc
converters are three-phase controlled rectifiers. The synthesis of output waveform for an output frequency
of 12 Hz is shown in Figure 11.19b. The positive converter operates for half the period of output frequency
and the negative converter operates for the other half period. The analysis of this cycloconverter is similar
to that of singlephase/ single-phase cycloconverters.
The control of ac motors requires a three-phase voltage at a variable frequency. The cycloconverter in
Figure 11.19a can be extended to provide three-phase output by having 6 three-phase converters, as shown
in Figure 11.20a. Each phase consists of 6 thyristors, as shown in Figure 11.20b, and a total of 18 thyristors
are required. If six fullwave three-phase converters are used, 36 thyristors would be required.

Gating sequence. The gating sequence [1] is as follows:

1. During the first half period of the output frequency To/2, operate converter P as a normal three-phase
controlled rectifier (in Section 11.6) with a delay angle of αp = α.

2. During the second half period operate To/2, converter N as a normal controlled three-phase rectifier
with a delay angle of αN = π – α.
 B.E./B.Tech. DEGREE EXAMINATION,
NOV/DEC 2011
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions
PART A (10 × 2 = 20 marks)
1. State the condition to be satisfied for the load commutation in SCR.

2. Define Turn-OFF time of SCR.

3. Give any two differences between single phase full converter and semi
converter.

4. What is meant by line commutated inverter?

5. What are the advantages of SMPS over phase controlled rectifier?

6. Give the uses of resonant switching?

7. What is meant by current source inverter?

8. Why is the series inverter called so?

9. What are the applications of cycle converter?

10. What is integral cycle control?

PART B (5 × 16 = 80 marks)
11. (a) Describe the current commutation technique to turn off the SCR
with neat sketch and waveforms.
Or
(b) With neat sketch explain the turn on and turn off characteristic of SCR.

EEE_Semester-V_Ch06.indd 3 7/7/2012 5:07:31 PM

 6.4 B.E./B.Tech. Question Papers

12. (a) Explain the working of a three phase full converter with ‘R’ load for
the firing angles of 60°, 90° and 150°
Or
(b) (i) Explain the operation of a single phase full bridge converter
with RL load for continuous and discontinuous load currents.
(ii) A single phase full bridge converter is connected to ‘R’ load.
The source voltage is of 230 V, 50 Hz. The average load current
is of 10 A. For R = 20 Ω find the firing angle.

13. (a) Explain the working of Buck–Boost converter with sketch and
waveforms and also drive the expression for Is.
Or
(b) With a neat sketch and output voltage waveforms, explain the work-
ing of full bridge SMPS.

14. (a) With a neat sketch and output voltage waveforms, explain the work-
ing of three phase bridge inverter in 180 degree mode of operation.
Or
(b) Discuss the different modes of operation of series resonant inverter
with unidirectional switch with neat circuit diagram and waveforms.

15. (a) Discuss the working of 2 stage sequence control of AC voltage

controller.
Or
(b) Discuss the working of a 3 phase to single phase cyclo-converter
with neat voltage and current waveforms.

EEE_Semester-V_Ch06.indd 4 7/7/2012 5:07:31 PM

 Solutions
PART A
1. The load resistance ‘RL’ and the commutating components L and C are so
selected that their combination forms an underdamped resonant circuit.

2. The turn OFF time of SCR is defined as the minimum time interval
between the instant at which the anode current becomes zero, and the
instant at which the device is capable of blocking the forward voltage.
tOFF = t rr + t gr

trr − Reverse recovery time

tgr − Hate recovery time

3. Full converter Semi converter

2 Quadrant operation is possible Single quadrant operation

4 thyristors are used 2 thyristors and 2 diodes are
used
Input power factor is less Input power factor is more
(RL Load) (with RL Load)

4. In a single phase full converter (with RL Load) When firing angle is

greater than 90°, the average DC output voltage is negative and the power
is being delivered from the DC side of the converter to the AC side.
The converter under this condition is operating as a line-commutated
inverter.

5. Due to high frequency switching, the filter components are small in val-
ues and less bulky. Hence cost is less, and ripple voltage is also less.

6. In resonant switching, zero voltage and zero current switching are pos-
sible which minimizes the switching losses.

7. The inverter, in which the current form the DC source is maintained at

an effectively constant level, irrespective of load (or) inverter conditions.
This is achieved by inserting a large inductance in series with the DC
supply.

EEE_Semester-V_Ch06.indd 5 7/7/2012 5:07:31 PM

 6.6 B.E./B.Tech. Question Papers

8. The commutation components, ‘L’ and ‘C’ are connected in series with
the load. If the load is purely resistive, this inverter constitutes a series
R-L-C resonant circuit.

9. • Speed control of AC drives

• Induction Heating
• Static VAR generation
• Aircraft applications

10. In integral cycle control of AC voltage regulator, the load is connected to

source for few cycles and the load is disconnected from source for few
cycles. This is done by triggering the SCR for few cycles and turning
OFF the SCR for few cycles

PART B
11. (a) Class B (or) Resonant Pulse Commutation
It is also called as current commutation.
T1
i0

Vc D
+ –

+ c L L
Vs O
– A
D
TA

• Vs is source vge
• T1 is main thyristor
• TA is auxilary thyristor
• C is commutating capacitor
• L is commutating inductor

ig , ig = triggering pulse for SCRT1 , SCRTA

1 A

iT = current through thyristor T1

1

ic = Capacitor charging current

Vc = Voltage across capacitor

EEE_Semester-V_Ch06.indd 6 7/7/2012 5:07:31 PM

 Power Electronics (Nov/Dec 2011) 6.7

• Capacitor C is fully charged to a Values Vs initially with left hand

plate positive; [Precharged capacitor].

Working
At time t = 0;
• SCR T1 is ON
• Capacitor is charged to Vc = Vs
• ∴ SCR T1 is ON, voltage across T1 = 0 ie; VT = 0 .
1

• Current flows through SCR

∴ iT = i0 = I 0
1

I0 = load current.
• SCR TA is OFF
• Diode D is reverse biased so its OFF.
ic = 0, ∵ there is no path for current to flow.

T1

Vc D
+ – L
+ O
Vs c A
– D

TA

[when device is ON its represented by a Short circuit and when it

is OFF it is represented by open circuit].

At t = t1
• SCR TA is turned ON.
• When SCR TA is turned ON to commutate SCR T1; capacitor
discharges thro’ SCR TA.

EEE_Semester-V_Ch06.indd 7 7/7/2012 5:07:31 PM

 6.8 B.E./B.Tech. Question Papers

• Capacitor current ic starts flowing. ic is in the negative direction

C
∴ ic = −Vs * sin ω 0 t .
L
• As ic ↑; Vc ↓.
∵ the capacitor discharges, Vc decreases ∴ i0 = iT = I 0
1

After t1
T1 i0

Vc D
c L
+ –
+ L
Vs ic O
A
– D
TA

• The negative capacitor current increases and reaches a peak

valule ic = − Ip
• When ic reaches peak negative value is at ic= − Ip; the capacitor
completely discharges and the voltage across the capacitor Vc = 0.
• Now due to the flow of ic, capacitor starts charging in the reverse
direction.
• ic falls from its negative peak value Ip to zero.

At t = t2
• When ic reaches zero, and capacitor charges in reverse direction
to Vc = −Vs, SCR TA is turned OFF (due to reverse voltage and
zero ant).
• Diode D is forward biased and is turned ON.
• So capacitor discharges through L and D; Now ic starts flowing in
the positive direction
∴ i0 = iT + ic ; (or) iT = i0 − ic .
1 1

ic starts ↑ in positive direction.

EEE_Semester-V_Ch06.indd 8 7/7/2012 5:07:31 PM

 Power Electronics (Nov/Dec 2011) 6.9

T1 iT1 i0

ic
D
c L
+ L
– + O
– A
D
TA

At t = t3
• Vc = −Vs.
• When ic ↑es and reaches a i0 ie when ic= i0, iT = i0 − ic
1

iT = i0 − i0 = 0;
1

∴ When current through SCR T1 = 0; SCR T1 turns OFF.

Capacitor charges in opposite direction

At t = t4
• Now capacitor charges in the opposite direction from −Vs to zero.
• At t = t4; Vc = 0 and i0 = ic.
• Capacitor charges from 0 to Vs.

ic
+ –
+ L
Vs c L O
– A
D

At t = t5
ic ↓ and reaches zero; ic = 0.
VC = Vs
Diode D is reverse biased and turns OFF.

EEE_Semester-V_Ch06.indd 9 7/7/2012 5:07:32 PM

 6.10 B.E./B.Tech. Question Papers

ig1
igA

i0

it
1

ic

I0

Vc –Ip

Vs Vs

–Vs

t1 t2 t3 t4 t5
T1 ON TA ON TA OFF T 1 OFF

(b) Switching characteristics (or) Dynamic characteristics

Turn ON Mechanism
• When a positive gate signal is applied to a forward biased SCR,
the transition of SCR from blocking state too conducting state is
called as turn ON mechanism.
• The time taken for SCR to traverse from the blocking state to
conducting state is called as turn ON time.
• Turn on time is divided into 3 periods
tON = td + tr + tp
td = delay time; tr = rise time; tp (or) ts = peak time (or) spread
time.

EEE_Semester-V_Ch06.indd 10 7/7/2012 5:07:32 PM

 Power Electronics (Nov/Dec 2011) 6.11

• when the gate current reaches 0.9 IG the anode current (IA) starts
increasing, and reaches 0.1 IA (10% of its max value)
• The time taken for anode current to ↑ and reach 0.1 IA is called as
delay time (td). [or] It is the time taken for anode voltage to fall
from VA to 0.9 VA is called as delay time.
• The anode current further increases and reaches 0.9 IA.
• The time taken by the anode current to increase from 0.1 IA to 0.9
IA is called as risetime (tr). [or] it is the time taken by the anode
voltage to fall from 0.9VA to 0.1VA.

VG Gate Voltage

IG 0.9IG
Gate Current

IA Anode Current

0.9IA

0.1IA
t1 t2 t3 t4
td tr tp
VA

trr tgr
0.9VA Anode Voltage

0.1VA Onstate Vge Drop

td 1 tr tp
trr tgr

EEE_Semester-V_Ch06.indd 11 7/7/2012 5:07:32 PM

 6.12 B.E./B.Tech. Question Papers

Spread Time or Peak Time (ts or tp)

It is time taken by the anode current to rise from [0.9 IA to maximum
value of IA] 90% to 100% of its full value. (00) it is the time taken
by VA to fall from 0.1 VA to its ON state voltage drop. (nearly zero).

• During this time the conduction spreads over the entire cross sec-
tion of cathode and so e−s spread over all the functions.

Turn OFF Mechanism

• Turning OFF an SCR means bringing the SCR from conducting
state to blocking state.
• To turn OFF an SCR two things are to be done.
1. Reduce the anode current below its holding current level.
2. Application of reverse voltage.
• When the anode current is zero, if we apply forward voltage to
the SCR, the device will not be able to block this forward voltage
due to the fact that excess charge carriers are still at the junctions,
so the device will start conducting even when the gate signal is
not applied.
• In order to avoid this, reverse baising of SCR is done to remove
the excess charge carriers from all four layers.
• The turn OFF time is defined as the time from the instant the
anode current becomes zero to the instant SCR reaches its for-
ward blocking ability.

turn OFF time tOFF = trr + tgr

trr = Reverse recovery time
tgr = Gate recovery time
Reverse recovery process is the removal of excessive charge carriers
from the top and bottom layers of SCR.
• At t1; current IA = 0.
• After t1; IA build up in the reverse direction, due to the charge car-
riers stored in the four layers.
• Reverse recovery current removes the excessive carriers from
junctions J1 and J3 during the time t1 to t3. (Reverse recovery cur-
rent flows due sweeping out of holes from top p-layer and e−s
from bottom n-layer).

EEE_Semester-V_Ch06.indd 12 7/7/2012 5:07:32 PM

 Power Electronics (Nov/Dec 2011) 6.13

Reverse Recovery Time: trr

It is the time taken from the removal of excessive carriers from top
and bottom layer of SCR.
• At t2; when nearly 60% of charges are removed from the outer
two layers, the reverse recovery current (↓es) decays.
• This decaying causes a reverse voltage to be applied across the
SCR.
• At t3 all excessive carriers from J1, and J3 is removed.
• The reverse voltage across SCR removes the excessive carriers
from junction J2.
• Gate recovery process is the removal of excessive carriers from J2
junction by application of reverse vge.
• Time taken for removal of trapped charges from J2 is called gate
recovery time. (tgr).
• At t4 all the carriers are removed and the device moves to the
forward blocking mode.

12. (a) 3f Full Converter: [with R load]

T1 T3 T5

R
R
Y
B
T4 T6 T2

• Full converter consists of 6 SCRs

• T1, T3, T5 are SCRs of the positive group.
• T4, T6, T2 are SCRs of the negative group.
• Only two SCRs conduct in any interval.
• Each SCR conducts for 120°.
• Every SCR pair conducts for an interval of 60°.

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 6.14 B.E./B.Tech. Question Papers

• SCRs are triggered in the sequence T1 → T2 → T3 → T4 → T5 → T6.

• Triggering delay between individual SCRs is 60°.
ie if T1 is triggered at a = 0, then T2 is triggered at a = 60, T3 at
a = 120; T4 at a = 180; T5 at a = 240; T6 at a = 300
• By varying a the conduction of SCRs in both the group is varied.
RB

R
RY YB
–B

30°
0°
12
–Y Y

B YR
BY
–R

BR

[ie if T1 is ON at 30°; T2 will turn ON 60° after T1 ans so on]

[angle delay b/w SCRs of positive group is 120° ie T1, T3, T5 conduct
with 120° delay. T2, T4, T6 conduct with 120° delay]
But angle delay b/w SCR of positive and negative group is 60°.
• Always SCR from negative group and one SCR from positive
group will conduct.
For a = 0; wt = 30
Positive group negative group
→ T1 is ON at wt = 30; • T2 is ON at wt = 90
→ T3 is ON at wt = 150; • T4 is ON at wt = 210
→ T5 is ON at wt = 270; • T6 is ON at wt = 330

From wt = 30 → 90
• R phase is more positive; Y phase is more negative.
• T1 is connected to R phase.

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 Power Electronics (Nov/Dec 2011) 6.15

• T6 is connected to Y phase.
• ∴ T1 T6 conducts
V0 = VRY
From wt = 90 to 150
• R phase is more positive; B phase is more negative.
• T1 is connected to R phase.
• T2 is connected to B phase.
• T1T2 conducts
V0 = VRB
From wt = 150 → 210
• Y phase is more positive; B phase is more negative.
• T3 is connected to Y phase.
• T2 is connected to B phase.
• T3T2 conducts
V0 = VYB
From wt = 210 → 270
• Y phase is more positive; R phase is more negative.
• T3 is connected to Y phase.
• T4 is connected to R phase.
• T3T4 conducts
V0 = VYR
From wt = 270 → 330
• B phase is more positive; R phase is more negative.
• T5 is connected to B phase.
• T4 is connected to R phase.
• T5T4 conducts.
V0 = VBR
From wt = 330 → 390
• B phase is more positive; Y phase is more negative.
• T5 is connected to B phase.
• T6 is connected to Y phase.
• T5 T6 conducts
V0 = VBY

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 6.16 B.E./B.Tech. Question Papers

Output voltage eqn.

For a ≤ 60°
π π
+α +α
1 2 32 ⎛ π⎞
V0 (avg ) = ∫ VRY dω t = ∫ 3 Vm sin ⎜ ω t + ⎟ dω t .
π /3π ππ ⎝ 6⎠
+α +α
6 6

• All combinations of SCRs conduct only for 60º

∴ time period = 60º = p/3
π 2+α
3 3 Vm ⎡ ⎛ π⎞⎤
∴ V0 = − cos ⎜ ω t + ⎟ ⎥
π ⎢⎣ ⎝ 6 ⎠ ⎦π 6+α

3 3 Vm ⎡ ⎛ π π⎞ ⎛π π⎞⎤
=− ⎢ cos ⎜ + α + ⎟ − cos ⎜ + α + ⎟ ⎥
π ⎣ ⎝ 2 6 ⎠ ⎝ 6 6⎠⎦
3 3 Vm ⎡ ⎛ 2π ⎞ ⎛π ⎞⎤
=− ⎢ cos ⎜ + α ⎟ − cos ⎜ + α ⎟ ⎥
π ⎣ ⎝ 3 ⎠ ⎝ 3 ⎠⎦
3 3 Vm ⎡ 2π 2π π π ⎤
=− ⎢ cos cos α − sin sin α − cos cos α + sin sin α ⎥
π ⎣ 3 3 3 3 ⎦
3 3 Vm ⎡ 3 3 ⎤
=− ⎢ −0.5cos α − sin α − 0.5cos α + sin α ⎥
π ⎣ 2 2 ⎦
3 3 Vm 3 3 Vm
=− [ − cos α ] = − [cos α ]
π π
3 3 Vm
∴ V0 = cosα
p
For a > 60º
5π 5π

1 6
1 6
π
π 3 π∫ 3 π∫
V0 ( avg ) = VRY dω t = 3Vm sin(ω t + )dω t
6
+∞ +∞
6 6

5π
3 3 Vm ⎡ ⎛ π⎞⎤ 6
= ⎢ − cos ⎜ ω t + ⎟ ⎥
π ⎣ ⎝ 6⎠⎦
π
+α
6

3 3Vm ⎡ ⎛π ⎞⎤
V0 = ⎢1 + cos ⎜ + α ⎟ ⎥
π ⎣ ⎝ 3 ⎠⎦
For a > 90º 3f full converter behaves like inverter.

EEE_Semester-V_Ch06.indd 16 7/7/2012 5:07:33 PM

 Power Electronics (Nov/Dec 2011) 6.17

Phase

Vges

a=0
wt = 0

V0
Line
Vges

EEE_Semester-V_Ch06.indd 17 7/7/2012 5:07:33 PM

 a = 30 T5 T1 T2 T5 T6 T3 T5 6.18
T2 T2 T4 T6 T2 T4
wt = 60
BY RY RB YB YR BR BY RY RB YB YR BR

EEE_Semester-V_Ch06.indd 18
T5 T6 T1 T6 T1 T2 T3 T2 T3 T4 T5 T4 T5 T6 T1 T6 T1 T2 T3 T2 T3 T4 T5 T4

30 60 90 120 150 180 210 240 270 300 330 360

a = 60 T5 T1 T3 T5 T1 T3 T5
wt = 90 T4 T6 T2 T4 T6 T2 T4
BR BY RY RB YB YR BR BY RY RB YB YR BR

T5 T4 T5 T6 T1 T6 T1 T2 T3 T 2 T3 T4 T5 T4 T5 T6 T1 T6 T1 T2 T3 T2 T3 T4 T5
a = 90
T5 T1 T2 T5 T1 T3
wt = 120 T4 T6 T2 T4 T6 T2 T4
B.E./B.Tech. Question Papers

BR BY RY RB YB YR BR BY RY RB YB YR

T5 T4 T5 T6 T1 T6 T1 T2 T3 T2 T3 T 4 T5 T4 T5 T6 T1 T6 T1 T2 T3 T2 T3 T4

7/7/2012 5:07:33 PM
 a = 120 T3 T5 T3 T2 T1 T5
wt = 180v

EEE_Semester-V_Ch06.indd 19
T3 T4 T5 T4 T5 T6 T2 T3 T2 T4 T1 T4 T1 T4 T2 T4 T 2 T5 T2 T6 T3 T6 T3 T1

T3
For < > 90° Sf Convertor Before like an Substrator

a = 180 T2 T5 T4 T5 T1 T2
wt = 240 T4 T4 T3 T2 T1 T6
Power Electronics (Nov/Dec 2011)

T3 T4 T5 T4 T5 T6 T2 T3 T2 T4 T1 T4 T1 T4 T2 T4 T2 T5 T2 T6 T1 T2 T3 T2

YR BR BY RY RB BY RY RB BY RY RB YB
6.19

7/7/2012 5:07:33 PM
 6.20 B.E./B.Tech. Question Papers

(b) (i) 1f Full Wave Bridge Rectifier with RL Load

i0
T1 T3

a R
VS = Vm Sin wt
v0
b
T4 T2 L

• Vs = Vmsinwt = Supply voltage.

• SCRs T1, T2 conduct in positive half cycle.
• SCRs T3, T4 conduct in positive half cycle.
In positive half cycle:
• In positive half cycle terminal ‘a’ is positive w.r.t terminal ‘b’.
• a is positive; b is negative.
• Vab = +Vmsinwt.
• Vba = −Vmsinwt.
• Vab supplies SCRs T1, T2 so they are forward biased.
• Vba supplies SCRs T3, T4, so they are reverse biased.
• SCR T1, T2 are turned on at wt = a.
∴ load current flows through a − T1 − R − L − T2 − b.

T1 T3
a

b
T4 T2

From wt = 0 to a
• SCR T1T2 is FB
• SCR T3T4 is RB

EEE_Semester-V_Ch06.indd 20 7/7/2012 5:07:33 PM

 Power Electronics (Nov/Dec 2011) 6.21

VT = VT = Vab
1 2

VT = VT = Vba
3 4

io = 0
Vo = 0
At wt = a SCR T1, T2 are turned ON.

From wt = a to p
• SCR T1, T2 are ON
• ∴ VT = VT = 0
1 2

• Due to inductive load current through SCR T1, T2 ↑es very

slowly. ∴ i0 = increases slowly.
• i0 = ↑es and reaches maximum at wt = π.
• V0 = Vs

At wt = p [During negative half cycle]

• At wt = p; SCR T1, T2 are reverse biased.
[∵ in negative cycle; a is negative; b is positive; ∴ Vab =
−Vmsinwt; Vba = +Vmsinwt]
• SCR T3, T4 are forward biased.
• Though SCR T1, T2 are reverse biased at wt = π, they do not
turn OFF because the current i0 does not drop below holding
current.
• i0 takes some time to fall to zero. The time taken by i0 to falls
to zero is “b ”. It is called extinction angle.

Based on the value of b we can divide the operation into two

modes.
(i) discontinuous mode: (a > b)
• When ‘b ’ is less than ‘a’, i0 reaches zero at ‘b ’ before
the turning ON of the next SCR at ‘a’.
(ii) continuous mode: (a = b )
• when a = b the current reaches to zero at the same time
when the next SCR is turned ON.
\ From p to b:
• i0 gradually reduces and falls to zero at wt = b.
∴ SCR T1, T2 is turned OFF at wt = b.

EEE_Semester-V_Ch06.indd 21 7/7/2012 5:07:33 PM

 6.22 B.E./B.Tech. Question Papers

∴ VT = VT = 0 till b.
1 2

VT = VT = Vba
3 4

i0 = 0 at b.
V0 = Vab till b.

From b to p + a No SCR conducts.

V0 = 0 T1 T2 = RB
i0 = 0 T3 T4 = FB
VT = VT = Vab
1 2

VT = VT = Vba.
3 4

At wt = p + a

T1 T3 R
a

b L
T4 T2

At wt = p + a SCR T3, T4 is turned ON.

∴ VT = VT = 0
3 4

SCR T1, T2 are RB; ∴ VT = VT = Vab

1 2

i0 = Slowly ↑es due to RL load.

V0 = Vs.
• i0 flows through b − T3 − R − L − T4 − a.

At wt = 2p
• SCR T3, T4 is RB, but does not turn OFF because i0 is not less
than holding current.
∴ V0 = Vba.

At wt = 2p + b
• i0 ↓ to zero ∴ SCR T3, T4 is OFF.
∴ at wt = 2p + b; V0 = 0; i0 = 0; VT = VT4 = Vba
3

VT = VT = Vab.
1 2

EEE_Semester-V_Ch06.indd 22 7/7/2012 5:07:34 PM

 Power Electronics (Nov/Dec 2011) 6.23

Equations for discontinuous mode:

β
1
v0 (avg ) =
π ∫α
Vm sin ω t .dω t

Vm
v0 ( avg ) = [cosα − cosβ ] already solved in page 62
π
vm
I 0 ( avg ) = [cos α − cos β ]
πR
β
1
π ∫α
V0 ( rms) = Vm 2 sin 2 ω t .dω t

Vm 1
V0 (rms) = [β - α ] − [ sin 2β − sin2α ]
2π 2

V0 rms
I 0 rms =
R
P = V0 rms * I 0 rms

Equations for continuous mode:

π +α
1
V0 ( avg ) = ∫α V sin ω t .dω t
π m

2Vm
V0 ( avg ) = cosα
π
π +α
1
V0 rms =
π ∫α V m
2
sin 2 cot .dω t

Vm 1
V0 rms = π [sin 2(π + α ) − sin 2α ]
2π 2
P = V0 rms* I 0 rms

V0 rms
I 0 rms =
R

EEE_Semester-V_Ch06.indd 23 7/7/2012 5:07:34 PM

 6.24 B.E./B.Tech. Question Papers

Vab Vba

Vs

a p+a 2p + a 3p + a

p 2p 3p 4p

Ig1, Ig2

Ig3, Ig4 a 2p + a

p+a 3p + a
Discontinous Mode (a = b)
V0

T1 T2 T3 T4 T1 T2 T3 T4
a p p + a 2p 2p + a 3p 3p + a 4p

i0

T1 T2 T3 T4 T 1 T2 T3 T4
p p+a 2p 2p + a 3p
a 3p + a 4p

VT1, VT2 p 3p

a p p + a 2p 2p 2p + a 3p 3p + a

VT3, VT4

a 2b
p p+a 2p 2p + a 3b 3p + a 4p
3p

(ii) Vrms = 230 V

R = 20 Ω
I L = 10 A
2Vm
I0 = cos α
πR

EEE_Semester-V_Ch06.indd 24 7/7/2012 5:07:34 PM

 Power Electronics (Nov/Dec 2011) 6.25

Vab Vba

Vs

p 2p 3p 4p

Ig1, Ig2

a 2p + a
Ig3, Ig4
p+a 3p + a
Continous Mode (a + b)
Vo

T1 T2 T3 T4 T1 T2 T3 T4
a p p + a 2p 2p + a 3p + a 4p
3p

i0

T1 T2 T3 T4 T1 T2 T3 T4
a p p+a 2p 2p + a 3p 3p + a 4p

VT1, VT2 3p + a 4p
a p 2p + a 3p
2p

VT3, VT4

a 2p + a
p+a 2p 3p 3p + a 4p
p

2 × 2Vrms
I0 = cos α
πR
2 × 2 × 230
I0 = cos α
20 × 3.14
⇒ α = 15°

EEE_Semester-V_Ch06.indd 25 7/7/2012 5:07:35 PM

 6.26 B.E./B.Tech. Question Papers

13. (a) Buck–Boost Regulators

A buck-boost regulator provides an output voltage that may be less
than or greater than the input voltage—hence the name “buck–
boost”; the output voltage polarity is opposite to that of the input
voltage. This regulator is also known as an inverting regulator. The
circuit arrangement of a buck–boost regulator is shown in figure.

is Q1 vD Dm

+ – +
i1
vc = – vo
C
Vs L
Load vo , Va
G
iL , IL ic +
− –
io , Ia

(a) Circuit Diagram

+
is iL

Vs L C Load

ic i0 = Ia
−

Mode 1

Dm

iL i1

C
L Load
ic
i0 = Ia

Mode 2
(b) Equivalent Circuits

EEE_Semester-V_Ch06.indd 26 7/7/2012 5:07:35 PM

 Power Electronics (Nov/Dec 2011) 6.27

vD

Vs
t1 t2
0 t
kT T
– Vs
iL
I2
DI
I1
0 t
kT T
i1
I2

I1
0 t
kT T
ic

I2 – Ia

0 t
– Ia kT T

Vc

– Va DVc

0 t

i0

Ia
0 t

(c) Waveforms

Buck–boost regulator with continuous iL.

The circuit operation can be divided into two modes. During

mode 1, transistor Q1 is turned on and diode Dm is reversed biased.
The input current, which rises, flows through inductor L and transis-
tor Q1. During mode 2, transistor Q1 is switched off and the current,
which was flowing through inductor L, would flow through L, C, Dm,

EEE_Semester-V_Ch06.indd 27 7/7/2012 5:07:35 PM

 6.28 B.E./B.Tech. Question Papers

and the load. The energy stored in inductor L would be transferred

to the load and the inductor current would fall until transistor Q1 is
switched ON again in the next cycle. The equivalent circuits for the
modes are shown in figure (b). The waveforms for steady-state volt-
ages and currents of the buck–boost regulator are shown in figure (c)
for a continuous load current.
Assuming that the inductor current rises linearly form I1 to I2 in
time t1,
I 2 − I1 ΔI
Vs = L =L (1)
t1 t1
or
ΔIL
t1 = (2)
Vs
and the inductor current falls linearly form I2 to I1 in time t2,
ΔI
Va = − L (3)
t2
or
−ΔIL
t2 = (4)
Va

Where ΔI = I 2 − I1 is the peak-to-peak ripple current of inductor L.

From Eqs. (1) and (3)
Vs t1 −Va t2
ΔI = =
L L
Substituting t1 = kT and t2 = (1 − k)T, the average output voltage is
Vs k
Va = (5)
1− k
Substituting t1 = kT and t2 = (1 − k)T into Eq.(5) yields
−Vs
(1 − k ) = (6)
Va − Vs
Substituting t2 = (1 − k)T, and (1 − k) from Eq.(6) into Eq. (5) yields
Va
t1 =
(V a
− Vs ) f
(7)

EEE_Semester-V_Ch06.indd 28 7/7/2012 5:07:35 PM

 Power Electronics (Nov/Dec 2011) 6.29

Assuming a lossless circuit, VsIs = −VaIa = VsIak/(1 − k) and the aver-

age input current Is is related to the average output current Ia by
Iak
Is = (8)
1− k
The switching period T can be found from
1 ΔIL ΔIL ΔIL(Va − Vs )
T= = t1 + t2 = + = (9)
f Vs Vs VsVa

and this gives the peak-to-peak ripple current

VsVa
ΔI = (10)
fL(Va − Vs )
or
Vs k
ΔI = (11)
fL
When transistor Q1 is ON, the filter capacitor supplies the load cur-
rent for t = t1. The average discharging current of the capacitor is
Ic = Ia and the peak-to-peak ripple voltage of the capacitor is
1 t1 1 t1 I t
ΔVc = ∫
C 0
I c dt = ∫ I a dt = a 1
C 0 C
(12)

Substituting t1 = Va ⎡⎣(Va − Vs ) f ⎤⎦ from Eq. (7) becomes

I aVa
ΔVc = (13)
(Va
− Vs ) fC
or
Iak
ΔVc = (14)
fC
Condition for continuous inductor current and capacitor
voltage. If IL is the average inductor current, the inductor ripple cur-
rent ΔI = 2 I L . Using Eqs. (5) and (11). We get

kVs 2kVs
= 2I L = 2I a =
fL (1 − k ) R

EEE_Semester-V_Ch06.indd 29 7/7/2012 5:07:35 PM

 6.30 B.E./B.Tech. Question Papers

which gives the critical value of the inductor Lc as

(1 − k ) R
Lc = L = (15)
2f

If Vc is the average capacitor voltage, the capacitor ripple voltage

ΔVc = 2Va . Using Eq. (14), we get

Iak
= 2Va = 2 I a R
CF

which gives the critical value of the capacitor Cc as

k
Cc = C = (16)
2 fR

A buck-boost regulator provides output voltage polarity reversal

without a transformer. It has high efficiency. Under a fault condi-
tion of the transistor, the di /dt of the fault current is limited by the
inductor L and will be Vs/L. Output short-circuit protection would be
easy to implement. However, the input current is discontinuous and
a high peak current flows through transistor Q1.

(b) Full Bridge Converter

D1 L
M1 M3
L
N2 c O
A
2

N1 V2
D
Vs
1

V1 N2
Uncontrolled V2
Rectifier
M4 D2
M2
–

• It has four MOSFETs M1, M2, M3, M4

• A transformer with center tap on secondary.
• Two diodes D1 and D2 and filter components L,C.

EEE_Semester-V_Ch06.indd 30 7/7/2012 5:07:36 PM

 Power Electronics (Nov/Dec 2011) 6.31

Mode 1: When M1 and M2 ON:

+ D1 L
M1
+V L
O
2 c A
+ D
– V2
Vs V1 = Vs
+V
2
–
– V2

M2
D2
–

• M1 and M2 are turned ON together

• Voltage Vs appears across primary. ∴V1 = Vs
• This induces a voltage V2 in both the secondary winding
N
V2 = Vs ∗ 2
N1

• This voltage V2 forward biases diode D1

∴V2 from upper half of secondary supplies the load
N
∴ V0 = V2 = Vs ∗ 2
N1
• Voltage V2 on lower half of system wdg reverse biases diode D2.
∴ it does not conduct.

Mode 2: When M3 and M4 ON:

+
D1 L
M3
L
– O
c A
V2
– D
+
V1 = –V2
Vs
–
+ V2
+
M4
D2
–

EEE_Semester-V_Ch06.indd 31 7/7/2012 5:07:36 PM

 6.32 B.E./B.Tech. Question Papers

• M3 and M4 are turned ON together.

• Voltage across the primary is reversed.
∴ V1 = −Vs.
• This induces a voltage V2 is both the secondary wdg.
N
∴ V2 = −Vs * 2
N1
• This voltage V2 in upper half reverse biases diode D1 and there-
fore it does not conduct.
• Vge V2 on the lower half forward biases diode D2.
∴ it conducts and supplies the load.
N
∴ V0 = V2 = Vs * 2
N1

14. (a) Three Phase Bridge Inverter: (3f VSI)

• 3f inverter is a 6 step bridge inverter.
• It has 6 SCRs.
• A step is defined as a change in firing from one SCR to the next
SCR in proper sequence.
• 3f inverter generates a 3f output.
• For one 360° cycle, 6 SCRs conduct.
360
∴ = 60°. ∴ every SCR is triggered with a delay of 60°.
6
There are two types of VSI
• 180° conduction
• 120° conduction
(i) 108° conduction mode 3f VSI:
• A 3f inverter has 6 SCRs
T1, T3, T5 → positive group SCRs
T4, T6, T2 → negative group SCRs.
• A 3f star connected load is used.
• Let A, B, C be the 3 phases.
T1T4 are connected in A
T3T6 are connected in B
T5T2 are connected in C

EEE_Semester-V_Ch06.indd 32 7/7/2012 5:07:36 PM

 Power Electronics (Nov/Dec 2011) 6.33

T1 T3 T5

Vs

T4 T6 T2

B
A N C

∴ A B C
T1 T3 T5
T4 T6 T2
• In 180° conduction mode every SCR conducts for an interval of
180°.
• Every SCR triggered with the delay of 60°
180
∴ = 3; ∴ during every instant 3 SCRs conduct.
60
• SCRs are triggered in the sequence T1, T2 , T3 , T4, T5, and T6 with
a delay of 60° between each
60° 60° 60° 60° 60°
i.e., T1 → T2 → T3 → T4 → T5 → T6

If T1 is ON at wt = 0;
Then T2 is ON at wt = 60
T3 is ON at wt = 120
T4 is ON at wt = 180
T5 is ON at wt = 240
T6 is ON at wt = 300
After being turned ON each SCR will conduct for 180° and it will
be OFF for another 180°

EEE_Semester-V_Ch06.indd 33 7/7/2012 5:07:36 PM

 6.34 B.E./B.Tech. Question Papers

The triggering sequence is as follows (from graph)

561, 612, 123, 234, 345, 456, 561….
During every instant Two SCRs from positive group and one SCR
from negative group conduct. (or) vice versa.

T1
60 120 180 240 300 360 420 480 540 600
T2

T3

T4

T5

T6

561 612 123 234 345 456 561 612 123 234 345 456

V/2

V/3

V an

– V/3

– 2V/3

2V/3

V/3

V bn

– V/3

– 2V/3

Vcn

Vab

–V

Vbc

Vca

EEE_Semester-V_Ch06.indd 34 7/7/2012 5:07:36 PM

 Power Electronics (Nov/Dec 2011) 6.35

For the first sequence 561.

SCRs T5, T6, T1 conduct.
T1, T5 are SCRs from positive group
T6 is SCR from negative group.
Now the equivalent circuit is
A C A C

T1 T5
R R
Vs
N
Vs

R
T6
B
B

A C
N

A1C

R/2
V = Vs
N

RAN and RCN are in parallel.

R * R R2 R
∴ Req = = =
R + R 2R 2

VAN = VCN

By voltage division technique. Let Vs = V

V * R /2 V
VAN = VCN = =
R + R /2 3
V *R 2
VBN = = V
R + R /2 3

EEE_Semester-V_Ch06.indd 35 7/7/2012 5:07:36 PM

 6.36 B.E./B.Tech. Question Papers

From this if 2 SCRs of same group conduct their load resistance is

in parallel and voltage = V/3
(positive if positive group SCR conduct negative if negative group
SCR conduct)
For the single SCR from other group the load will be in series with
other phase loads resistance and Vg = 2 V/3
(positive if positive group SCR conduct
negative if negative group SCR conduct)

561 612 123

A
C A A B

V V V N
N
N

B B C C

234 345 456

C
B C B
V V V
N
N N

A B A A C

Conducting VAN VBN VCN VAB VBC VCA

SCRs

561 V/3 −2 V/3 V −V 0

V
3
612 2 −V −V/3 V 0 −V
V
3 3
123 V/3 V/3 −2V/3 0 V −V
234 −V/3 2V/3 −V/3 −V V 0
345 −2V/3 V/3 V/3 −V 0 V
456 −V/3 −V/3 2V/3 0 −V V

EEE_Semester-V_Ch06.indd 36 7/7/2012 5:07:37 PM

 Power Electronics (Nov/Dec 2011) 6.37

VAB = VAN − VBN VAN, VBN, VCN = Phase voltage (Stepped wave)
VBC = VBN − VCN VAB, VBC, VCA = Line voltage (quasi square
wave)
VCA = VCN − VAN

(b) Series Inverter

• An inverter in which the commutating components (L and C) are
connected in series with the load is called as series inverter.
• As current attains zero value naturally, due to the nature of the
series circuit, the inverter is also called as self commutated (or)
load commutated inverters.
• It consists of load resistance ‘R’.

T1

i0 R L
Vs
V0
+ – –
C
+
T2

• Commutating components L and C are connected in series with

load ‘R’
• SCR T1 and T2 are turned ON so that o/p voltage of desired fre-
quency can be obtained.
• Capacitor C is precharged with upper plate negative and lower
plate positive. Vc = −Vs
Mode 1: SCR T1 ON
• SCR T1 is ON at time t = 0.
• Current i0 flows in the circuit through R − L − C
• ∴ capacitor is precharged the voltage is Vc = −V
• Vs = VL + Vc.
i0 = ic
• One to current i0 capacitor C is charged to upper plate positive
and lower plate negative; ∴ Vc = +V
• W.k.t when current in max; Vc = 0 at t = t1

EEE_Semester-V_Ch06.indd 37 7/7/2012 5:07:37 PM

 6.38 B.E./B.Tech. Question Papers

T1
+
R L
Vs
– + – ic
V0 VL +
i0
C
–

• When current in zero; Vc = +V at t = t2

• When capacitor charges from +Vs to −Vs the current is zero.
• When current goes through zero SCR T1 is turned OFF.
• Similarly when i0 ↑ voltage across L ↑es and when i0 ↓ voltage
across L ↓ (VL = V)
[Already seen in Unit-I RLC circuit]
V0
V0 = VR .; i0 = (V0 , i0 is + ve)
R

Mode II
• SCR T2 is not triggered immediately after T1 is OFF.
• If T2 is triggered immediately, then T1 and T2 will short the
supply Vs.
• This time delay between the conduction of T1 and T2 is called
dead band. (from t2 to t3)
• During the dead band VR = 0; VL = 0; VC = +V

Mode III: T2 is ON
• SCR T2 is triggered at time t = t3
• The capacitor discharges through L, R and T2.

R L

– V0 + i0
–
T2 C
+

EEE_Semester-V_Ch06.indd 38 7/7/2012 5:07:37 PM

 Power Electronics (Nov/Dec 2011) 6.39

• V0, i0 in R are opposite to assumed positive direction. ∴V0, i0 are

negative. i0 = ic.
• At t = t4 ic is max and Vc = 0
• At t = t4 ic decreases to zero and Vc = −Vs.
• At t = t4 ic = 0, ∴current through T2 is zero and ∴ SCR T2 is
turned OFF.
• After some dead band SCR T1 is again turned ON.

V 0,i 0

Dead
Band

+v

t=0
Vc
t1 t2 t3 t4

–v

+ V1

t1 t2 t3 t4
VL

–v

EEE_Semester-V_Ch06.indd 39 7/7/2012 5:07:37 PM

 6.40 B.E./B.Tech. Question Papers

Disadvantages of Series Inverter

• Battery is used only during positive half cycle
• Output voltage has harmonics due to dead band

15. (a) Two Stage Sequence Control

• In two stage sequence control two controllers are connected in
parallel.

a T1
T2
+
i0

V1 = Vm Sin wt = Vs
T3
Vs = Vm Sin wt

–
n T4 + L
+ O
V0 A
– D
V2 = Vm Sin wt = Vs

• Vs = Vm sin ω t
V1 = V2 = Vm sin ω t = Vs ( vge in secondary of transformer)
• Sum of two secondary voltages = V1 + V2 = Vm sin ω t + Vm sin ω t
= 2Vm sin ω t = 2Vs
(∵V m
sin ω t = Vs )
• Turns ratio from primary to each secondary is unity.
• Load used may be either R or RL load.
• For voltage variation between 0 to Vs
→ use SCR T3 , TH
→ For zero output voltage α = 180°
→ For V0 = Vs ; α = 0

• For voltage variation between V to 2Vs

→ Use SCR T1 T2 and T3, T4

EEE_Semester-V_Ch06.indd 40 7/7/2012 5:07:37 PM

 Power Electronics (Nov/Dec 2011) 6.41

For variation from V to 2Vs; T3 T4 is triggered at a = 0

T1, T2 is triggered for a = 0 to 180°

For R load
In the positive cycle: (wt = 0 to p)
• T1 and T3 are forward biased.
For varying voltage from 0 to Vs

T3
i0
+
+
Vs +
– R V0 = Vs
V2 = Vs –
–

• T3 is triggered at wt = 0
• T3 is ON at wt = 0
∴V0 = V2 = Vm sin ω t = Vs

Low to vary voltage from Vs to 2V6:

T1

V1 = Vs
i0
+
+
Vs = 2Vs
– R V0 = 2Vs
V2 = Vs –

• T1 is triggered at ω t = α
• T1 is ON at ω t = α
• When T1 is ON voltage V1 reverse biases SCR T3 and so T3 is
turned OFF
• Now V0 = V1 + V2 = 2Vs

EEE_Semester-V_Ch06.indd 41 7/7/2012 5:07:38 PM

 6.42 B.E./B.Tech. Question Papers

∴ the output voltage jumps from Vs to 2Vs.

At ω t = π ; since the input voltage and current = 0 ∴ SCR T1 is
turned OFF at ω t = π
In the negative cycle: (ω t = π to 2π )
• T2 and T4 are forward biased.

For varying voltage from 0 to −Vs

V 1 = Vs

–
Vs T4
+ – i0

V 2 = Vs –
R
+
+

• T4 is triggered at ω t = π (180°)
• T4 is ON
∴V0 = −V2 (∵ − ve sign because current and voltage direction is opposite
to assumed +ve direction)
ie., V0 = −V2 = −Vm sin ω t = −Vs

Now to vary the voltage from −Vs to −2Vs

V1 = Vs T2

–
Vs 2Vs i0
+ –
V2 = Vs
R
+ +

• T2 is triggered at ω t = π + α
• T2 is ON

EEE_Semester-V_Ch06.indd 42 7/7/2012 5:07:38 PM

 Power Electronics (Nov/Dec 2011) 6.43

• when T2 is ON; V1 reverse biases

• ∴ at ω t = π + α ; SCR T4 is OFF
• Now V0 = −(V1 + V2 ) = −2Vs
(∵ negative sign because current and voltage direction is opposite
to assumed opposite direction)
∴ V0 jumps from −Vs to −2Vs.
At ω t = 2π as the current goes thro’ 0 SCR T2 is reverse biased and
turns OFF.
∴ at ω t = 2π SCR T2 is OFF.
Again opposite cycle repeats itself with T1, T2 forward biased.

With RL load
In the opposite cycle:
• T1 and T3 are forward biased
Varying voltage from 0 to Vs:

2Vs

Vs 2Vs Vs

p+a
0 a p 2p 2p + a 3p wt

V0, i0

p+a
0 a p 2p 2p + a 3p wt

T3 ON T1 ON T1 OFF T2 ON T2 OFF T1 ON T1 OFF

V0 = Vs T3 OFF T4 ON V0 = 2Vs T3 ON T3 OFF
V0 = 2Vs V0 = Vs V0 = Vs V0 = 2Vs

EEE_Semester-V_Ch06.indd 43 7/7/2012 5:07:38 PM

 6.44 B.E./B.Tech. Question Papers

• T3 is triggered at ω t = 0
• T3 is ON at ω t = 0
• V0 = V2 = Vs ; Due to RL load i0 increases slowsly.
i0 vary vge from Vs to 2Vs
• T1 is triggered at ω t = α
• At ω t = α T1 is ON
• When T1 is ON; vge V1 reverse biases SCR T3 amd turns it OFF.
∴ T3 is OFF at ω t = α
• Now V0 = V1 + V2 = 2Vs
• Now, i0 increases further to maximum value.

In the negative cycle

At ω t = π ; SCR T1 is reverse biased
But T1 is not OFF because current i0 is zero.
At ω t = π ; T4 is turned ON (But does not conduct till T1 is OFF)

To vary vge from 0 to −Vs

• At ω t = β; i0 = 0 ∴ T1 is OFF
• Now after ω t = β; T4 is ON.
∴ V0 = −V2 = −Vs
i0 = increases slowly in reverse direction

To vary vge between −Vs to −2Vs

• At ω t = π + α T2 is turned ON
• when T2 is ON V1 reverse biases T4 and turns it OFF.
• At ω t = π + α ; T4 is OFF.
−V0 = −(V1 + V2 ) = −2Vs
i0 increases and reaches maximum value at ω t = 2π .
∴ at ω t = 2π ; SCR T2 does not turns OFF since i0 is not zero.
∴ T2 conducts till i0 is zero at ω t = 2β
At ω t = 2β , T3 conducts.
At ω t = 2π + α T1 is ON. (then the cycle repeats itself).

EEE_Semester-V_Ch06.indd 44 7/7/2012 5:07:39 PM

 Power Electronics (Nov/Dec 2011) 6.45

2Vs

Vs 2Vs Vs

0 r p 2p 3p

V0 Vo

p+a
0 a p 2p 2p + a 3p

i0

0 a p b p+a 2p 2b 2p + a 3p

(b) Three-phase to Single-phase Cyclo-converter

The circuit of a three-phase to single-phase cyclo-converter is shown
in Fig. 1. Two three-phase full-wave (six-pulse) bridge convert-
ers (rectifier) connected back to back, with six thyristors for each
bridge, are used. The ripple frequency here is 300 Hz, six times the
input frequency of 50 Hz. So, low value of load inductance is needed
to make the current continuous, as compared to one using single-
phase bridge converters described in the previous lesson (#4.4) with
ripple frequency of 100 Hz. Also, the non-circulating current mode
of operation is used, where only one converter − bridge 1 (posi-
tive) or bridge 2 (negative), conducts at a time, but both converters
do not conduct at the same time. It may be noted that each thyris-
tor conducts for about 120°(π/3), i.e., one-third of one complete
cycle, whereas a particular thyristor pair, say 1& 2 conduct for about
60°(π/6), i.e., one-sixth of a cycle. The thyristors conduct in pairs
as stated, one (odd-numbered) thyristor in the top half and the other

EEE_Semester-V_Ch06.indd 45 7/7/2012 5:07:39 PM

 6.46 B.E./B.Tech. Question Papers

(even-numbered) one in the bottom half in two different legs. Two

thyristors in one leg are not allowed to conduct at a time, which
will result in short circuit at the output terminals. The sequence
of conduction of the thyristors is 1 & 6, 1 & 2, 3 & 2, and so on.
When thyristor 1 is triggered, the conducting thyristor (#5) in top
half, being reverse biased at that time, turns off. Similarly, when
thyristor 2 is triggered, the conducting thyristor (#6) in bottom half,
being reverse biased at that time turns off. This sequence is repeated
in cyclic order. So, natural or line commutation takes place in this
case. Otherwise, the procedure is similar to the one as discussed in
the previous lesson.
The procedure to be followed in the triggering of the thyristors in
sequence in the two bridge converters has been briefly given earlier.
The readers are requested to go through two lessons (#2.5-2.6) in
module 2 (AC-DC Converters), or any standard text book. As given
in the earlier lesson (#4.4), the firing angle (α) of two converters is
first decreased starting from the initial value of 90° to the final value
of 0°, and then again increased to the final value of 90°, as shown in
Fig. 1. Also, for positive half cycle of the output voltage waveform,
bridge 1 is used, while bridge 2 is used for negative half cycle. The
two half cycles are combined to form one complete cycle of the
output voltage, the frequency being decided by the number of half
cycles of input voltage waveform used for each half cycle of the
output. As more no. of segments of near 60°(π/6) is used, the output
voltage waveform becomes near sinusoidal, with its frequency also
being reduced.
The initial value of firing angle delay is kept at a1 ≈ 90°, such the
average value (dc) of the output voltage in this interval of near 60°
(π/6) [Vav ∝ cos a1 = cos 90° = 0.0], is zero. It may be noted that the

iP iN

P1 P3 P5 + N1 N3 N5

3-phase A L A 3-phase
o
Ac B iO a B Ac
Supply C d C Supply
v
–
P4 P6 P2 N4 N6 N2

Fig. 1 Three-phase to single-phase cycloconverter

EEE_Semester-V_Ch06.indd 46 7/7/2012 5:07:39 PM

 Power Electronics (Nov/Dec 2011) 6.47

next thyristor in sequence is triggered at a2 < 90°, as the firing angle

is decreased for each segment, to obtain higher voltage Vav ∝ cos a2 =
+ve, to form the sine wave at the output. This can be observed from
the points, M, N, O, P, Q, R & S, shown in Fig. 2. From these seg-
ments, the first quarter cycle of the output voltage waveform from 0°
to 90°, is obtained. The second quarter cycle of the above waveform
from 90° to 180°, is obtained, using the segments starting from the
points, T, U, V, W, X & Y (Fig. 2). It may be noted that the firing angle
delay at the point, Y is a = 90°, and also the firing angle is increased
from 0° (T) to 90° (Y) in this interval. When the firing angle delay
is 0°, the average value of the segment is Vav ∝ cos a = cos 0° = 1.0
The two quarter cycles form the positive half cycle of the output
voltage waveform. In this region, the bridge 1 (positive) is used.
To obtain the negative half cycle of the output voltage waveform
(180°−360°), the other bridge converter (#2) termed negative (N) is
used in the same manner as given earlier, i.e. its firing angle delay
(α) is first decreased starting from the initial value of 90° to the final
value of 0°, and then again increased to the final value of 90°, as
given earlier. The two half cycles (positive and negative) together
give one complete cycle (0°−360°) of the output voltage waveform.
The load on the output of the cyclo-converter is assumed to be
inductive (R-L). The load can also be capacitive. For inductive load,
the output current (Fig. 3) lags behind the voltage by its phase angle,
f (assumed to be positive). The load power factor is also +ve (cos f ).
It may be noted that the current is unidirectional in a thyristor

Fabricated Output Voltage

Mean Output Voltage
a = 90° a = 0° a = 90°
e0

T
R S U
Q V
P W

O X
M N Y q = wt

Fig. 2 Output voltage waveforms for a three-phase to single phase

cyclo-converter

EEE_Semester-V_Ch06.indd 47 7/7/2012 5:07:39 PM

 6.48 B.E./B.Tech. Question Papers

Fabricated Output Voltage Mean Output Voltage

a = 90° a = 0° a = 90°

e0

q=w

(a)
Inversion Inversion Inversion

Rectification Rectification
i0

Current in Positive Group Current in Negative Group

Angle of Load
Impedance (f)
(b)
Fig. 3 Voltage (a) and current (b) waveforms for a three phase full-wave
(six-pulse) cycloconverter.

converter. As the current, being alternating in nature, flows in both

directions in a complete cycle, two converters are connected in anti-
parallel. The positive (P) converter carries current during positive
half cycle of output current, while the other, i.e. negative (N) one
carries current in the negative half cycle. As discussed in the previ-
ous lesson (#29), P-converter acts as a rectifier, when the output
voltage is positive, and as an inverter, when the output voltage is
negative (Fig. 3). Similarly, N-converter acts as a rectifier, when the
output voltage is negative, and as an inverter, when the output volt-
age is positive. It can thus be inferred, in general, that one of two
converters would operate as rectifier, if its output voltage and cur-
rent have the same polarity, and as an inverter, if these are of oppo-
site polarity.

EEE_Semester-V_Ch06.indd 48 7/7/2012 5:07:40 PM

 B.E./B.Tech. DEGREE EXAMINATION,
April/May 2011
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions
PART A (10 × 2 = 20 marks)
1. What are the parameters involved in switching loss of a power device?

2. What are the methods of turn – on of SCR?

3. Write any four performance parameters of a phase controlled rectifiers.

4. What is dual converter?

5. What is the principle of current limit control of chopper?

6. What is meant by SMPS and mention its two advantages?

7. What are the PWM methods for voltage control within the inverters?

8. What are the merits and demerits of current source inverter?

9. What is Matrix converter?

10. List out the different types of cyclo converter

Part B (5 × 16 = 80 marks)
11. (a) Explain the switching characteristics of the IGBT with neat circuit
diagram and waveforms. (16)
Or
(b) Write short notes on:
(i) Snubber circuit for BJT. (8)
(ii) Communication circuit for SCR. (8)

PE_April-May 2011-QP.indd 1 4/23/2014 6:20:29 PM

 2.2 B.E./B.Tech. Question Papers

12. (a) Describe the effect of source inductance on the performance of a

single phase full converter indicating clearly the conduction of
various thyristors during one cycle. Derive the expression for its
output voltage. (16)
Or
(b) Explain the principle of operation of single phase dual converter
with neat power circuit diagram. (16)
13. (a) A step up chopper has input voltage of 220V and output voltage of
660V. If the non
conducting time of thyristor chopper is 100μsec,
compute the pulse width of output voltage. In case the pulse width is
halved for constant frequency operation, find the new output voltage.
(16)
Or
(b) Explain the various modes of operation of Boost DC – Dc converter
with necessary waveforms. (16)
14. (a) Describe the operation of single phase auto sequential commutated
current source inverter with power circuit and waveforms. (16)
Or
(b) Describe the operation of three phase voltage source inverter with
120’ mode of operation. (16)
15. (a) Explain the working of multistage sequential control of AC voltage
controller. (16)
Or
(b) Explain the principle of single phase to single phase step – down
cyclo – converter with power circuit and waveforms. (16)

PE_April-May 2011-QP.indd 2 4/23/2014 6:20:29 PM

 Solutions
April/May 2011

PART A

1. The magnitude of forward curent, di/dt at the time of communication and junction temperature are the
paramters involved in switching loss of a power device.

2.
1) Forward voltage triggering
2) dv/dt triggering
3) Gate triggering
a) DC gate triggering
b) AC gate triggering
c) Pulse gate triggering
4) Radiation triggering
5) Thermal triggering

3. Input performance paramters

a) Input power factor
b) Input displacement factor
c) Input current distortion factor
d) Input current harmonic factor
e) Crest factor

Output performance parameters:

a) Rectification ratio
b) Form factor
c) Voltage ripple factor
d) Current ripple factor

4. It consists of two full converters; one full converter operates as a rectifier in first quadrant (both Vo, Io
is positive) from α = 0° to 90° and as an inverter (Vo negative but Io positive) from α = 90° to 180° in
the fourth quadrant, Thus a full converter can operate as a two quadrant converter.

5. In this control strategy, the on and off of chopper circuit is guided by the previous set value of load
current. These two set values are maximum load current Io .max and minimum load current Io .min.

6. SMPS (switched mode power supply) is based on the chopper principle, the output dc voltage is
controlled by varying the duty cycle of chopper by PWM or FM techniques is called switched mode
power supply.
Advantages:
1) For the same power rating, SMPs is of smaller size, lighter in weight and possesses higher
efficiency because of its high frequency operation.
2) SMPs is less sensitive to input voltage variations.

7. The control of voltage can be done at three places in the system.

a) At the input of the inverter – external control of dc input voltage
b) At the output of the inverter – external control of ac output voltage
c) Within the inverter – Internal control of inverter

8. Merits:
1) CSI does not require any feedback diodes.
2) Commutation circuit is simple as it contains only capacitors.
 Demerits:

1) Load current as well as its magnitude depends upon the nature of the load impedance.
2) CSI has stiff dc current square as its input terminals.

9. The matrix converter is a single stage converter. It uses bi-directional fully controlled switches for
direct conversion from ac to ac. It is an alternative to the double sided PWM voltage source rectifier
inverter.
It is a single stage converter that requires only nine switches from three phase conversion.

10. Cyclo converters are of two types, namely:

a) Step – down cyclo converters
b) Step – up cyclo converters

Part – B

11. a) Refer: Qns. No: 11(a) Nov/Dec 2010

11. b) (i) Snubber Circuit

A series combination of (RS + CS) in parallel with the device prevents the unwanted dv/dt triggering of
the SCR. This circuit is called a snubber circuit.

Operation
When S is closed, a snubber voltage appears across the circuit. The capacitor CS behaves as a short
circuit and therefore VSCR is zero.
With time the capacitor charges at a slow rate such that dv/dt across CS and across the SCR is less than
the maximum dv/dt rating of the device

Fig: 1.21 – Snubber circuit

Before the SCR is fired, CS charges to VS. When turn – on the SCR, CS discharges through SCR and
sends current is.

VS

( R  RSCR )
Where R = Resistor of the capacitor.

RSCR – Resistor of SCR during forward bias mode.

This resistance ‘R’ value is quite low. By the turn ON the di/dt will tend to be excessive damaging the
SCR. The magnitude of the discharge current is controlled by RS in series with CS. Now, when SCR is
turned on, initial discharge current VS/CS is relatively small and turn on di/dt is thereby reduced.

11. b)(ii) Refer; Qns. no: 11(b)(ii) Nov/Dec 2010

12. a) EFFECT OF SOURCE IMPEDANCE ON THE PERFORMANCE OF CONVERTERS:
The source impedance is taken as purely inductive. The load inductance is assumed large so that output
current is virtually constant. The source inductance causes the outgoing and incoming SCRs to conduct
together. During the commutation period (when both incoming and outgoing SCRs are conducting
together), the output voltage is equal to the average value of the conducting phase voltages. For a single
phase converter, the load voltage will be zero and for a 3 phase converter, the load voltage is (V2 + Vb)/2
(average value of the conducting phases a and b). The commutation period in seconds, when outgoing and
incoming SCRs are conducting together, is also known as the overlap period. The angular period, during
which both the incoming and outgoing SCRs are conducting, is known as commutation angle or overlap
angle μ in degrees or radians.
The effect of source inductance is investigated in this section for both single phase and three phase full
converters. It would be observed that the effect of source inductance is
i) to lower the mean output voltage
ii) to distort the output voltage and current waveforms and
iii) to modify the performance parameters of the converter.

Single phase full converter:

In the single phase full converter shown in fig (a) LS is the source inductance. The load current is
assumed constant (analysis with pulsating load current more involved), fig (b) gives the equivalent circuit
for fig (a) for analytical purposes. When terminal 1 of source voltage VS is positive in fig (a), current i1,
flows through LS. T1, load and T2; this is shown as V1, LS. T1, T2 and load in fig (b). Similarly when
terminal 2 of VS is positive, load current i2 flows through T3, load, T4; this is shown as V2, LS, T3, T4 and
load in fig (b).

Fig: 2.24(c) – Typical voltage and current waveforms

 di di 
LS  1  2   2Vm sin t …. (2.16)
 dt dt 
As the load current is assumed constant throughout, i1 + i2 = I0. Differentiating this w.r.t t, we get,
di1 di2
 0
dt dt
di1 di2 2Vm
  sin t
dt dt LS
 Addition of equation gives,
di1 Vm
 sin t
dt LS
Load current I, through thyristor pair T1, T2 builds up from zero to I1 = I0 during the overlap angle μ;
i.e., at ωt = α, i1 = 0 and at ωt = (α + μ),

i1 = I0,

I0 Vm (a  )
0
di1 
LS   /
sin t.dt

Vm
I0  [cos   cos(   )] … (2.17)
 LS
It is seen from fig (c), that output voltage V0 is zero from α to (α + μ), thus the average output voltage
V0x is given by,

Vm (   )
Vox   
( )
sin t.d (t )

Vm
 
[cos(   )  cos(   )]

Vm
 
[cos   cos(   )]
Average value of output voltage at no load,
2Vm
V0  cos  .

Maximum mean output voltage,
2V
V0 m  m

Maximum mean o/p Vge at no load

2
V0 m
 [cos   cos(   )]
2
L
cos(   )  cos   S I 0
Vm
2Vm  LS
V0 x  cos   I0
 Vm
2Vm
 cos   2 fLS I 0

Also from equn,
 LS
cos   I 0  cos(   )
Vm
Subs, this value of cos α,
2V  LS
V0 x  m cos(   )  I0
 
Voltage regulation due to source inductance
  LS  I 0 1
 
 V0 at no load
2 fLS I 0  fLS I 0
 
2Vm cos  Vm cos 
 LS V
I 0  m [cos   cos(   )]
 
For a full wave diode rectifier at, α = 0

 LS I 0 Vm
 [1  cos  ]
 
Inductive Vge regulation

 LS I 0 Vm
(1  cos  )
   m
2Vm / 2Vm /
1  cos  
 
 2 
12. b) Explain the principle of operation of single phase dual converter with neat power circuit diagram.

13. a) Refer: Qns. no: 13(a) Nov/Dec 2007

13. b) STEP – UP CHOPPERS:

In this chopper, a large inductor L in series with source voltage VS is shown in fig 3.6(a). For the
chopper configuration of fig 3.6(a), average output voltage V0 is less than the input voltage VS, i.e. V0 <
VS; this configuration is therefore called step – down chopper. Average output voltage V0 greater than input
voltage VS, can be obtained by a chopper called step – up chopper.

Operation:
In this chopper, a large inductor 1, in series with VS. When the chopper CH is on, the closed current
path is as shown in fig 3.6(b) and inductor stores energy during Ton period. When the chopper CH is off, as
the inductor current cannot die instantaneously, this current is forced to flow through the diode and load for
a time Toff, fig 3.6(c). As the current tends to decrease, polarity of the emf induced in L is reversed as
di
shown in fig 3.6(c). As a result voltage across the load, given by V0 – VS  L exceeds the source voltage
dt
VS. In this manner, the circuit of fig 3.6(a) acts as a step – up chopper and the energy stored in L is released
to the load.
When CH is on, current through the inductance L would increase from I1 to I2 as shown in fig 3.6(d).
When CH is off, current would fall from I2 to I1. With CH on, source voltage is applied to L. i.e. VL – VS.
When CH is off, KVL for fig (c) gives VL – V0 + VS – 0, or VL – V0 – VS. Here VL = voltage a/c L.
Variation of source voltage VS, source current i3, load voltage V0 and load current i0 is sketched in fig
3.6(d). Assuming linear variation of output current, the energy input to inductor from the source, during the
period Ton, is
 di
Fig: 3.6(a) – Step – up chopper, (b) L stores energy, (c) L is added to VS, (d) Voltage and current
dt
waveforms

Win = (Voltage across L) (average current through L) Ton

I I 
 VS   1 2  Ton … (3.4)
 2 

During the time Toff, when chopper is off, the energy released by inductor to the load is

Woff – (Voltage across L) (average current through L) Toff

I I 
 (Vo  VS )  1 2  Toff … (3.5)
 2 

Considering the system to be lose less, then two energies given by equations will be equal.
I I  I I 
VS  1 2  Ton  (Vo  VS )  1 2  Toff
 2   2 
VS  Ton  V0Toff – VS Toff
(1) … (3.6)
VoToff  VS Ton  Toff   VS  T
T T 1
V0  VS  VS  VS
Toff T  Toff 1
It is seen from eqn (1), that average voltage across the load can be stepped up varying the duty cycle. In
practice, chopper is turned on and off so that α is variable and the required step – up average output
voltage, more than source voltage is obtained.

Example for step – up chopper:

Fig: 3.7(a) – Variation of load voltage V0 with duty cycle

Fig: 3.7(b) – Regenerative braking of DC motor

The principle of step – up chopper can be employed for the regenerative breaking of dc motors. This is
illustrated in fig (b) where motor armature voltage Ea represents VS of fig (a). Voltage V0 is the dc source
voltage. When CH is on, L stores energy. When CH is off, L releases energy. In case Ea/(1 – α) exceeds V0,
dc machine begins to work as a dc generator and armature current Ia flows opposite to motoring mode.
Power now flows from dc machine to source V0 causing regenerative breaking of dc motor. Motor armature
voltage Ea is directly proportional to field flux and motor speed. Therefore, even at decreasing motor
speeds, regenerative breaking can be made to take place provided duty cycle and field <??> Ea/(1 – α) is
more than the fixed source voltage V0.

14. a) CURRENT SOURCE INVERTERS

The inverters are fed from a voltage source and the load current is forced to fluctuate from positive to
negative, and vice versa. To cope with inductive loads, the power switches with freewheeling diodes are
required, whereas in a current – source – inverter (CSI), the input behaves as a current source. The output
current is maintained constant irrespective of load on the inverter and the output voltage is forced to
change. The circuit diagram of single – phase transistorized inverter is forced to change. The circuit
diagram of single – phase transmission <??> is shown in fig. 4.33(a). Because there must be a continuous
current flow from the source, two switches must always conduct – one from the upper and one from the
lower switches. The conduction sequence is 12, 23, 34 and 41 as shown in fig. 4.33(b). The switch states
are shown in table 4.2. Transistors Q1 and Q4 in fig act as the switching devices S1, S4 respectively. If two
switches, one upper and one lower, conduct at the same time such that the output current is ± IL, the switch
state is 1: whereas if these switches are off at the same time, the switch state is 0. The output current
waveforms are shown in fig. 4.33(c).

Fig. 4.33(a) Transistor CSI

 When two devices in different arms conduct, the source current IL flows through the load. When two
devices in the same arm conduct, the source current is by passed from the load.

The load current can be expressed as


4I L n
i0  
n 1, 3, 5 n
sin
2
sin n (t ) … (4.66)

Fig 4.33 Single phase current source

State State No Switch State i0 Component

S1 S2 S3 S4 conducting
S1 and S2 are on & S4 and S3 are 1 1100 It S1 & S2, D1 & D2
off
S3 and S4 are on & S1 and S2 are 1 0 0 11 -IL S3 & S4, D3 & D4
off
S1 and S4 are on & S3 and S2 are 1 1001 0 S1 & S4, D1 & D4
off
S3 and S2 are on & S1 and S4 are 1 0110 0 S1 & S2, D3 & D2
off

Table 4.2 – Switch states for a full – bridge single – phase current source inverter (CSI)

Fig: 4.34(a) – Circuit

Fig 4.34(a) shows the circuit diagram of a three – phase current source – inverter. The waveforms for
gating signals and line currents for a Y – connected load are shown in fig 4.34(b). At any instant, only two
thyristors conduct at the same time. Each device conducts for 120°. The instantaneous current for phase a
of a Y – connected load can be expressed as


4I L n  
ia  
n 1, 3,5 n
sin
3
sin n  t  
 6
… (4.67)

Te instantaneous phase current for a delta – connected load is given by


4I L  n 
ia   sin   sin (nt ) for n  1,3,5 … (4.68)
n 1 3n  3 

A current source inverter that utilizes capacitors to turn off the switching devices such as thyristors as
shown in fig 4.35. Let us assume that T1 and T2 are conducting, and capacitors C1 and C2 are charged with
polarity as shown. Firing of thyristors T3 and T4 reverse biases thyristors T1 and T2. T1 and T2 are turned off
by impulse commutation. The current now flows through T2 C1 D1, load and D2 C2 T4. The capacitors C1
and C2 are discharged and recharged at a constant rate determined by load current Im = IL. When C1 and C2
are charged to the load voltage and their currents fall to zero, the load current is transferred from diode D1
to D3 and D2 to D4 and D2 are turned off when the load current is completely reversed. The capacitor is now
ready to turn off T3 and T4 if the thyristors T1 and T2 are fired in the next half cycle. The diodes in fig 4.35
isolate the capacitors from the load voltage.
Fig: 4.34 - Three – phase current source transistor inverter

Fig: 4.35 - Single – phase thyristor CSI

Advantages:

i) Since the input de current is controlled and limited, misfiring of switching devices, or a short
circuit would not be serious problems.
ii) The peak current of power devices is limited
iii) The commutation circuits for thyristors are simpler
iv) It has the ability to handle reactive or regenerative load without free wheeling diodes.
14. b) Degree Conduction
In this type of control, each transistor conducts for 120°, only two transistors remain on at any instant
of time. The gating signals are shown in fig 4.0. The conduction sequence of transistors is 61, 12, 23, 34,
45, 56, 61. There are three modes of operation in one half-cycle and the equivalent circuits for a Y –
connected load as shown in fig 4.10. During mode 1 for 0 ≤ ωt ≤ π/3, transistors 1 and 6 conduct.

During mode 2 for π/3 ≤ ωt ≤ 2π/3, transistors 1 and 2 conduct.

Vs Vs
Van  Vbn  0 Vcn 
2 2

During mode 3 for 2π/3 ≤ ωt ≤ 3π/3, transistors 2 and 3 conduct

Vs Vs
Van  0 Vbn  Vcn 
2 2

The line – to – neutral voltages are shown in fig. 4.9 can be expressed in fourier series as


2Vs  n   
Van  
n 1,3,5 n
sin 
 3
 sin n  t   …… (4.24 a)
  6


2Vs n  
Vbn  
n 1,3,5 n
sin
3
sin n  t   …… (4.24 b)
 2


2Vs n  7 
Vcn  
n 1,3,5 n
sin
3
sin n  t 

 ……. (4.24 c)
6 

The line a – to – b voltage is Vab  3Van with a phase advance of 20°. Therefore the instantaneous line
– to – line voltage are
Fig: 4.9 - Gating signals for 120° conduction

Fig: 4.10 - Equivalent circuits for Y – connected resistive load


2 3Vs  n   
Vab   sin   sin n  t   for n  1,3,5 …….. (4.25 a)
n 1 n  3   3


2 3Vs  n   
Vbc   sin   sin n  t   for n  1,3,5 …….. (4.25 b)
n 1 n  3   3


2 3Vs  n 
Vca   sin   sin n t    for n  1,3,5 ……. (4.25 c)
n 1 n  3 

Therefore is a delay of π/9 between turning off Q1 and Q4. At any time, two load terminals are
connected to the de supply and the third one remains constant.
15. a) MULTISTAGE SEQUENCE CONTROL OF VOLTAGE CONTROLLERS:

Multistage sequence control of ac voltage controllers is employed when it is desired to have harmonic
content lower than that in a two – stage sequence control. The fig 5.8 shows the power circuit for n – stage
sequence control of voltage controllers.

In this figure, the transformer has n secondary windings. Each secondary is rated for Vs/n where Vs is
the source voltage. Voltage of terminal a with respect to 0 is Vs. Voltage of terminal b is (n-1) Vs/n and so
on. If voltage control from Vdo = (n - 3) Vs/n to Vco = (n – 2) Vs/n is required, then thyristor pair 4 is fired at
α = 0° and the firing angle of thyristor pairs are kept off. Similarly, for controlling the voltage from Vbo =
(n – 1) Vs/n to Vao = Vs, thyristor pair 2 is triggered at α = 0° whereas for pair 1, α is varied from 0° to 180°
by keeping the remaining (n – 2) SCR pairs off. Thus, the load voltage can be controlled from Vs/n to Vs by
an appropriate control of triggering the adjacent thyristor pairs.

Fig: 5.8 – Multistage sequence control of voltage controllers

The presence of harmonies in the output voltage depends upon the magnitude of voltage variation. If
this voltage variation is a small fraction of the total output voltage, the harmonic content in the output
voltage is small. For example, for voltage control from (n – 2) Vs/n to (n – 1) Vs/n, if voltage variation is
Vs/n << (n – 1) Vs/n, then the harmonic content in the output voltage would be small.
15. (b) SINGLE – PHASE TO SINGLE – PHASE CIRCUIT STEP – DOWN CYCLO
CONVERTER:
A step – down cyclo converter does not require forced commutation. It requires phase – controlled
converters connected as shown in fig 5.9(a). These converters need only line, or natural, commutation
which is provided by ac supply. Both mid – point and bridge – type cyclo converters are described as
follows:

Mid - point cyclo converter:

This type of cyclo converter will be described for both continuous as well as discontinuous load
current. The load is now assumed to consist of R and L in series.

Fig: 5.11 - Voltage and current waveforms for step - down cyclo converter with discontinuous load
current

a) Discontinuous load current:

When a is positive with respect to 0 in fig. 5.11(a) forward biased SCR P1 is triggered at ωt = α. With
this, load current i0 starts building up in the positive direction from A to 0. Load current i0 becomes zero at
ωt = β > π but less than (π + α), fig. 5.11(c). Thyristor P1 is thus naturally commutated at ωt = β which is
already reverse biased after π. After half a cycle, b is positive with respect to 0. Now forward biased
thyristors P2 is triggered at ωt = = π + α. Load current is again positive from A to 0 and builds up from zero
as shown in fig. 5.11(c). At ωt = π + β, i0 decays to zero and P2 is naturally commutated. At 2 π + α, P1 is
again turned on load current in fig. 5.11(c) is seen to be discontinuous. After four positive half cycles of
load voltage and load current, thyristor N2 (after P2, N2 should be fired) is gated at (4 π + α) when 0 positve
with respect to b. As N2 is forward biased, it starts conducting but load current direction is reversed, i.e, it is
now from 0 to A, after N2 is triggered, load currents builds up in the negative direction as shown in fig.
5.11(c). In the next - half cycle, 0 is positive with respect to a but before N1 is fired, i0 decays to zero and
N2 is naturally commutated. Now when N1 is gated at (5 π + α), i0 again builds up but it decays to zero
before thyristor N2 in sequence and again gated. In this manner, four negative half cycles of load current
and load voltage, equal to the number of four positive half cycles, are generated. Now P1 is again triggered
to fabricate further four positive half cycles of load voltage and so on. For discontinuous load current,
natural commutation is achieved, i.e, P1 goes to blocking state before P2 is gated and son on.

In fig. 5.11 mean output voltage and current waves are also shown. It is seen from this figure that
frequency of output voltage and current is f0 = 1/4fs.

b) Continuous load current:

When a is positive with respect to 0 in fig. 5.12(a), P2 is triggered at ωt = α, positive output voltage
appears across load and load current starts building up, fig. 5.12(c). At ωt = π, P1 is reverse biased. As load
current is continuous, P1 is not turned off at ωt = π. When P2 is triggered in sequence at π + α, a reverse
voltage appears across P1, it is therefore turned off by natural commutation. When P1 is commutated, load
current has built up to a value equal to RR, fig. 5.12(c). With the turning on of P2 at (π + α), output voltage
is again positive as it was with P1 on. As a result, load current builds up further than RR as shown in fig.
5.12(c). At (2π + α), when P1 is again turned on, P2 is naturally commutated and load current through P1
builds up beyond RS as shown. At the end of four positive half cycles of output load voltage, load current
is RU. When N2 is now triggered after P2, load is subjected to a negative voltage cycle and load current i0
decreases from positive RU to negative AB (say) as shown in fig. 5.12(c). Now N2 is commutated and N1 is
gated at (5π + α). Load current i0 becomes more negative than AB at (6π + α), this is because with N1 on,
load shown in fig. 5.12(c). Load current waveform is redrawn in fig. 5.12(d) under steady state conditions.
It is seem from load current waveform that i0 is symmetrical about ωt axis in fig. 5.12(d). The positive
group of voltage group and current wave consists of four pulses and same is true for negative group of
wave. One positive group of pulses along with one negative group of identical pulses constitute one cycle
for the load voltage and load current. The supply voltage has, gone through four cycles.

The output frequency is, therefore,

Fig. 5.12 Voltage and current waveforms for step - down cyclo converter with continuous load current

Bridge – type cyclo converter:

It consist of a total of eight thyristors. P1 to P4. i.e. four for positive group and remaining four for
negative group. When a is positive with respect to x in fig. 5.13(a) i.e, during the positive half cycle of
supply voltage of figure, thyristor pairs P1. P2 and N1. N2 are forward biased from ωt – 0° to ωt – π. When
forward biased thyristors P1. P2 are turned on together at ωt – 0°, then load voltage is positive with respect
to x, forward biased thyristors P1. P2 are turned on together at ωt – 0 so that load voltage is positive with
terminal A positive with respect to 0.

Load voltage now traverses two positive envelope of supply voltage, fig. 5.13(a) at <??> pair P1. P2 is
force commutated and forward biased pair N1, N2 are turned on. With this, load voltage is negative with
terminal 0 positive with respect to A. Load voltage now follows the negative envelope of source voltage
figure. At ωt2. N2. N2 are force commutated and P1. P2 are turned on. Two load voltage is now positive and
follows two positive envelope of source voltage. After ωt = π, thyristor pairs P3. P4 and N3. N4 are forward
biased, these can therefore be turned on and force commutated from ωt - π to ωt - 2π. In this way, a high –
frequency turning on and force commutation of pairs P1. P2. N1. N2 and P3. P4, N3. N4 gives a carrier -
frequency modulated output voltage across load terminals.
Fig. 5.13(a) Bridge type cyclo converter

(b) – Voltage and current waveforms for bridge type cyclo converter
 B.E./B.Tech. DEGREE EXAMINATION,
APRIL/MAY 2010
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions
PART A (10 × 2 = 20 marks)
1. Why is the current gain low at high current levels in a power transistor?

2. What are the advantages of a MOSFET in switching applications?

3. What are the advantages of three phase converter over single phase
converter?

4. Draw the output voltage of the converter as a function of firing angle.

5. What are the methods of controlling the output voltage of a chopper?

6. Give the application of SMPS.

7. Why is PWM inverter superior than the square wave inverter?

8. Compare between 180° and 120° mode inverter operation.

9. What are the types of shunt compensator?

10. Define transfer time and backup time for UPS.

EEE_Semester-V_Ch06.indd 49 7/7/2012 5:07:40 PM

 6.50 B.E./B.Tech. Question Papers

PART B (5 × 16 = 80 marks)
11. (a) (i) Draw the dynamic characteristics of SCR during turn on and
turn off and explain.
(ii) Draw the simplified model of a MOSFET to show the interelec-
trode capacitance. Discuss the importance of these capacitances.
Or

(b) (i) Describe the structure of an IGBT.

(ii) Calculate the switching losses of an IGBT for the following
condition both for resistance and clamped inductive load. Vcc =
200 V, tf1 = 0.5 µs, Icm = 50 A, trv = 0.5 µs, f = 20 Hz, tf2 = 25 µs.

12. (a) Discuss the effect of source inductance on the performance of single
phase full converter.
Or
(b) Draw the necessary circuit of single phase full converter with RL
load, voltage and current waveforms and explain its operation.
Obtain the expression for the average output voltage.

13. (a) (i) Derive the expression for the output voltage of a step up chop-
per and explain its control strategies.
(ii) A step up chopper supplies a load of 480 V from 230 V DC
supply. Assuming the non conducting period of thyristor to be
50 µ sec. Find the on time of the thyristor.
Or

(b) (i) Draw the power circuit diagram of buck boost regulator and
explain its operation with equivalent circuit for different modes
with necessary waveforms.
(ii) Compare linear and switched mode power supplies.

14. (a) (i) State the different methods of voltage control in inverters.
Describe any one of the PWM control in inverter.
(ii) Draw the power circuit diagram of a 3 φ transistorised inverter
and explain its function.
Or

EEE_Semester-V_Ch06.indd 50 7/7/2012 5:07:40 PM

 Power Electronics (April/May 2010) 6.51

(b) (i) Compare CSI and VSI.

(ii) Explain the operation of single phase capacitor commutated
CSI with R load and necessary waveforms.

15. (a) With the help of block diagram explain the operation of online UPS.
Why is it called as inverter referred UPS?
Or

(b) (i) Write a short note on UPFC.

(ii) State and explain the different types of DC links in HVDC.

EEE_Semester-V_Ch06.indd 51 7/7/2012 5:07:40 PM

 Solutions
PART A
Ic
1. The current gain of power transistor =
Ib
Also, the current has two components, one due to the base current and
the other is the leakage current of the collector base junction. Hence,
when the base current increases, the collector current also increases
hence, the current gain is low.

2. MOSFETs are voltage controlled devices and less sensitive to junction

temperature. There is no secondary breakdown and no need for negative
gate voltage during turn off. Parallel operation of MOSFETs is also easy.

3. • Ripple content in the DC output voltage is less.

• Power handling capacity is high.

V
o/p
4.
Vo

wt
O a p p+a 2p 2p + a

Vi

Output of a Pulse Converter with R Load

5. • Time ratio control

– Pulse width modulation
– Frequency modulation
• Current limit control

6. • Computers, printers, monitors

• Battery charges, electronic ballasts
• Television sets, DVD players
• Video games, toys.

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 Power Electronics (April/May 2010) 6.53

7. • The output voltage control can be obtained without any additional

components.
• Lower order harmonics can be eliminated (or) minimized signifi-
cantly in this inverter as the higher order harmonics can be filtered
easily.

8.
180° mode operation 120° mode operation

• A maximum of 3 thyristors • At any instant only two

conduct at any instant. thyristor conduce.
• Each thyristor conducts for 180° • Each thyristor conducts for
in every cycle of the output. 120° duration in every cycle of
output.
• Simultaneously incoming of • There is a 60° interval between
outgoing thyristors are to be the turning OFF of outgoing
turned ON and turned OFF and turning ON of incoming
respectively, chances of short thyristors, commutation is
circuit of source is more. more reliable.
Po
• Utility factor, U F = is more. • Utility factor is less.
PT
where PT is power handling
capacity of thyristor.

9. • SVC: Static VAR Compensator

– TCR
– TSC
– FC - TCR
• STATCOM

10. Transfer time is the time taken by the UPS to switch from mains to the
battery backup in case of mains failure (or) from battery power to mains
power when normal power is restored. It is less than 5 minutes.
Backup time is the time period for which the UPS is required to support
the load in case of mains failure.

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 6.54 B.E./B.Tech. Question Papers

PART B
11. (a) (i) Dynamic Characteristics
SCR: Silicon Controlled Rectifier
Turn-ON Characteristics
• When a thyristor is forward biased i.e, with positive VAK, with
gate circuit open, the junctions J1, J3 are forward biased but
junction J2 is reverse biased.
• In this condition, a small current called forward leakage cur-
rent, flows (Forward Blocking Mode).
• If forward VAK is increased, the reverse biased junction J2 will
have an avalanche breakdown at a voltage called forward
break over voltage VBO.
• When forward VAK is less than VBO , thyristor offers a high
impedance. Hence, SCR acts as an open switch in forward
blocking mode.
• If a thyristor is forward biased, the injection of gate cur-
rent by applying positive gate voltage between the gate and
cathode terminals turns ON the SCR. As the gate current
is increased, the forward blocking voltage is decreased, and
SCR turns ON (Forward Conduction Mode).
• In forward conduction mode, SCR is in ON-state and
behaves like a closed switch. Voltage drop across SCR is in
the order of 1 to 2 V.
• The gate signal should be removed after the thyristor is
turned ON. A continuous gating signal would increase the
power loss in the gate junction.
Turn On Time (Ton)
ton time is a transition time of SCR during which it changes from
forward OFF state to forward ON state.
It can also be defined as the time interval between 10% of steady
state gate current (0.1 Ig) and 90 % of steady state thyristor
ON-state current (0.9 IA).
ton = td + tr + ts
td delay time is the time interval between 10 % of gate current
(0.1 Ig) and 10 % of thyristor ON state current (0.1 IA)

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 Power Electronics (April/May 2010) 6.55

tr rise time t is the time required for the anode current to rise
from 10 % of ON state current (0.1 Ia) to 90 % of ON state cur-
rent (0.9 Ia).
ts spread time is the time taken by the anode current to rise from
0.9 Ia. During this time, conduction spreads over entire cross-
section of the cathode of SCR. After the spread time, anode
current attains steady state value.
∴ Total turn on-time of SCR is the sum of delay time, rise time
and spread time.
SCR manufactures usually specify the rise time which is of the
order of 1 to 4 m sec.

Vg
Gate Pulse

Va

0.9 Va

0.9 Ig
On State Voltage Drop
Ig
Across SCR
0.1 Ig 0.1 Va
t

Ia

Recovery Recombination
0.9 Ia

Qrr
0.1 Ia
t1 t2 t3 t4
t
Forward Steady
Leakage td tr ts State
Current ton Operation trr tgr
(Va Ia ) tq
Power tc
Loss

ton = td + tr + ts tgr – Gate Recovery time

tq = trr + tgr tq – SCR turn OFF time
trr - Reverse Recovery time tc – Circuit turn OFF time

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 6.56 B.E./B.Tech. Question Papers

Turn OFF Mechanism

Turn OFF process (or) the communication process is the
dynamic process that is used to bring the SCR from conducting
state to blocking state.
To turn off SCR, the following methods are adopted.
• Reducing the anode current below its holding current. This
can be achieved through natural (or) forced communication.
• Application of reverse voltage.
At the instant, IA is zero, if we apply forward VAK to the SCR,
the device will not be able to block this forward voltage due
to the fact that excess charge carries in all the junctions are
still favourable for conduction. So immediately the device starts
conducting, though gate signal is not applied.
Hence, reverse biasing of SCR (after Ia = 0) is essential to
remove these excess charge carries from all the four layers.

Turn OFF Time

Turn-OFF time can be defined as the time elapsed between
the instant, anode current becomes zero and the instant SCR
regains its forward blocking capability.

Turn-OFF time encounters,

• Reverse recovery process
• Gate recovery process
• In reverse recovery process, the excessive carriers from top
p layer and bottom n layer are removed. Time in current dur-
ing this process is reverse recovery process time (trr).
• In Gate recovery process excessive carriers (trapped charges)
from junction.J2 are the time incurred during this process is
hate recovery time (tgr).
• At t1, IA = 0
• After t1, IA build up in the reverse direction with the same
slope di/dt as before t1; due to the fact that charge carries are
stored in four layers.
• The reverse recovery current removes excess carriers from
the junctions J1 and J3 during t1–t3.

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 Power Electronics (April/May 2010) 6.57

• At t2, 60 % of stored charges are removed there by decreas-

ing the charge carrier density at J1 and J3. This results in
decay of reverse recovery current.
• This fact decay of Irr causes reverse voltage across the device
due to circuital inductance.
• At the end of t3, all the charge carries at J1 and J3 are removed
but still SCR is favourable for conductor due to charge car-
riers at J2.
• The excessive carriers at J2 can be removed by applying
reverse voltage at t4.
• Turn OFF time of SCR is generally in the order of
(3 – 100) μ s.
tq = trr + tgr ; t q < tc

• tc is the circuit turn OFF time that elapsed between the

instant Ia = 0 and the instant reverse voltage due to particular
circuit reaches zero.

(ii) Power MOSFET

Switching Model of MOSFET

Cgd
Gate Drain

Cgs Cds rds gmvgs

Source

• The gate structure has parasitic capacitances to the source

Cgs and to the drain Cgd. The drain to source capacitance
is Cds.
• The switching times are determined by the ability of the
drive, to charge and discharge a tiny input capacitance,
Cin = CGs + C gd with Cds shorted.

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 6.58 B.E./B.Tech. Question Papers

Turn ON Process
The turn ON time ton = t dn + t r
Where tdn turn ON delay time.
• The turn ON delay time is the time that is required to charge
the input capacitance to threshold voltage level (VGST).
• The turn ON rise time (tr) is the gate charging time from the
threshold level (VGST) to full gate voltage (VGSP).

Turn OFF Time

As MOSFET is a majority carrier device, the turn OFF process
get initiated soon after removal of gate voltage.
Turn OFF time is given by,
Toff = tdf + tf

tdf: Turn OFF Delay Time

Turn OFF delay time is the time required for the input capaci-
tance to discharge from the over drive gate voltage (V1) to the
pinch OFF voltage. (VGSP) VGS must decrease significantly
before VDS begins to rise.
tf : Fall time
During fall time the input capacitance discharge from the pinch
off region to threshold voltage (VGST). If VGS ≤ VGST the MOSFET
turns OFF.
• During fall time, the drain current falls from ID to zero.
• The switching characteristics of a power MOSFET are influ-
enced to a large extent by the device internal capacitance and
internal impedance of gate drive circuit.

ID
D

RD (Load)
R VDs

G
VG
(Vi ) VDD
VGs
S

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 Power Electronics (April/May 2010) 6.59

Switching Characteristics
VG

V1

VGS

V1
VGSP

VGST
t

ID

ID

tdn
tr tdf
tf

Ton t off

V 1 Over Drive Gate Voltage

VGSP Peak Gate to Source Voltage
VGST Threshold Gate to Source Voltage
Ton = tdn + tr
t off = tdf + tf

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 6.60 B.E./B.Tech. Question Papers

(b) (i) IGBT: Insulated Gate Bipolar Transistor

• IGBT is obtained by combining the properties of BJT and
MOSFET.
• The gate circuit of MOSFET and collector emitter circuit of
BJT is combined together to form the IGBT.
• IGBT has input impedance like MOSFET and low on state
conduction loss like BJT, but there is no secondary break-
down problem like BJT.
Construction: It is a voltage controlled device. It is bipolar.
• It is made of four alternate PNPN layers.
• On pt substrate a high resistivity n layer is grown epitaxillary.
• On thickness of n layer determine the voltage blocking capa-
bility of the device.
• On the other side of pt substrate a metal layer is deposited to
form the collector terminal.
• Now P region are diffuced in the epitaxially grown n layer,
and then n+ regions are difficult in P regions.
• The SiO2 layer is added and the emitter and gate terminal are
formed.
C
Collector PnP
C
nPn Resistance
G G Offered by
Gate E n-channel
Emitters
E
Symbol Equivalent Circuit

Structure of IGBT
VG
E

G
–+
+ –+–+
–+–+
–+–+ –
–
––– –
––– n+
n+ +
n –– –– n+

VC P P

n–

p + Substrate

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 Power Electronics (April/May 2010) 6.61

Working
• When Gate is +ve with respect to emitter and when VGE is
> Vthreshold an n–channel is formed in the P regions as in a
MOSFET. This shorts the n–region with n+ region.
• An electron movement in the n channel causes sustational
hole injection from Pt substrate layer into the epitarial n
layer. Therefore a forward current flows.
Equivalent Circuit
• The three layers P+ , n− , P contributes an pnp transistor with
Pt as emitter , n as base and P as collector.
• n−, P, n+ serves as npn transistor , here n− acts as collector.
V-I Characteristics

C
G
VC
E
VG

• V-I channels are drawn for different values of VGE.

• When VGE is > VGE(threshold) IGBT turns ON.
• By keeping VGE constant, the value of VCE is varied and cor-
responding values of IC is noted down.
• A graph is plotted between VCE and IC.
VGE 4 >VGE 3 >VGE 2 >VGE 1

Ic VGE4

VGE3

VGE 2

VGE1
VRM

VCE

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 6.62 B.E./B.Tech. Question Papers

Transfer Characteristics
• VCE is increased and maintained at a constant value.
• Now VGE is varied in steps and IC is noted down.
• Till VGE = VGE (th) the collector current is zero.
• Alfa VGE is > VGE (th) the collector current increases.

Ic

VGE
VGR (th)

Switching Characteristics
Turn ON
• VGE is normally negative. VGE is made positive to turn on
IGBT.
• As gate voltage is ↑ed , VGE ↑. When VGE = VGE(th) the collector
current IC starts to flow.
• Time taken for VGE to rise and reach VGE(th) (or) the time for IC
to starts ↑ing is called as turn on delay time tdn.

(ii) For Resistive Load

Switching loss during turn ON = Won × fs
VCE (max) I c (max) × ton . f
=
6
200 × 50 × 0.5 × 10 × 20
=
6
= 0.0167 W
200 × 50 × (0.5 + 25) × 10 −6 × 20
Switching loss during turn OFF =
6
= 0.85 W
Total switching loss = 0.867 W

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 Power Electronics (April/May 2010) 6.63

For Inductive Load

⎡ t rv + 1.1t f 1 + 0.1t f 2 ⎤
Pav = Vcc I cm . f ⎢ ⎥
⎣ 2 ⎦
⎡ 0.5 + 1.1(0.5) + 0.1(25) ⎤
= 200 × 50 × 20 ⎢ ⎥ × 10
−6

⎣ 2 ⎦
= 0.355 W

12. (a) Effect of Source Inductance (Ls) on Performance of Rectifier

with RL Load
i0

LS
R LS = Source Inductance
T1 T3
a
L = Load Inductance
VS v0
L
b

T4 T2

Equivalent Circuit
V1 LS T1 T2 i1
– +
a N b

V2 LS T3 T4 i2
– +
d N c

R L

i0
v0

• Load current i0 is assumed constant.

• When terminal a of source voltage is positive, current V1
flows through Ls, T1, load and T2 and this is shown in equiva-
lent circuit as V1 − Ls − T1 − T2 − RL load.
• When terminal b of source vge is positive; current i2 flows
through Ls, T3, load, T4 and this is shown in equivalent circuit
as V2 − Ls − T3 − T4 − RL load.
• When T1, T2 are triggered at firing angle α, the SCRs T3 T4
which have been already conducting will be commutating.

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 6.64 B.E./B.Tech. Question Papers

• ie., the current through the incoming SCRs T1, T2 builds up

very slowly, whereas due to foresence of source inductance
(Ls ) the current through the outgoing SCRs T3, T4 decreases
very slowly.
• ∴ during this period all 4 SCRs T1, T2, T3, T4 are conducting.
This period is called as overlap period and the angle is called
as overlap angle µ.

Working
From (a + µ to p + a)
• From wt = a + µ to p + a, SCRs T1 and T2 will be conducting.
• At wt = p + a, the supply Vge is negative.
• SCRs T3 and T4 are triggered at wt = p + a. ∴ current passes
through T3 , T4 es slowly.
• At wt = p + a, SCRs T1, T2 does not turn OFF because energy
stored in source inductance (Ls) induces a Vge that forward
biases T1 ,T2.
∴ from wt = p + a to wt = p + a + µ SCRs T1,T2, T3, T4 are
conducting. This period is called overlap period.
• At wt = p + a + µ current through T1, T2, reduces to zero and
turns OFF and current through T3,T4 reaches maximum value.

From the Equivalent Circuit

Vge across ab = Vge Cd ( ∵ they are parallel paths)
ie.,
di1 di2
V1 − Ls . = V2 − Ls
dt dt
di1 di2 ⎡ di di ⎤
V1 − V2 = Ls − Ls = Ls ⎢ 1 − 2 ⎥
dt dt ⎣ dt dt ⎦
V1 = Vm sin wt; V2 = − Vm sin wt; ∴V1 − V2 = Vmsin wt − (− Vm sin wt)
V1 − V2 = 2Vm sin wt

⎡ di di ⎤ di di 2V
∴2Vm =Vm sinω t = Ls ⎢ 1 − 2 ⎥ ; 1 − 2 = m sinω t (1)
⎣ dt dt ⎦ dt dt Ls

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 Power Electronics (April/May 2010) 6.65

V1 V2

p 2p 3p

Ig1, Ig2
a a+p p u2 u3
Ig3, Ig4 u
a+p p + a + u 2p 2p + a 2p + a + u

T1 T2 T3 T4 T1 T2
a p+a 2p + a

a+p p p+a+u 2p 2p + a + u

T2 X1

i0

a a+p p p+a p+a+u 2p 2p + a 2p + a + u

T1T2 T3T4 T1T0

T1T2 T1T2
T3T4 T3T4

All All
SCRs SCRs
ON ON

We know that i1+ i2 = i0 [but i0 is constant]

di1 di2
∴ + =0 (2)
dt dt
On adding equation 1 and 2

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 6.66 B.E./B.Tech. Question Papers

di1 di2 di1 di2 2Vm sin ω t di1 2Vm

+ + − = ;2 = sin ω t .
dt dt dt dt Ls dt Ls
di1 Vm
∴ = sin ω t
dt Ls
Vm
di1 = sin ω t .dt
Ls
α+μ α
w.k .t : i1 = i0 at ω t = α + μ (or ) t = ; i1 = 0 at ω t = α (or )t =
ω ω
(α + μ )
α+μ
−V ⎡ cos ω t ⎤ ω
i0 ω
Vm
∴ ∫ di1 = ∫α sin ω t .dt ;[i ] = m ⎢
i0

0
Ls Ls ⎣ ω ⎥⎦ α
1 0
ω
ω

Vm ⎡ α+μ α⎤
∴ i0 = − ⎢ cos ω + − cos ω + ⎥
ω Ls ⎣ ω ω⎦
V
i0 = m [cos α − cos(α + μ ) ] (3)
ω Ls
α +π
1 Vm α +π

π α∫ μ
V0 ( avg ) = V sin ω t .dω t = − [cos ω t ]α + μ
+
m
π
Vm Vm
=− [cos(α + π ) − cos(α + μ )] = − [ − cos α − cos(α + μ )]
π π
Vm
V0 ( avg ) = [cos α + cos(α + μ )] (4)
π

From Eqn 3

Vm
i0 = = [cos α − cos(α + μ ) ]
ω Ls
ω Ls
i0 = cos α − cos(α + μ ) (or )
Vm
ω Ls
cos(α + μ ) = cos sα − i0
Vm
(5)

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 Power Electronics (April/May 2010) 6.67

Substituting equation 5 in equation 4

Vm ⎡ ω Ls ⎤
V0 ( avg ) = ⎢cos α + cos α − i0 ⎥
π ⎣ Vm ⎦
2V ω Ls
V0 ( avg ) = m cos α − i0
π π
(6)
From equation 3

Vm
i0 = [cos α − cos(α + ω )] (or )
ω Ls
i0ω Ls
cos α = + cos(α + μ )
Vm (7)

Substituting equation 7 in equation 4

Vm ⎡ ω Ls ⎤
V0 ( avg ) = ⎢i0 + cos(α + μ ) + cos(α + μ ) ⎥
π ⎣ Vm ⎦
i ωL V
V0 ( avg ) = 0 s + 2 m cos (α + μ )
π π (8)

From equation 6 DC equivalent circuit is drawn as follows:

WLS
D p i0

Vm cos ∝ v0
p

(b) Refer answer 12(b)(i) from Nov/Dec 2011 Question paper.

13. (a) (i) Step Up Choppers (or) Boost Converter

• A chopper which produces output voltage greater than
source voltage is called as step up chopper.
i.e., V0 > Vs

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 6.68 B.E./B.Tech. Question Papers

L D

i0

+ L
Vs CH O V0
–
A
D

• A large inductor L is connected in series with source voltage

Vs.
• The chopper is kept ON for a period TON and the chopper is
kept OFF for a period TOFF.

During the Turn ON Period TON

• Chopper CH is ON.
• Closed path is shown in the figure.
• Curve i flows in closed path.
di
• Inductor stores energy during TON period VL = L .
dt
• ∵ CH is ON; V0 = 0; i0 = slowly ↑ due to L

L D

+ –
+
L
+ i O
Vs CH
– A
– D

During the Turn OFF Period TOFF

• Chopper CH is OFF.
• i0 decreases slowly due to L
• As i0 decreases, polarity of emf induced in inductor L is
reversed.

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 Power Electronics (April/May 2010) 6.69

L D

+ –
+
L
Vs O
CH
A
– D

∴ voltage across load V0 = Vs + Ldi

dt
∴ V0 is greater than vs., because inductor voltage odds up with
source voltage.
∴ i0 slowly decreases.

When CH is ON
di
VL = L  Vs
dt
∴VL = Vs

When CH is OFF

di di
V0 = Vs + L VL = L
dt dt
∴V0 = Vs + VL
(or )VL = V0 − Vs

Energy input to the inductor (VL = Vs during TON)

From source during TON = Wi = VL × i = TON =Vs × i × TON

Energy output from = W0 = VL× i × TOFF =

the inductor (V0 − V0) × i × TOFF
to load during TOFF (during TOFF VL=(V0 − Vs))

Considering a lossless system; = energy output

energy input

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 6.70 B.E./B.Tech. Question Papers

∴ ωi = ω0
Vs × i × TON = (V0 − Vs ) × i × TOFF
VsTON = (V0 − Vs )TOFF
V0TON = V0TOFF − VsTOFF
Vs (TON + VsTOFF ) = V0TOFF
TON + TOFF
∴V0 = Vs ×
TOFF
TON + Toff = T
TON + TOFF
∴Vo = Vs ×
TOFF
TOFF = T − TON
T T 1
∴V0 = Vs × = Vs × = Vs ×
T − TON T T
T (1 − ON ) 1 − ON
T T
TON
=α
T
1 V
∴V0 = Vs × = s
1− α 1− α
Vs
∴V0 =
1− α
For α = 0;V0 = Vs
For α =1;V0 = ∞ → infinity
∴ For variation of α b/w; 0 < α <1; V0 varies between Vs< V0 < ∞

Note:
When V0 > Vs, regeneration takes place.

i0

t
TON TOFF TON TOFF

V0
TON TOFF

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 Power Electronics (April/May 2010) 6.71

Control Strategies
There are two types of control
(i) Time ration control (TRC)
(ii) Current limit control

Time Ration Control

V0 = αVs

By vary α we can vary V0

TON
α = duty cycle =
T
TON 1
α= = * TON = f .TON
T T
∴ α = f .TON

α can be varied by varying f (or) TON

• constant frequency system: [f constand, TON varying]
• variable frequency system: [varying f]

a) Constant Frequency System (or) Pulse Width

Modulation Control
T = TON + TOFF.
In this method, TON and TOFF is varied but frequency is kept
constant.
1
TON TON T
1
α= ; If TON = T then α = = 4 = 25%
T 4 T T

∴V0 = αVs = 25% of Vs ;

3
TON T
3
If TON = T ;α = = 4 = 75%
4 T T

∴V0 = αVs = 75% of Vs

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 6.72 B.E./B.Tech. Question Papers

V0

TON TOFF

T t

1
Varying TON, Keeping f Constant f = ∴ T is Constant
T

V0
TON TOFF

T t

b) Variable Frequency System (or) Frequency Modulation

Control
• Here f is varied and either TON (or) TOFF can be maintained
constant.

V0
TON TOFF

Keeping TON Constant

V0
TON TOFF

Keeping TOFF Constant

V0
TOFF TON

V0
TOFF TON

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 Power Electronics (April/May 2010) 6.73

(ii) Current Limit Control

• In this method the chopper is switched ON and OFF so that
the load current is maintained between two limit
• I0 (min) is minimum current limit.
• I0 (max) is maximum current limit.
• when current exceed I0(max) the chopper is turned OFF
• when current reaches I0(min) the chopper is turned ON.
• This method is used only if load has energy storage
elements.

I0 (max)
i0

I0 (min)

v0

TON TOFF

Ton + Toff
(ii) The average o/p voltage, E0 = Edc
Toff
Given that,
E0 = 480 V
EDC = 230 V
Toff = 50 m sec

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 6.74 B.E./B.Tech. Question Papers

On substituting,
⎡T Toff ⎤
480 = 230 × ⎢ on + ⎥
⎣⎢ Toff Toff ⎥⎦
T
⇒ 480 = 230 × on + 230
Toff
Ton
480 − 230 = 230 ×
50 × 10 −6
⇒ Ton = 54.35 μ sec

13. (b) (i) Refer answer 13(b) from Nov/Dec 2011 Question paper.
(ii)
Linear Power Supply Switched Mode Power Supply
• Size and weight are large due to • Size and weight are smaller due
low operating frequency to higher operating frequency
(50 – 60 Hz). (typically 50 KHz – 1 MHz).
• If unregulated, the output voltage • Any voltage is available. Voltage
varies significantly with load. varies little with low.
With transformer used any
voltage can be obtained.
• Output can be regulated (or) • Output voltage is always
unregulated. If unregulated, regulated using duty cycle
transformer iron losses and control. The transistors are
copper losses are significant. always switched fully ON (or)
fully OFF. Hence, power loss and
heat loss are minimized.
• Mild, high frequency radio • EMI/RFI produced due to the
interface may be generated under current being switched ON and
heavy current loading. OFF sharply. Therefore, EMI
filters and RF shielding are
required.
• Risk of equipment damage is • Failure of a component in
very low. the SMPS itself can cause
further damage to other PSU
components. It can destroy even
the input stage amplifiers.

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 Power Electronics (April/May 2010) 6.75

• Electronic noise at input and • Noisier due to high switching

output terminal is very low (or) frequency.
no high frequency noise.
• AC ripples are considerably high. • Very loss AC ripples in the
output, which are of higher
frequency and can easily be
filtered.
• Filter circuit design is difficult to • Filter circuit design simple.
filter out low frequency ripples.

14. (a) (i)

• AC loads may require a constant or variable voltage at their
input terminals.
• When the load is fed by inverters, they should be controlled
to fulfill the requirements of the load.
• AC load may require a constant voltage. Therefore the AC
input voltage must be adjusted in order to get the constant
AC output.(or it may require a variable voltage)
• Various methods for control of output voltage of inverters are
– External control of AC output voltage
– External control of DC input voltage
– Internal control of inverter.

External Control of AC Output Voltage

This is done by two methods
• AC voltage control
• Series inverter control.
AC voltage control: Here an AC voltage controller is inserted
between the inverter and the load. Output of inverter is given to
AC voltage controller, and converted to a variable AC voltage
and given to load.

Constant AC Controlled AC
Invertor Voltage
Load
DC Voltage Controller AC Voltage

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 6.76 B.E./B.Tech. Question Papers

Series inverter control: Here, two or more inverters are con-

nected in series. Output of the inverter is fed to two transform-
ers whose secondaries are connected in series. Output voltage
to two inverters is summed up with the help of transformer to
get variable AC voltage.

Inverter 1 v 01 v 01

Constant
v 0 = v 01 + v 02
DC Voltage

Inverter 2 v 02 v 02

External Control of DC Input Voltage

• In this method, if the available voltage is AC then the DC i/p
to the inverter is controlled through a
– fully controlled rectifier (or)
– an uncontrolled rectifier and chopper (or)
– an AC voltage controller and an Uncontrolled rectifier
• If the available voltage is DC, then it is controlled by means
of chopper.

Constant Full Controlled Controlled Controlled

Filter Inverter
AC Voltage Rectifier DC Voltage AC Voltage

Constant Uncontrolled Controlled Controlled

Chopper Filter Inverter
AC Voltage Rectifier DC Voltage AC Voltage

Constant AC Voltage Uncontrolled Controlled Controlled

Rectifier Filter Inverter
AC Voltage Controller DC Voltage AC Voltage

Constant Controlled Controlled

Chopper Filter Inverter
DC Voltage DC Voltage AC Voltage

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 Power Electronics (April/May 2010) 6.77

Internal Control of Inverter

• Output voltage from an inverter can also be adjusted by
doing a control inside the inverter itself.
• The most commonly used method is Pulse Width Modulation
(PWM).
PWM Control
• Here the output voltage is controlled by adjusting the ON/
OFF periods of the switches in the inverter.
Advantages:
• O/P voltage is controlled without any additional components.
• Lower order harmonics are eliminated.
PWM Inverters
Various PWM techniques are
• Single pulse modulation.
• Multiple pulse modulation.
• Sinusoidal pulse modulation.
• Modified sinusoidal PNM.
(i) Single PNM

T1 T3
V0
+ –
V
R
T4 T2

• T1 , T3 are SCRs of positive group.

• T2, T3 are SCRs of negative group.
• Every SCR conducts for 120°.
• SCRs of same group conducts with delay of 60°
i.e., T3 conducts 60° after T1 and
T4 conducts 60° after T4.
• SCRs from different groups conduct with delay of 120°.
i.e., T4 conducts 120° after T1
T2 conducts 120° after T3.
∴ T1 is ON at wt = 0 ; T3 is ON at wt = 60°

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 6.78 B.E./B.Tech. Question Papers

T4 is ON at wt = 120° ; T2 is ON at wt = 180°
60°
T1 T3

120° 120°
60°
T4 T2

ig1

60 120 180 240 300 360 420

ig2

ig3

ig4

1,2 1,3 3,4 2,4 1,2 1,3 3,4

V0

• Based on the firing pulses available across the SCRs, it is

found which SCR conducts.
• For example, during first 60° T1, T2 conduct. Then V0 is positive.
• When T1T3 conduct the load is shorted ∴ V0 = 0.
• When T3T4 conduct V0 is negative.

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 Power Electronics (April/May 2010) 6.79

(ii) Refer answer 14 (a) from Nov/Dec 2011 Question paper.

(b) (i) Diode D1 is OFF

T3

D3
B

D2

T2

• When capacitor is completely charged left plate negative, the

diode D1 is reverse biased and turns OFF.
• D1 is OFF.
• Now load current flows through T3 − D3 − load − D2 − T2.
Similar modes follow for other sequences.
Differences between VSI and CSI
Voltage Source Inverter Current Source Inverter

• Input voltage is constant. • Input current constant.

• Current waveform depends • Voltage waveform depends
on load. on load.
• Short circuit can damage • Short circuit cannot
the circuit. damage the circuit.
• Freewheeling diodes • Freewheeling diodes are
are required in case of not required.
inductive loads.
(ii) 1j Capacitor Commutated CSI (with R Load)
• Capacitor is connected parallel to load.
• It has 4 SCRs.
T1 T3
Vc C
+ –
I
+ V0 –
i0 R
T4 T2

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 6.80 B.E./B.Tech. Question Papers

T1, T2 ON

ic C
T1 + –
I i i
R
T2
i0 + V –
0

• T1, T2 are ON at time t = 0.

• Current i flows through SCR T1, T2
• Current i0 flows through load
• Current ic flows through C
• ∵ R, C and in parallel V0 = Vc.
• Capacitor C charges with left plate positive and right side
plate negative to Vc = Vs, ∴V0 = Vc = +Vs.
• Now when at time t = t1, SCR T3, T4 are turned ON then the
voltage across C reverse biases T1, T2 and turns it OFF.

T3, T4 ON

C ic T3
i – +
V
I – c + i
V0
T4 R i0

• When T3, T4 is ON at t = t1, current i flows through T3 and T4.

• ic flows through C.
• i0 flows through R.
• ic charges C with left plate negative and right plate positive.
∴VC = – Vs.
V0 = Vc = – Vs.
• Now at t = t2 when T1, T2 are turned ON the capacitor voltage
reverse biases T3, T4 and turns them OFF.

1j Auto Sequential Commulated Inverter (1 φ ASCI)

• Capacitor are precharged with left plate positive.

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 Power Electronics (April/May 2010) 6.81

T1 C1 T3
+ –
VC1
D1 D3
Load

D4 V D2
+ C2–
C2
T4 T2

When T1 ,T2 are turned ON: When SCR T1, T2 are turned ON.
Load current flows through T1 − D1 − load D2 – T2. V0, i0 is
positive.

T1

D1 + v0 –
Load
i0 D2

T2

When T3 and T4 are ON: When T3 and T4 are ON, the capacitor
voltage Vc1 and Vc2 apply a reverse bias across SCR T1 and T2
respectively and turns them OFF.

T3
– +
C1
D1
+ v0 –
Load
i0
D2
– +
C2
T4

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 6.82 B.E./B.Tech. Question Papers

• Now load current flows through T3 − C1 − D1 − load − D2

−C2 − T4.
• Due to current flowing through C1 and C2 they are charged
with right plate positive and left plate negative.
• This increasing polarity on the capacitors forward biases
diodes D3 and D4.
• D1 and D2 are already ON.
Now all diode D1, D2, D3 and D4.
When D1, D2, D3, D4 ON: Here all four diodes are ON. Now
when the capacitors is completely charged with right side plate
positive the D1 and D2 are reverse biased by VC1 and VC2 and they
are turned OFF.

C1 T3
– +
VC1
D1 D3

Load
D4 D2
VC2
– +
C2
T4

Diodes D1, D2 turned OFF: Now when D1, D2 is OFF, the cur-
rent i0 flows through
T3 → D3 → load → D4 → T4
Now V0, i0 is negative. To turn OFF SCR T3, T4, SCR T1, T2 are
turned ON.

T3

D3
i0
Load
– V0 +
D4

T4

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 Power Electronics (April/May 2010) 6.83

15. (a) No Break Ups [or] Online UPS [or] Redundant UPS

Normally OFF

Load
Main dc ac
ac Rectifier Inverter Filter
Supply
Battery
Normally ON

• It is used when a no break supply is required.

• Here the main AC supply is rectified to DC by using rectifier. This
DC is used to charge the battery.
• The DC is also converted again to AC by an inverter and then
filtered and supplied to load, continuously using the normally ON
contact.
• In case of power failure the batteries immediately take over with
no break of supply.
• The DC stored in battery, is converted to AC by inverter and given
to load through the normally ON contact.
• If there is a fault in the inverter then the normally OFF contact
is closed and supply is directly given to load through normally
OFF contact.
Advantages of Short Break Ups
• High efficiency since charges is not continuously ON.
• Not very costly.
• Internal control is simpler.
Disadvantages of Short Break Ups
• Since main supply is given when it is present, the output contains
voltage spikes.
• Break in supply continuously when inverter takes ON.
• Output is not reliable.
Applications
• Computers, printers, scanners, emergency power supplies.

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 6.84 B.E./B.Tech. Question Papers

Advantages of No Break Ups

• Provides isolation between mains and load.
• Since inverter is ON, the load voltage is free from distortion.
• Voltage regulation is better.
• No break in supply.
Disadvantages of No Break Ups
• Overall efficiency of UPS is reduced since the inverter is
always ON.
• Costlier.
Applications
• Inductions motor drivers, motor control applications.
• Intensive care units, medical equipments.

(b) (i) Unified Power Flow Controller

A unified power flow controller (UPFC) consists of an advanced
shunt and series compensator with a common DC link, as shown
in the figure. The energy-storing capacity of the DC capacitor is
generally small. Therefore, the active power drawn (generated)
by the shunt converter should be equal to the active power gen-
erated (drawn) by the series converter. Otherwise, the DC-link
voltage may increase or degenerated by both converters. On the
other hand, the reactive power in the shunt or series converter
can be chosen independently, giving a greater flexibility to the
power flow control.
Power control is achieved by adding the series voltage Vinj to
Vs, thus giving the line voltage VL, as shown in the figure. With
two converters, the UPFC can supply active power in addition
to reactive power. Because any active power requirement can
be supplied through the shunt-connected converter, the applied
voltage Vinj can assume any phase with respect to the line cur-
rent. Because there is no restriction on Vinj, the locus of Vinj
becomes a circle centered at Vs with a maximum radius that
equals the maximum magnitude of Vinj = |Vinj|.
UPFC is a more complete compensator and can function in any
of the compensating modes, hence, its name. It should be noted
that the UPFC shown in the figure is valid for power flowing
from Vs to VL. If the power flow is reverted, it may be necessary

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 Power Electronics (April/May 2010) 6.85

to change the connection of the shunt compensator. In a more

general UPFC with bidirectional power flow, it would be neces-
sary to have two shunt converters: one at the sending end and
one at the receiving end.
Busbar Vinj
Transmission
Line

Series + Locus of Positions

+ Transformer of Vinj Relative to Vs
VL
Vs Step-down Vinj
Transformer
VL
Shunt Series
Vs
Voltage Voltage
Controller Sourced Sourced
Converter Converter

Setting 0

(a) Circuit Arrangement (b) Phasor Diagram

Key Points
• UPFC is a complete compensator.
• This compensator can function in any of the compensating
modes.
(ii) HVDC Transmission
• Electric power generated should be transmitted to the load
centres. Transmission of electric energy should be done with
minimum loss.
• Electrical energy is transmitted at very high voltages to
reduce losses.
• High voltage AC and DC transmission is possible. But high
voltage DC (HDVC) transmission is more economical and
efficient than HVAC transmission.
Basic HVDC Transmission System

A +KV B

AC Converter DC DC Converter AC
AC AC
Filter 1 Filter Filter 2 Filter

Step Up –KV Step Down

Transformer Transformer

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 6.86 B.E./B.Tech. Question Papers

• Two AC system A and B are interconnected by the DC line.

• If power flows from A to B, then converter 1 acts as a recti-
fier and converter 2 as an inverter.
• If power flows from B to A, then converter 2 acts as rectifier
and converter 1 as an inverter.
• The AC supply is first passes through AC filter to remove
harmonics and then stepped up through step up transformer.
• This high voltage AC is converted to high voltage DC by the
converter 1 which acts as rectifier.
• This DC output from converter is filtered by smoothing
inductors to remove the AC ripples, and is then transmitted
through the DC transmission line.
• DC transmission line has +KV and −KV with respect to
ground. This is to balance the voltage of two transmission
lines w. r. t the earth.
• At the receiving side, the DC voltage is filtered and given to
converter 2 which acts as an inverter.
• AC output from inverter is stepped down and passed through
AC filter. Thus the filtered AC output is obtained.

Types of HVDC Link

• Mono polar link.
• Bi polar link.
• Homo polar link.
Mono Polar (or) Uni Polor Link

–ve
–
3f 3f
AC – AC

Return Current

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 Power Electronics (April/May 2010) 6.87

• It uses a single conductor with either positive or negative

polarity.
• It is preferred to have negative polarity to the single conduc-
tor, as it produces less radio interference.
• The return path is provided by the ground.
• This is used for light loads.
• Return path through ground leads to higher conduction
losses.

Bipolar Link

+ve

3f – 3f
AC – AC

–
Return Current
–
–ve

• Two conductors are used.

• One conductor is positive and the other is negative with
respect to ground.
• Since the positive and negative conductors carry equal cur-
rent there is no earth current.
• In case of fault on one conductor, the other conductor with
ground will form a unipolar link and transmit half the rated
power until the fault is cleared.
• This is used for heavy loads.
• Power flows in both the directions.
• No ground return is required.

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 6.88 B.E./B.Tech. Question Papers

Homopolar Link

3f – 3f
AC – AC

–
–

• It has two or more conductors of the same polarity.

• Ground serves as return path.
• Used for medium loads.
• Corona effect is less.

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 B.E./B.Tech. DEGREE EXAMINATION,
NOV/DEC 2009
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions
PART A (10 × 2 = 20 marks)
1. What is holding current of SCR?

2. Define the pinch off voltage of MOSFET.

3. Why power factor of semi converter is better than full converter?

4. What are the basic requirements for the successful firing of the thyristor?

5. What are the disadvantages of frequency modulation scheme over pulse

width modulation scheme?

6. What do you mean by integral cycle control?

7. Mention the methods available for the output voltage control of inverters.

8. List the different types of PWM techniques.

9. What is on-line UPS?

10. Mention the different types of HVDC links.

PART B (5 × 16 = 80 marks)
11. (a) Discuss steady state and the switching characteristics of power
MOSFET.
Or
(b) Sketch the transverse and switching characteristics of IGBT.

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 6.90 B.E./B.Tech. Question Papers

12. (a) Explain the operating of three phase fully controlled rectifier sup-
plying R load with neat waveforms and also derive an expression for
average output voltage.
Or
(b) A single phase full converter is supplied from 230 V, 50 HZ source.
The load consists of R = 10 Ω and a large inductance so as to render
the load current constant. For a firing angle of 30 degree, determine.
(i) average output voltage
(ii) average output current
(iii) average and rms values of thyristor currents
(iv) the power factor.
Also if the source has an inductance of 1.5 mH, determine (1) aver-
age output voltage, (2) the angle overlap, (3) the power factor.

13. (a) Classify the basic topologies of switching regulators and explain the
operation of cuk converter.
Or
(b) Describe a ZVS resonant converter with appropriate circuits and
waveforms.

14. (a) Discuss the function of three phase voltage source inverter supply-
ing a balanced star connected load in 180 degree operating mode.
Or
(b) Explain the operation of single phase capacitor commutated CSI
with R load.

15. (a) Explain the operation of on-line and off-line UPS in detail.
Or
(b) Discuss the principle of operation of unified power controller as
compensator with a neat circuit arrangement.

EEE_Semester-V_Ch06.indd 90 7/7/2012 5:07:46 PM

 Solutions
PART A
1. The holding current may be defined as the minimum value of anode cur-
rent below which the SCR stops conducting and returns to its OFF state.
The value of this current is very small, usually in milliamperes.

2. If gate to source voltage ‘VGS’ is made negative enough, the channel will
be completely depleted, offering a high value of drain to source resis-
tance RDS. Hence, there will be no current flow from the drain to source,
i.e., IDS = 0. This value of VGS is called pinch off voltage.

3. For supplying given load, the semi converter receives less reactive power
due to free wheeling action of diodes present when compared to full
converter. Therefore the power factor is better than full converter.

4. The thyristor is turned ON when the forward anode to cathode voltage is

equal to or greater than forward break over voltage − VBO on the applica-
tion of gate trigger thyristor starts conducting due to regenerative active
with anyone of the following ways.
(i) Hate drive, (ii) Temperature triggering, (iii) High forward voltage,
(iv) dv/dt, (v) light triggering.

5. • Filter design is complex due to wide variation of frequency and pres-

ence of lower order harmonics
• Interference with signaling and telephone lines is high
• Load current is discontinuous due to large off time

6. In integral cycle control of AC voltage controllers, thyristor switches

connect the load to AC source for few cycles of in voltage and then
disconnect it for another few cycles. This method is also called ON-OFF
control.

7. • External control of AC output voltage

• External control of DC input voltage
• Internal control of inverters
– Series inverter control
– Pulse width modulation control

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 6.92 B.E./B.Tech. Question Papers

8. • Single PWM
• Multiple PWM
• Sinusoidal PWM
• Space vector modulation
• Multiple sinusoidal PWM
9. In on-line UPS, when the main supply is present, the rectifier/charger
provides power to inverter as well as battery. The battery is charged and
inverter is ON, feeds power to load. When the main supply is not avail-
able, then battery bank supplies power to an inverter. Thus the inverter is
always ON and it takes power from rectifier or battery.
10. • Monopolar DC link
• Homopolar DC link
• Bipolar DC link

PART B
11. (a) Refer answer 11(a)(ii) from April/May 2010 Question paper.
(b) Switching Characteristics
• IGBT is designed such that the turn ON and turn OFF times of
the device can be controlled by the gate – emitter impedance
• The device is turned ON by applying a positive voltage between
the gate and emitter terminals.
Transfer Characteristics
• VCE is increased and maintained at a constant value
• Now VGE is varied in steps and IC is noted down
• Till VGE = VGE (th) the collector current is zero
• Alfa VGE is > VGE (th) the collector current increases

Ic

VGE
VGR (th)

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 Power Electronics (Nov/Dec 2009) 6.93

12. (a) Refer answer 12(a) from Nov/Dec 2011 Question paper.
(b) A single phase full converter is supplied from 230 V, 50 Hz source.
The load consists of R = 10 Ω and a large inductance so as to render
the load current constant. For a firing angle of 30 degree, determine,
• Average output voltage
• Average output current
• Average and rms value of thyristor current
• The power factor
Also if the source has an inductance of 1.5 mH, determine
• Average output voltage
• The angle overlap
• The power factor
For 1φ full converter, average output voltage Vo,
2Vm
(i) Vo = cos α (for RL cond).
π
2 2 × 230
= cos 30° = 179.303 V
π
Vo
(ii) Average output current, I o =
R
179.303
= = 17.93 A
10
(iii) The average value of thyristor current is,
π I 17.93
ITavg = I 0 . = 0 = = 8.965 A
2π 2 2
Rms value of thyristor current is,
1 I
ITrms = I 02π × = 0 = 12.68 A
2π 2

(iv) Load power = V0 I 0 = 179.3 × 17.93

= 3, 214.85w = 3.214 Kw

Input power = VsIs cos φ .

EEE_Semester-V_Ch06.indd 93 7/7/2012 5:07:47 PM

 6.94 B.E./B.Tech. Question Papers

π
I s = I 02 . = I 0 = 17.93 A
π
Assume loss less, Vs I s cos φ = V0 I 0
V0 I 0
∴ Power factor = cos φ =
Vs I s
3.214 × 103
cos φ = = 0.779 lag
230 × 17.93
With source inductance, Ls =1.5 mH
(i) Average output voltage,
2Vm ω Ls
V0 = cos α − I
π π 0
ω = 2π f
Ls = 1.5 mH
I 0 = 17.93 A

2 × 2 × 230 2π × 50 × 1.5 × 10 −3
V0 = cos 30° − × 17.93
π π
= 176.614 V
Vm
(ii) I0 = [cos α − cos(α + μ )].
ω Ls
2 × 230
17.93 = [cos 30° − cos(30° + μ )]
2π × 50 × 1.5 × 10 −3

⇒ μ = 2.855° → overlap angle

V0 I 0 176.614 × 17.93
(iii) Power factor = =
Vs I s 230 × 17.93
= 0.7679 lag

13. (a) There are four basic topologies of switching regulators:

• Buck regulators
• Boost regulators
• Buck-boost regulators
• Cúk Regulators

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 Power Electronics (Nov/Dec 2009) 6.95

Cúk Regulators
The circuit arrangement of the Cúk regulator [10] using a power
bipolar junction transistor (BJT) is shown in figure (a). Similar to
the buck-boost regulator, the Cúk regulator provides an output volt-
age that is less than or greater than the input voltage, but the output
voltage polarity is opposite to that of the input voltage. It is named
after its inventor [1]. When the input voltage is turned ON and tran-
sistor Q1 is switched OFF, diode Dm is forward biased and capacitor
C1 is charged through L1, Dm, and the input supply Vs.

IL1 , Is + eL – C1 Ic1 IL2

+ L1 + + – + L2 – +
Vc1

Vs vT Vdm Dm Vc2 C2 Load v0 , Va

G
Ic 2
Q1
I0 = I a
− – – + –

(a) Circuit Diagram

Vc1 IL2
+ –
+
L1 IL1 Ic1 C1 + L2
C2
Vs vdm Load

Ic2 I0
− –

Mode 1

Ic1 C1 L2

+ L1 IL1 + – IL2
vT + C2
Vs Load
vdm
I1 Ic 2
− – I0 = Ia

Mode 2
(b) Equivalent Circuits

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 6.96 B.E./B.Tech. Question Papers

vT
Vs – L 1 dls
dt

0 t
kT T
– Vdm
Vcl
t1 t2
0 t
kT T
iL1
IL12
Is DI 1
IL11
0 t
iL2 kT T
IL22
IL2 DI 2
IL21
0 t
kT T
ic2

0 t
T
vc2

– Va DVc 2

0 t
ic1

0 t
kT T
i0

Ia

0 t
(c) Waveforms
Cúk regulator

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 Power Electronics (Nov/Dec 2009) 6.97

The circuit operation can be divided into two modes. Mode 1 begins
when transistor Q1 is turned ON at t = 0. The current through induc-
tor L1 rises. At the same time, the voltage of capacitor C1 reverse
biases diode Dm and turns it OFF. The capacitor C1 discharges its
energy to the circuit formed by C1, C2, the load, and L2. Mode 2
begins when transistor Q1 is turned OFF at t = t1. The capacitor C1 is
charged from the input supply and the energy stored in the inductor
L2 is transferred to the load. The diode Dm and transistor Q1 provide
a synchronous switching action. The capacitor C1 is the medium for
transferring energy from the source to the load. The equivalent cir-
cuits for the modes are shown in figure (b) and the waveforms for
steady-state voltage and currents are shown in figure (c) for a con-
tinuous load current.
Assuming that the current of inductor L1 rises linearly from IL11 to
IL12 in time t1,
I L12 − I L11 ΔI
Vs = L1 = L1 1 (1)
t1 t1
or
Δ I1 L1
t1 = (2)
Vs
and due to the charged capacitor C1, the current of inductor L1 falls
linearly from IL12 to IL11 in time t2,
Δ I1
Vs − Vc1 = − L1 (3)
t2
or
−Δ I1 L1
t2 = (4)
Vs − Vc1
where Vc1 is the average voltage of capacitor C1, and Δ I1 = I L12 − I L11 .
From Eqs. (1) and (3).
Vst1 −(Vs − Vc1 )t2
Δ I1 = =
L1 L1
Substituting t1 = kT and t2 = (1 − k)T, the average voltage of capacitor
C1 is
V
Vc1 = s (5)
1− k

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 6.98 B.E./B.Tech. Question Papers

Assuming that the current of filter inductor L2 rises linearly from IL21
to IL22 in time t1,
I L 22 − I L 21 ΔI
Vc1 + Va = L2 = L2 2 (6)
t1 t1
or
Δ I 2 L2
t1 = (7)
Vc1 + Va
and the current of inductor L2 falls linearly from IL22 to IL21 in time t2,
Δ I2
Va = − L2 (8)
t2
or
Δ I 2 L2
t2 = (9)
Va
where Δ I 2 = I L 22 − I L 21 . From eqs. (6) and (8),

Δ I2 =
(V c1
+ Va ) t1
=−
Vat2
L2 L2

Substituting t1 = kT and t2 = (1 − k )T , the average voltage of capaci-

tor C1 is
Va
Vc1 = (10)
k
Equating Eq. (5) to Eq. (10), we can find the average output voltage
as
kV
Va = − s (11)
1− k
which gives
Va
k= (12)
Va − Vs
Vs
1− k =
Vs − Va (13)

Assuming a lossless circuit, Vs I s = −Va I a = Vs I a k /(1 − k ) and the

average input current,

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 Power Electronics (Nov/Dec 2009) 6.99

kI a
Is = (14)
1− k
The switching period T can be found from Eqs. (2) and (4):
1 ΔI L Δ I1 L1 −Δ I1 LV
T= = t1 + t2 = 1 1 − = 1 c1
(15)
f Vs Vs − Vc1 Vs (Vs − Vc1 )
which gives the peak-to-peak ripple current of inductor L1 as
−Vs (Vs − Vc1 )
Δ I1 = (16)
fLV
1 c1

or
Vs k
Δ I1 = (17)
f L1
The switching period T can also be found from Eqs. (7) and (9):
1 Δ I 2 L2 Δ I 2 L2 −Δ I 2 L2Vc1
T= = t1 + t2 = − = (18)
f Vc1 + Va Va Va (Vc1 + Va )
and this gives the peak-to-peak ripple current of inductor L2 as
−Va (Vc1 + Va )
Δ I2 = (19)
f L2Vc1
or
Va (1 − k ) kVs
Δ I2 = = (20)
f L2 f L2

When transistor Q1 is OFF, the energy transfer capacitor C1 is

charged by the input current for time t = t2. The average charging
current for C1 is Ic1 = Is and the peak-to-peak ripple voltage of the
capacitor C1 is
1 t2 1 t2 It
C1 ∫0 c1
ΔVc1 = I dt = ∫ I s dt = s 2 (21)
C1 0 C1
Equation (13) gives t2 = Vs /[(Vs − Va ) f ] and Eq. (21) becomes

I sVs
ΔVc1 = (22)
(V s
− Va ) fC1
or
I s (1 − k )
ΔVc1 = (23)
fC1

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 6.100 B.E./B.Tech. Question Papers

If we assume that the load current ripple Δ io is negligible, Δ iL 2 = Δ ic 2 .

The average charging current of C2, which flows for time T/2, is
I c 2 = Δ I 2 /4 and the peak-to-peak ripple voltage of capacitor C2 is

1 T2 1 T 2 Δ I2 Δ I2
ΔVc 2 =
C2 ∫0
I c 2 dt =
C2 ∫0 4
dt =
8 fC2
(24)

or
Va (1 − k ) kVs
ΔVc 2 = − 2
= (25)
8C2 L2 f 8C2 L2 f 2
Condition for continuous inductor current and capacitor
voltage. If I L1 is the average current of inductor L1, the inductor rip-
ple current Δ I1 = 2 I L1 . Using Eqs. (14) and (17), we get
2
kVs 2kI a ⎛ k ⎞ Vs
= 2 I L1 = 2 I s = = 2⎜ ⎟
f L1 1− k ⎝1− k ⎠ R

which gives the critical value of the inductor Lc1 as

(1 − k )2 R
Lc1 = L1 = (26)
2kf
If I L 2 is the average current of inductor L2, the inductor ripple cur-
rent Δ I1 = 2 I L 2 . Using Eqs. (11) and (20), we get

kVs 2V 2kVs
= 2I L2 = 2I a = a =
f L2 R (1 − k ) R

which gives the critical value of the inductor Lc2 as

(1 − k ) R
Lc 2 = L2 = (27)
2f
If Vc1 is the average capacitor voltage, the capacitor ripple voltage
ΔVc1 = 2Va . Using ΔVc1 = 2Va into Eq. (23), we get

I s (1 − k )
= 2Va = 2 I a R
fC1

which, after substituting for Is, gives the critical value of the capaci-
tor Cc1 as
k
Cc1 = C1 = (28)
2 fR

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 Power Electronics (Nov/Dec 2009) 6.101

If Vc2 is the average capacitor voltage, the capacitor ripple voltage

ΔVc 2 = 2Va . Using Eq. (11) and (25), we get
kVs 2kVs
= 2Va =
8C2 L2 f 2
1− k

which, after substituting for L2 from Eq. (27), gives the critical value
of the capacitor Cc2 as
1
Cc 2 = C2 = (29)
8f R
The Cúk regulator is based on the capacitor energy transfer. As a
result, the input current is continuous. The circuit has low switching
losses and has high efficiency. When transistor Q1 is turned ON, it
has to carry the currents of inductors L1 and L2. As a result a high
peak current flows through transistor Q1.
(b) Zero-Voltage-Switching Resonant Converters
The switches of a ZVS resonant converter turn ON and OFF at zero
voltage [9]. The resonant circuit is shown in figure (a). The capaci-
tor C is connected in parallel with the switch S1 to achieve ZVS. The
internal switch capacitance Cj is added with the capacitor C, and it
affects the resonant frequency only, thereby contributing no power
dissipation in the switch. If the switch is implemented with a transis-
tor Q1 and an antiparallel diode D1, as shown in figure (b), the voltage
across C is clamped by D1, and the switch is operated in a half-wave
configuration. If the diode D1 is connected in series with Q1, as shown
in figure (c), the voltage across C can oscillate freely, and the switch
is operated in a full-wave configuration. A ZVS resonant converter is
shown in figure (a). A ZVS resonant converter is the dual of the ZCS
resonant converter in figure (a). Equations for the M-type ZCS reso-
nant converter can be applied if iL is replaced by Vc and vice versa, L
by C and vice versa and Vs by I0 and vice versa. The circuit operation
can be divided into five modes whose equivalent circuits are shown
in figure (b). We shall redefine the time origin, t = 0, at the beginning
of each mode.
Mode 1. This mode is valid for 0 ≤ t ≤ t1. Both switch S1 and diode
Dm are OFF. Capacitor C charges at a constant rate of load current I0
. The capacitor voltage V0, which rises, is given by
I0
Vc = t (1)
C
This mode ends at time t = t1 when Vc(t = t1) = Vs . That is, t1 = VsC/I0.

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 6.102 B.E./B.Tech. Question Papers

S1
L

(a) ZVS Circuit

D1 L

Q1
S1

(b) Half-wave

L
Q1
S1 D1

(c) Full-wave

Mode 2. This mode is valid for 0 ≤ t ≤ t2. The switch S1 is still OFF,
but diode Dm turns ON. The capacitor voltage Vc is given by
Vc = Vm sin ω 0 t + Vs (2)

Where Vm = I 0 L / C . The peak switch voltage, which occurs at

t = (π / 2) LC , is
L
VT ( pk ) = VC ( pk ) = I 0 + VS (3)
C
The inductor current iL is given by
i L = I 0 cos ω 0 t (4)
This mode ends at t = t2 when Vc( t = t2 ) = Vs, and iL( t = t2 ) = − Io.
Therefore, t2 = π LC

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 Power Electronics (Nov/Dec 2009) 6.103

S1
iL L io = Io Le

+ +
D1
Vs Dm Cf Vo R
− −
C
+ −
Vc

(a) ZVS Circuit

iL C L iL C L iL + V−s L
+ i0 +V − I0 C I0
s
Vs i0 Vs I0 Vs i0
− Dm I0 i0
iL iL
Mode 1 Mode 2 Mode 3
iL L iL L
iL3 i0
Vs i0 Vs

Mode 4 Mode 5
(b) Equivalent Circuits

iL
Vs + Vm
Vm
Is

0
iL T t
I0

0
T t
– I0

t1 t2 t3 t4 t5

(c) Waveforms

Mode 3. This mode is valid for 0 ≤ t ≤ t3. The capacitor voltage that
falls from Vs to zero is given by
Vc = Vs − Vm sin ω 0 t (5)

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 6.104 B.E./B.Tech. Question Papers

The inductor current iL is given by

iL = − I 0 cos ω 0 t (6)
This mode ends at t = t3 when Vc( t = t3 ) = 0, and iL( t = t3) = IL3. Thus,
t3 = LC sin −1 x

Where x = Vs Vm = (Vs I 0 ) C / L .

Mode 4. This mode is valid for 0 ≤ t ≤ t4. Switch S1 is turned ON,

and diode Dm remains ON. The inductor current, which rises linearly
from IL3 to I0, is given by
Vs
iL = I L.3 + t (7)
L
This mode ends at time t = t4 when iL( t = t4) = Io. Thus, t4 = (I0 – IL3)
(L/Vs). Note that IL3 is a negative value.
Mode 5. This mode is valid for 0 ≤ t ≤ t5. Switch S1 is ON, but Dm is
OFF. The load current I0 flows through the switch. This mode ends
at time t = t5, when switch S1 is turned OFF again and the cycle is
repeated. That is, t5 = T – ( t1 + t2 + t3 + t4).
The waveforms for iL and Vc are shown in figure (c). Equation (3)
shows that the peak switch voltage VT(pk) is dependant on the load
current I0. Therefore, a wide variation in the load current results in a
wide variation of the switch voltage. For this reason, the ZVS con-
verters are used only for constant-load applications. The switch must
be turned ON only at zero voltage. Otherwise, the energy stored in C
can be dissipated in the switch. To avoid this situation, the antiparel-
lel diode D1 must conduct before turning ON the switch.

14. (a) Refer answer 14(a) from Nov/Dec 2011 Question paper.

(b) Refer answer 14(b)(ii) from April/May 2010 Question paper.

15. (a) Static UPS

Static UPS uses power electronic switches. Types of static UPS are
• Short-break UPS
• No-break UPS.

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 Power Electronics (Nov/Dec 2009) 6.105

Short Break Ups [Or] Offline Ups [Or] Non-Redundant Ups

Normally ON
Static Switch

LOAD
Main DC AC
AC Rectifier Inverter Filter
Supply Static Switch
Battery
Normally OFF

• It is used in case where short interruption in supply can be

tolerated.
• Under normal condition normally ON contacts are closed and
normally OFF contacts are open.
• During normal condition the mains supply is given to the load
through the normally ON switch.
• At the same time AC is converted to DC by rectifier.
• This DC voltage is used to charge the battery.
• In case of power failure, the normally OFF contact is closed, and
the DC supply from battery is converted to AC by inverter, and
then filtered and supplied to load.
But here we have a momentary interruption of 4 to 5 ms and so is
called a short break UPS.
Further Refer answer 15(a)(i) from April/May 2010 Question paper.

(b) Refer answer 15(b)(i) from April/May 2010 Question paper.

EEE_Semester-V_Ch06.indd 105 7/7/2012 5:07:50 PM

 B.E./B.Tech. DEGREE EXAMINATION,
APRIL/MAY 2009
Fifth Semester
Electrical and Electronics Engineering
POWER ELECTRONICS
Time: Three hours Maximum: 100 marks
Answer ALL questions
PART A (10 × 2 = 20 marks)
1. How SCR differs from TRIAC?

2. What is snubber circuit?

3. Define distortion factor.

4. What is the inversion mode of rectifiers?

5. What is CUK converter?

6. What is meant by SMPS?

7. List the advantages of multiple PWM over single PWM technique.

8. What is current source inverter?

9. What is the need for UPFC?

10. What is off-line UPS?

PART B (5 × 16 = 80 marks)
11. (a) (i) Compare the performance characteristics of MOSFET and BJT.
(ii) Briefly discuss the V-I characteristics of SCR.
Or
(b) Explain the turn ON and turn OFF characteristics of IGBT with neat
waveforms.

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 Power Electronics (April/May 2009) 6.107

12. (a) Explain the operation of three phase full converter. Also derive the
expression for its average output voltage.
Or
(b) A single phase full wave AC voltage controller has an input voltage
of 230 V, 50 HZ and it is feeding a resistive load of 10 ohms. If firing
angle of thyristors is 110 degree, find the output RMS voltage, input
power factor and average current of thyristor.

13. (a) (i) A DC chopper has an input voltage of 200 V and a load of 20 ohm
resistance. When chopper is ON, its voltage drop is 1.5 V and the
chopping frequency is 10 KHz. If the duty cycle is 80 %, find
(1) Average output voltage
(2) RMS output voltage
(3) Chopper ON time.
(ii) Prove that the output voltage of step down chopper is V0 = DVs.
Or
(b) Explain the operation of boost and buck-boost converter with neat
circuit diagram and waveforms.

14. (a) Discuss the functioning of three phase voltage source inverter in 120
degree operation mode.
Or
(b) Explain the different methods of voltage control adopted in an
inverter with suitable waveforms.

15. (a) Discuss the operation of on-line and off-line UPS with block
diagram.
Or
(b) Write short note on the following:
(i) HVDC transmission.
(ii) Static VAR compensator.

EEE_Semester-V_Ch06.indd 107 7/7/2012 5:07:50 PM

 Solutions
PART A

1. SCR TRIAC
It is an unidirectional device as it TRIAC is a bidirectional device,
conducts from anode to cathode and conducts in both the directions.
not from cathode to anode

2. A snubber circuit consists of a series combination of resistance Rs and

capacitance Cs in parallel with the thyristor. It is used for dv/dt protection
of thyristor.

3. Distortion factor (DF) is a measure of effectiveness in reducing unwanted

harmonics without having to specify the value of second order load filter.
DF indicates the amount of harmonic distortion that remains in a particu-
lar waveform after the harmonic of that waveform have been subjected to
a second order attenuation.
1/ 2
1 ⎡ ∞ ⎛ VON ⎞ 2 ⎤
DF = ⎢∑ ⎜ 2 ⎟ ⎥
V01 ⎢⎣ n = 2,3.. ⎝ n ⎠ ⎥⎦

4. When the single phase full converter with RL load is operated with a
firing angle, a > 90°, the average DC output voltage is negative. In other
words, power is now being delivered from the DC side of the converter
to the AC side. This mode is called as inversion mode and the converter
is operating as a line commutated inverter.

5. A CUK converter provides an output voltage which can be either higher

or lower than the input voltage. CUK converter is a combination of buck
and boost converter. Here, the output voltage polarity is opposite to that
of supply voltage.

6. SMPS (Switched Mode Power Supply) is based on the chopper prin-

ciple, the output DC voltage is controlled by varying the duty cycle of
the chopper by PWM (or) FM techniques.

7. • The harmonic content can be reduced by using several pulses in

each half cycle of output voltage.

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 Power Electronics (April/May 2009) 6.109

• Distortion factor is reduced.

• Power factor is improved.

8. Refer answer 7 from Nov/Dec 2011 Question paper.

9. UPFC (Unified Power Flow Controller) is meant for both series and
shunt compensation. It controls real power as well as reactive power flow
of the system to which it is connected.

10. The offline UPS is also called short break UPS or non-redundant UPS.
In case of power failure, the static switch (Normally OFF Switch) dis-
connect the mains from the load and connect the load to the UPS output.
The battery then supplies power to the load via the inverter. The inverter
comes into the circuit only when power fails.

PART B
11. (a) (i) Demerits of MOSFET
• On state loss is high
• Used for low power appreciations.
• Static charge problems.
Applications
• High frequency and low power inverters.
• High frequency SMPS
• High frequency inverters and chapters.
• Low power AC DC drives.
Differences between BJT and MOSFET
BJT MOSFET
• It is a bipolar device. • It is a unipolar device.
• It is controlled by base. • It is controlled by gate.
• It is a current controlled • It is a voltage controlled
device. device.
• Negative tempt coeff of • Positive tempt coeff of
resistance. resistance.
• Paralleling of BJT is • Paralleling MOSFET is
difficult. simple.
• ON state loss is low. • ON state loss is high.
• Switching loss is high. • Switching loss is less.

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 6.110 B.E./B.Tech. Question Papers

• Drive circuit is complex. • Drive circuit is simple.

• Switching frequency is • Switching frequency is high.
less.
• Used in high power • Used in low power
applications. applications.
• High voltage and current • Less voltage and current
rating. rating.

(ii) SCR Operation

• Operation of SCR is explained by the help of four modes.
– Forward blocking mode.
– Forward conducting mode.
– Reverse blocking mode.
– Reverse conducting mode.
Forward Blocking Mode (with gate open)
• A positive voltage is applied between anode (A) and cathode
(K) of SCR.
• Anode is positive w.r.t cathode.
• Junction J1, and J3 are forward biased and Junction J2 is
reverse biased.
A

P
J1
N +
J2
G P –
J3
N

• ∴ A depletion layer is formed in J2. ∴ No current flows

from anode to athode.
• But a small leakage current flows due to the existence of
leakage carriers in the junction J2.
Forward Conducting Mode
• As the applied voltage is increased, the junction J2 will
undergo avalanche breakdown and loose its blocking ability.

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 Power Electronics (April/May 2009) 6.111

• This voltage at which the junction breaks down is called as

VBO (Forward break over Vge, (or) Threshold voltage).
• SCR acts like a closed switch; and the current flowing from
anode to cathode increases.
• At VAK > VBO, SCR turns ON.
• After SCR is ON, the voltage acrons the device reduces.
Reverse Blocking Mode
• If anode is made –ve w.r.t. cathode, the junctions J1, and J3
are reverse biased and J2 is forward biased.
• There is no flow of current, expect for the leakage current
through the device due to the leakage carriers.
Reverse Conducting Mode
• As the reverse voltage is further increased, at the reverse
breakdown voltage (VBR) avalanche breakdown occurs at
junction J1 and J3.
• SCR acts as a closed switch in reverse direction.
• A larger current gives rise to more losses in SCR, dissipating
in form of heat, thereby damaging the SCR.
• So the value of VAK should not be increased beyond VBR in
the reversed biased condition.

Forward Conducting
Iak

Latching Current
Holding Current

VBR

VBO VAK
Forward Blocking
Reverse
Reverse Blocking
Conducting

V-I Characteristics

Latching Current (IL)

It is the minimum anode current required to switch (latch) the
SCR from OFF state to ON state.
Holding Current (IH)
It is the minimum anode current required to hold the SCR in
ON state

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 6.112 B.E./B.Tech. Question Papers

(or)
It is the minimum current below which the device will move
from ON state to OFF state.
Peak Reverse Voltage
It is the maximum voltage that can be applied across the SCR in
reverse biased condition.
Peak Inverse Voltage
It is the maximum voltage which the device can safely with-
stand in its OFF state.
ON State Voltage
The voltage which appears across the device during its ON state
is known as its ON state voltage.
dv
Rate of Rise of Voltage
dt
The rate at which the voltage across the device rises without
triggering the device is known as its rate of rise of voltage.
Current Rating
The current carrying capacity of the device is known as its cur-
rent rating.

IGBI – Insulated Gate Bipolar Transistor

Symbol and Equivalent Circuit

Pnp
C

Npn

G G
Rn

Rn – Resistance offered by n-channel

E

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 Power Electronics (April/May 2009) 6.113

Switching Characeteristics
• IGBT is designed such that the turn ON and turn OFF times
of the device can be controlled by the gate-emitter impedance
• The device is turned ON by applying a positive voltage
between the gate and emitter terminals.
Turn ON Process
The turn ON time is defined as the time between the instant of
the rise of collector current ‘IC’ from ICEO to IC
ICEO – Leakage current
IC − final (Maximum collector current)
Turn ON time is composed of delay time (tdn) and rise time (tr)
i.e., tON = t dn + t r

Until VGE reaches VGET (threshold level), no collector current

flows significantly.
Switching Characteristics of IGBT
VGE

VGET
VGET

O
VGB
VCE, Ic VCE
Ic
0.9 VCE
0.9 Ic

0.2 Ic
0.1 Ic 0.1 Ic

VCES

tdf
ICEO tdn tr tf 2
tf 1

tON
tOFF
VGET – Threshold Gate – Emitter Voltage
VCES – VCE at Saturation (Conduction Drop)
ICEO – Leakage Current tON = t dn + t r
tOFF = t df + t f 1 + t f 2

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 6.114 B.E./B.Tech. Question Papers

Delay Time tdn

The turn ON delay time is the time for VCE to fall from VCE to
0.9 VCE. Also tdn can be defined as the time for the IC. Also tdn can
be defined as the time for the Ic to rise from its initial leakage
current ICE0 to 0.1 Ic
• During this period the gate emitter voltage increases from
zero to gate-emitter threshold voltage (VGET)
Rise Time tr
The rise time ‘tr’ is the time during which collector emitter volt-
age (VCE) falls from 0.9 VCE to 0.1 VCE and the collector current
rises from 0.1 Ic to its final value Ic.
After tON, the collector emitter voltage falls to small value called
conduction drop = VCES − VCE at saturation.
Turn OFF process
The turn OFF delay is caused by the discharge time constant of
the effective gate-to-either capacitor and RGE.
The turn OFF time consists of three intervals
• Turn OFF delay time (tdf)
• Initial fall time (tf1)
• Final fall time (tf2)

tOFF = t df + t f 1 + t f 2

Delay Time tdf

During delay time, the gate voltage falls from VGE to threshold
voltage VGET. As VGE falls to VGET, the collector current falls from
IC to 0.9IC.
At the end of tdf, the VCE begins to rise.
Initial Fall Time tf1
The first/Initial fall time ‘tf1’ is defined as the time during which
collector current falls from 90 to 20% of its initial value.
Also VCE rises from VCES to 0.1 VCE.
Final Fall Time tf2
During tf2, IC falls from 20 % to 10 % of its initial value (IC) (or)
VCE rises from 0.1 VCE to final value of VCE.

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 Power Electronics (April/May 2009) 6.115

IGBT’s are available with current ratings upto 400 A and 1200 V,
and the switching frequently up to 20 KHz.
IGBT’s are finding increased applications in medium-power
application such as DC and AC motor drives, power supplies,
solid state relays and contractors.
Upper limits of commercially available IGBT’s ratings are
increasing as high as 6500 V and 2400 A.

12. (a) Refer answer 12(a) from Nov/Dec 2011 Question paper.
(b) Given data
R = 10 Ω
Vs = 230 V
α = 110°
RMS Output Voltage

1⎛ sin 2α ⎞
Vo = Vs ⎜⎝ π − α + ⎟
π 2 ⎠
1/ 2
⎡1 ⎛ ⎛ 110 × π ⎞ sin 2(110) ⎞ ⎤
= 230 ⎢ ⎜ π − ⎜ +
⎣ π ⎝ ⎝ 180 ⎟⎠ 2 ⎟⎠ ⎥
⎦
Vo rms = 123.1 V

Input Power Factor

Vorms 123.1
I P P .F = = = 0.535(lag )
Vs 230

Average Current of Thyristors

Vdc
ITAvg =
R
Vm 2 × 230
Vdc = (cos α + 1) = (cos110 + 1)
2π 2π
= 34.062 V
34.062
ITavg = = 3.406 A
10

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 6.116 B.E./B.Tech. Question Papers

13. (a) (i) Given

a = 0.8
Edc = 200 V
RL = 15 Ω
Ed, Voltage drop = 1.5 V
fc = 10 KHz
RMS Output Voltage
Eo rms = α ( Edc − Ed ) = 0.8 (200 − 1.5) = 177.54 V

Average Output Voltage

Eo = a (Edc − Ed) = 0.8 (200 − 1.5) = 158.8 V
Chopper On Time
TON
=∞
T
fc = 10 KHz
1
Ts = = 0.1 m sec
10 × 103
a × T = TON
∴ On time, TON = 0.8 × 0.1 m sec.
= 0.08 m sec (or) 80 µsec

(ii) Step Down Chopper with RL Load

• It is called a step down chopper because the output voltage
Vo is < Vs
io

CH R
+
Vs Df Vo
–
L

• Vs = dc supply voltage
• CH = chopper
• DF = free wheeling diode

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 Power Electronics (April/May 2009) 6.117

• io = load curt
• Vo = load Vge.
• The chopper CH is turned ON for an interval TON and is
turned OFF for an interval TOFF.

During turn ON period TON

CH io

R
+
Vs Vo
–
L

• Chopper CH is turned ON.

• Source is connected to load.
• Vo = Vs
• io = increases slowly due to L of the load.
• CH is ON till time period TON.
During turn OFF period TOFF
• Chopper CH is turned OFF
• Load is disconnected from source.
• The freewheeling diode is forward biased due to the load
inductance voltage.
• Output voltage is zero; Vo = 0
• io = slowly and reaches zero.
• io flows through the free wheeling diode.

R
+ io
Vs FD Vo
–
L

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 6.118 B.E./B.Tech. Question Papers

Vs

Vo

TON TOFF
T

io

Continuos Load Current (High L)

Vs

Vo

TON TOFF

io

Discontinuos Load Current (Low L)

1 TON V TON Vs Vs
Vo ( avg ) =
T ∫ 0
Vs .dt = s
T ∫
0
dt =
T
[t ]T0ON =
T
[TON − 0]

TON
Vo ( avg ) = Vs .
T
TON
ut = α = duty cycle.
T
∴ Vo ( avg ) = α = Vs
TON = ON time
TOFF = OFF time
T = TON + TOFF = chopping period
1
f = = chopping frequency.
T

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 Power Electronics (April/May 2009) 6.119

(b) Boost Regulation

In a boost regulator [8, 9] the output voltage is greater than
the input voltage—hence the name “boost.” A boost regulator
using a power MOSFET is shown in the figure given below. The
circuit operation can be divided into two modes. Mode 1 begins
when transistor M1 is switched ON at t = 0. The input current,
which rises, flows through inductor L and transistor Q1. Mode 2
begins when transistor M1 is switched OFF at t = t1. The current
that was flowing through the transistor would now flow through
L, C, load, and diode Dm. The inductor current falls until transis-
tor M1 is turned ON again in the next cycle. The energy stored
in inductor L is transferred to the load. The equivalent circuits
for the modes of operation are shown in the figure given below.
The waveforms for voltages and currents are shown in the fig-
ure given below for continuous load current, assuming that the
current rises or falls linearly.

is , Is + eL – i , I i1 Dm
L L iL
+ L + + +
ic , Ic io , Is

Vs vD Vc C
M1 Load vo , Va

G
− – – –

(a) Circuit Diagram

+ iL , is ic + io , Ia
L

Vs C vc Load

− –
Mode 1

i s = IL Dm
+ L i1 + ic io = Ia

Vs C
Vc Load

− −

Mode 2
(b) Equivalent Circuits

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 6.120 B.E./B.Tech. Question Papers

Vu
Vs

0 t
is,iL kT T
I2
DI
I1
0 t
i1 kT T
I2

I1
0 t
ic kT T
I2 – Ia

0 t
Ia kT T

Vc

Va DVc

0 t
kT T
i0
Ia
0 t

(c) Waveforms

Boost regulator with continuous iL

Assuming that the inductor current rises linearly from I1 to I2
in time t1,
I −I ΔI
Vs = L 2 1 = L (1)
t1 t1
or
Δ IL
t1 = (2)
Vs

and the inductor current falls linearly from I2 to I1 in time t2,

ΔI
Vs − Va = − L (3)
t2

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 Power Electronics (April/May 2009) 6.121

or
Δ IL
t2 = (4)
Va − Vs

where Δ I = I 2 − I1 is the peak-to-peak ripple current of induc-

tor L. From Eqs. (1) and (3),

Vst1 (Va − Vs ) t2
ΔI = =
L L

Substituting t1 = kT and t2 = (1 − k )T yields the average output

voltage,

T V
Va = Vs = s (5)
t2 1 − k
which gives
Vs
(1 − k ) = (6)
Va

Substituting k = t1 /T = t2 f into Eq. (6) yields

Va − Vs
t1 = (7)
Va f

Assuming a lossless circuit, Vs I s = Va I a = Vs I a /(1 − k ) and the

average input current is
I
Is = a (8)
1− k
The switching period T can be found from

1 Δ IL Δ IL Δ ILVa
T= = t1 + t2 = + = (9)
f Vs Va − Vs Vs (Va − Vs )

and this gives the peak-to-peak ripple current:

Vs (Va − Vs )
ΔI = (10)
f LVa
or

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 6.122 B.E./B.Tech. Question Papers

Vs k
ΔI = (11)
fL

When the transistor is ON, the capacitor supplies the load current
for t = t1 . The average capacitor current during time t1 is I c = I a
and the peak-to-peak ripple voltage of the capacitor is
1 t1 1 t1 I t
ΔVc = Vc − Vc (t = 0) =
C ∫0
I c dt = ∫ I a = a 1
C 0 C
(12)

Substituting t1 = (Va − Vs ) (Va f ) from Eq. (7) gives

I a (Va − Vs )
ΔVc = (13)
Va fC
or
I ak
ΔVc = (14)
fC

Condition for continuous inductor current and capacitor

voltage. If IL is the average inductor current, the inductor ripple
current Δ I = 2 I L .
Using Eqs. (5) and (11), we get
kVs 2Vs
= 2I L = 2I a =
fL (1 − k ) R

which gives the critical value of the inductor Lc as

k (1 − k ) R
Lc = L = (15)
2f
If Vc is the average capacitor voltage, the capacitor ripple voltage
ΔVc = 2Va . Using Eq. (14), we get

I ak
= 2Va = 2 I a R
Cf
which gives the critical value of the capacitor Cc as
k
Cc = C = (16)
2fR

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 Power Electronics (April/May 2009) 6.123

A boost regulator can step up the output voltage without a trans-

former. Due to a single transistor, it has a high efficiency. The
input current is continuous. However, a high-peak current has
to flow through the power transistor. The output voltage is very
sensitive to changes in duty cycle k and it might be difficult
to stabilize the regulator. The average output current is less
than the average inductor current by a factor of (1 − k), and a
much higher rms current would flow through the filter capaci-
tor, resulting in the use of a larger filter capacitor and a larger
inductor than those of a buck regulator.
Buck Boost: Refer answer 13(a) from Nov/Dec 2011 Question paper.

14. (a) 120° conduction mode VSI

T1 T3 T5

Vs

T4 T6 T2

B
A N C

• It has 6 SCRs
• T1, T3, T5 → positive group SCRs
• T4, T6, T2 → negative group SCRs
• A, B, C be the 3 phases.
• T1T4 is connected in phase A
• T3T6 is connected in phase B
• T5T2 is connected in phase C
• In 120° conduction mode every SCR conducts for an inter-
nal of 120°.

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 6.124 B.E./B.Tech. Question Papers

• Every SCR is triggered with a delay of 60°

120
= 2 . ∴ during every instant 2 SCRs conduct.
∴
60
• SCRs are triggered in sequence T1, T2, T3, T4, T5, T6 with a
delay of 60° between each.
60° 60° 60° 60° 60°
T1 → T2 → T3 → T4 → T5 → T6

T1 is ON at wt = 0 ; T2 is ON at wt = 60°; T3 is ON at wt = 120°
T4 is ON at wt = 180°; T5 is ON wt = 240°; T6 is ON at wt = 300°.
After being turned ON each SCR will conduct for 120° and will
be OFF for another 240°.
• The triggered sequence is as follows.
61, 12, 23, 34, 45, 56, 61, 12…….
• During every instant one SCR from positive group and one
SCR from negative group conduct.
• Now for the sequence 61, SCR, T6, T1 conduct
T1 is positive group SCR in phase A
T6 is negative group SCR in phase B
Now the equivalent circuit is:
A
VAN = VBN = V/2
Vs R
T1 (∴ Voltage is equally divided)
Vs N
VCN = 0 ∴ SCR in C
R
B Phase is not ON
T6
B
R
A N
R

From this if SCR in positive group conducts the voltage is = + V/2

V
and if SCR of negative group conduct the voltage is =
2
VAB = VAN – VBN VAN, VBN, VCN = Phase voltage (quasi square
wave)
VBC = VBN – VCN VAB, VBC, VCA = Line voltage (stepped wave)
VCA = VCN – VAN

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 Power Electronics (April/May 2009) 6.125

T1
60 120 180 240 300 360 420 480 540 600 660 720
T2

T3

T4

T5

T6

61 12 23 34 45 56 61 12 23 34 45 56

V/2

V an

– V/2

V bn

V cn

V/2

– V/2

–V

V bc

V ca

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 6.126 B.E./B.Tech. Question Papers

Conducting VAN VBN VCN VAB VBC VCA

SCRs
61 V/2 −V/2 0 V −V/2 −V/2
12 V/2 0 −V/2 V/2 V/2 −V
23 0 V/2 −V/2 −V/2 V −V/2
34 −V/2 V/2 0 −V V/2 V/2
45 −V/2 0 V/2 −V/2 −V/2 V
56 0 −V/2 V/2 V/2 −V V/2

61 12 23
A A B

V N V N V N

B C C

34 45 56
B C C

V N V N V N

A A B

(b) Refer answer 14(a)(i) from April/May 2010 Question paper.

Multiple PWM

Triangular Wave (Carrier Signal)

+
Comparator Vo
–

Square Wave (Control Signal)

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 Power Electronics (April/May 2009) 6.127

Let
VT = Triangular wave
VC = Square wave
Vo = Output
• A triangular (VT) signal is compared with a square wave
form (VC).
• Output of the comparator is high when VT is > VC. ∴ an o/p
pulse is produced.
• Output of comparator is low when VT < VC.
∴ no o/p pulse.
∴ The output of comparator has a train of pulses.
∴ Multiple PWM has multiple pulses per cycle.

VT
VT

VC
VC

Vo

15. (a) Uninterruptible Power Supplies (UPS)

• UPS provide a continuous supply in case of power failure
from the mains.

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 6.128 B.E./B.Tech. Question Papers

Rotating Type UPS

To Load

DC Alter- Diesel
2

3f
AC Motor nator Engine
1

Rectifier

Battery

•Earliest type of UPS.

•It consists of an alternator driven by a DC motor.
•Alternator is also coupled to a diesel engine.
•Output of alternator is used to give an uninterrupted power
supply to the load.
• 3f AC supply is rectified to DC by rectifier.
• This dc is used to charge a battery and also run a DC motor
coupled to another.
• When the main supply fails, the diesel engine drives the
alternator. But the diesel engine takes some time (say 15 sec-
onds) to start.
• Till then the battery gives DC supply to motor and hence
runs the alternator, after which the diesel engine runs the
alternator. It gives a continuous supply even in case of a
power outage.
Further Refer answer 15(a) from Nov/Dec 2009 Question paper.

(b) (i) Refer answer 15(b)(ii) from April/May 2010 Question paper.
(ii) Static VAR compensator
The use of either TCR or TSC would allow only capacitive or
inductive compensation. However, in most of the applications, it is
desirable to have the possibilities of both capacitive and inductive
compensation. A static VAR compensator (SVC) consists of TCRs
in parallel with one or more TSCs [4, 7]. The general arrangement of
an SVC is shown in the figure. The reactive elements of the compen-
sator are connected to the transmission line through a transformer
to prevent the elements having to withstand full system voltage.

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 Power Electronics (April/May 2009) 6.129

Transmission Line
V Vr

Step-Down Potential
C
Transformer Transformer

Vref
Thyristor Controller
Modules
Auxiliary
Input

C C L L Parameter Setting

Capacitor Banks Reactor Banks

General arrangement of static VAR compensator

A control system determines the exact gating instants of reactors

according to a predetermined strategy. The strategy usually aims to
maintain the transmission line voltage at a fixed level. For this rea-
son, the control system has a system voltage input taken through
a potential transformer (PT); additionally, other input parameters
(or variables) to the control system may exist. The control system
ensures that the compensator voltage remains more or less constant
by adjusting the conduction angle [5, 6].

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