Product Information

STR-X6700 Series Off-Line

Quasi-Resonant Switching Regulators

Introduction
The STR-X6700 series integrates a quasi-resonant control
IC and a MOSFET with avalanche guarantee. In normal
operation, the device provides high efficiency and low EMI
noise with bottom-skip quasi-resonant operation during
light output loads. Low power consumption is also achieved
by Auto-standby mode (not available in the STR-X6729, LF1901 LF1902
STR-X6759N, or STR-X6768N) or manual standby mode
(external trigger).
LF1905
The device is supplied in a seven-pin fully-molded TO-3P-
style package, which is suitable for downsizing and stan- Figure 1. STR-X6700 series packages are fully molded TO-3P
dardizing of an SMPS by reducing external component package types: LF1901 (STR-X6737 and STR-X6769), LF1902
count and simplifying circuit design. (STR-X6729 and STR-X6768N), and LF1905 (STR-X6757 and
STR-X6759N).
Features and benefits include the following:
▪ Auto standby mode (burst oscillation) or manual standby
mode (UVLO intermittent oscillation) in the standby
Table 1. Product Line-up
mode.
MOSFET RDS(on) VAC
▪ In addition to the standard quasi-resonant operation, a Type # VDSS (Max) Input
POUTa
bottom-skip mode is available for increased efficiency (V) (Ω) (V)
(W)
from light to medium load. STR-X6729b 450 0.189 120 460
▪ Soft-start operation at start-up.
STR-X6737 500 0.36 120 280
▪ Reduced switching noise (compared to conventional
Wide 165
PWM hard-switching solution) with a step-drive STR-X6757 0.62
function. 230 320
650
▪ Built-in avalanche-energy-guaranteed power MOSFET Wide 250
STR-X6759Nb 0.385
(to simplify surge-absorption circuit; no VDSS derating is 230 460
required). Wide 150
▪ Overcurrent protection (OCP), overvoltage protection STR-X6768Nb 1.00
230 220
(OVP), overload protection (OLP), and maximum 800
Wide 210
On-time control circuits are incorporated; OVP and OLP STR-X6769 0.66
go into a latched mode. 230 310
aThe listed output power represents thermal ratings, and the peak
The product lineup for the STR-X6700 series provides the output power, POUT , is obtained by 120% to 140% of the thermal
options shown in table 1. rating value. In case of low output voltage and narrow on-duty
cycle, the POUT (W) becomes lower than the above.
Contents bAuto-standby mode not included.
Introduction 1
Pin functional descriptions 2
Operation description 6
Transformer parameters 10
General considerations 11
Design considerations 13 All performance characteristics given are typical values for
Package dimensions, TO-3P 14 circuit or system baseline design only and are at the nominal
Worldwide Contacts 19 operating voltage and an ambient temperature of 25°C, un-
less otherwise stated.

28103.3013
Pin functional descriptions starts its operation by the start-up circuit, and supply current is
increased. Once the VCC pin voltage drops down to lower than
the Operation-Stop voltage 9.7 V, the UVLO circuit operates to
VCC Supply (pin 4)
stop the control circuit, and the IC returns to its initial state.
Start-up circuit The start-up circuit detects the VCC pin volt-
age, and makes the control IC start and stop operation. The power Bias/drive winding After the control circuit starts its operation,
supply of the control IC (VCC pin input) employs a circuit as the power supply is operated by rectifying and smoothing the
shown in figure 2. At start-up, C3 is charged through a start-up voltage of the bias winding. Figure 4 shows the start-up voltage
resistor R2. The R2 value needs to be set for more than the hold waveform of the VCC pin. The bias winding voltage does not
current of the latch circuit (140 μA max.) and to operate at the immediately increase up to the set voltage after the control circuit
minimum AC input. starts its operation. That is why the VCC pin voltage starts drop-
ping. The Operation-Stop voltage is set as low as 10.6 V (max),
If the value of R2 is too high, the C3 charge current will be
the bias winding voltage reaches a stabilized voltage before it
reduced. Consequently, it will take longer to reach the Operation-
drops to the Operation-Stop voltage, and the control circuit conti-
Start voltage. The VCC pin voltage falls immediately after
ues its operation. The bias winding voltage, in normal power sup-
the control circuit starts its operation. The voltage drop can be
ply operation, is set for the voltage across C3 to be higher than
reduced by increasing C3 capacitance. However, too large a
C3 capacitance will cause an improperly long time to reach the the Operation-Stop voltage, VCC(OFF) , 10.6 V (max.) and lower
Operation-Start voltage after the initial power turn on. than the OVP-operation voltage, VCC(OVP) , 25.5 V (min.).

In general, SMPS performs its start-up operation properly

with a value of C3 between 4.7 and 47 μF, and R2 between
47 and 150 kΩ for 120 V narrow or universal AC input, and I CC
82 to 330 kΩ for 200 V narrow AC input.
As shown in figure 3, the circuit current is limited to 100 μA max
(VCC = 15 V, and resistor R2 with appropriate high resistance
value for the circuit) until the control circuit starts its operation.
Once the VCC pin voltage reaches 18.2 V, the control circuit

100 μ A
( MAX) VCC
9. 7 V 15V 18. 2 V
( TYP) ( TYP)

Figure 3. VCC pin current versus voltage

Operation Start
VCC
R2
P 18.2 V
(TYP) Bias Winding Voltage

1
D D2 10.6V
(MAX)
VCC
4 Start-up
STR-X6700 D failure
C3
GND time
3
AC on

Figure 2. External start-up circuit. Figure 4. VCC pin voltage after start-up, capacitor C3 installed

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In an actual power supply circuit, the VCC pin voltage might and the voltage is in proportion to the output voltage; thus, the
be changed by the value of secondary output current as shown OVP circuit also operates in the case of overvoltage output of the
in figure 5. C3 is fully charged by the surge voltage generated secondary side, for example, when the voltage detection circuit
instantly after the MOSFET turns off. In order to prevent this, it is open. The secondary output voltage for the OVP operation
is effective to add a resistor (R7) of several ohms to tens of ohms (VO(OVP)) is obtained from the following formula:
in series with the diode as shown in figure 5. The optimum value VO(normal operation)
VO(OVP) = 27.7 V (1)
of the additional resistor is determined in accordance with the VCC(normal operation)
specifications of the transformer because the VCC pin voltage is Latch circuit OVP and OLP fault modes latch the oscillation
determined by construction of the transformer. output low, which stops the power supply circuit operation. The
Furthermore, the variation ratio of the VCC pin voltage becomes holding current of the latch circuit is 140 μA (max., TA = 25°C)
worse due to a loose coupling between primary and secondary when the VCC pin voltage is at the Operation-Stop voltage minus
windings of the transformer (the coupling between the bias wind- 0.3 V.
ing and the stabilized output winding for the constant voltage In order to prevent malfunction caused by, for instance, noise,
control). Therefore, when designing a transformer, the winding a delay time is programmed into a timer circuit, which prevents
position of the bias winding needs to be studied carefully. latch circuit operation until the OVP or OLP circuit keeps operat-
ing for more than a programmed time. During the latched mode,
Overvoltage protection (OVP) circuit If VCC, referenc-
the internal regulator circuit keeps running, the circuit current is
ing the GND pin, exceeds 27.7 V, the OVP circuit of the control
maintained at a high level, and the VCC pin voltage drops.
IC starts its operation and the fault mode is latched by the latch
circuit, the control IC stopping its oscillation. Generally, the VCC When the VCC pin voltage drops down to the Operation-Stop
pin voltage is supplied from the bias winding of the transformer, voltage (9.7 V (typ.) ), the voltage starts rising again as the circuit
current becomes less than 140 μA. When the VCC pin voltage
reaches the Operation-Start voltage (18.2 V (typ.) ), the circuit
current increases, and the voltage drops again. Consequently,
the VCC pin voltage is maintained between 9.7 V and 18.2 V in
VCC the latched mode. Figure 7 shows the voltage waveform in the
latched mode. The latched mode is released by decreasing the
ut R7 VCC pin voltage to below 7.2 V, or in general, by shutting off the
Witho AC input.

With R7 SS/OLP (Pin 5)

Through the SS/OLP pin, soft-start and overload protection is
enabled by connecting a 0.47 to 3.3 μF capacitor to the pin.

IO

Figure 5. VCC versus IO (secondary load)

D2 R7
VCC
4
Bias

STR-X6700 D
C3
GND
3

Figure 6. VCC versus IO (secondary load)

Figure 7. VCC during latch mode

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Soft-start operation at start-up of power supply At the Gradual increase of drain current suppresses audible noise from
power supply start-up, an external capacitor is charged up to the the transformer.
soft-start operation threshold voltage, VSSOLP(SS) , by soft-start
operation charging current, ISSOLP(SS) , sourced from the SS/OLP Overload protection (OLP) Figure 9 shows output character-
pin. Soft-start is activated at power supply start-up by means of istics of the secondary side when the OCP circuit is activated due
the SS/OLP pin voltage change from the initial 0 V level, up to to an overload at the secondary side output. When the output volt-
1.2 V. Timing is shown in figure 8 and the following table: age drops in an overload mode, the bias winding voltage of the
primary side drops proportionally, and the VCC pin voltage drops
Soft-start Timing (Charging current: 550 μA)*
below the Operation-Stop voltage to deactivate the IC. Then the
CSS
0.47 1 2.2 3.3 4.7 circuit current decreases, and the VCC pin voltage rises again by
(μF)
way of the start-up resistor (R2) charge current to reactivate the
Time
1.0 2.2 4.8 7.2 10.3 IC intermittently at the Operation-Start voltage. However, where
(ms)
*A large CSS value also results in a longer time from OLP the transformer has multiple output windings and coupling is
operation to latched mode. not good enough, the intermittent operation might not be sensed
By comparing the oscillation waveforms of the SS/OLP pin and even if the output voltage drops in an overload mode, because
that of the internal control, soft-start widening of the on-width is the primary bias winding voltage would not drop. Although the
activated. In addition, soft-start is operated every time in the burst intermittent operation is not realized, protection might still be by
oscillation of Auto-standby mode and manual standby mode. means of the OLP activation.

Figure 8. Soft-start operation Figure 9. Current-mode control

Figure 10. Timing at overload

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In the overload mode, where drain current is controlled by OCP current value therefore does not exactly match the value calcu-
operation, the secondary-side output voltage drops. Accordingly, lated in the equation above, and the actual load conditions should
the error-amplifier and photocoupler on the secondary side are be carefully considered. Also, make sure that OCP operation at
cut off. The STR-X6700 series regards the signal absence with power supply start-up does NOT place the IC in a latched mode.
continuous OCP operation as an overload status, and the SS/OLP Note: During this period, if VCC goes below the UVLO thresh-
pin voltage starts rising by ISSOLP(OLP) as shown in figure 10 and old voltage, the IC does not go into a latch mode, but goes into
in the following table: intermittent operation. Where the CSS voltage rises to 4.9 V and
VCC does not go below the UVLO threshold voltage, the IC goes
OLP timing (0 to 4.9 V, charging current: 11 μA)
into a latched mode.
CSS (μF) 0.47 1.0 2.2 3.3 4.7
Time (ms) 209 445 980 1470 2094
Operation at power supply turn off At power supply turn
off, voltage on capacitor CSS, which is externally connected to
NOTE: A large CSS value also results in a longer soft-start time.
the SS/OLP pin, is discharged by way of an internal RESET cir-
After the SS/OLP pin voltage keeps rising to the OLP-Operation cuit as shown in figure 11. The RESET circuit does not operate in
Threshold Voltage (VSSOLP(OLP) = 4.9 V), the oscillation stops, normal operation while the internal regulator circuit operates.
and the IC goes into a latched mode. Deactivating the OLP circuit To deactivate the OLP circuit
The time from OLP activation to a latched mode should be while soft-start is active, connect either a 47 kΩ resistor or a
obtained from the following formula, assuming ISSOLP(OLP) is Zener diode to the SS/OLP pin (figure 12). By doing this, OLP
from a constant-current circuit: operation is deactivated at start-up or during an overload status.
CSS × ∆V
t= (2)
ISSOLP(OLP) FB (Pin 6)
where ∆V is the capacitor charging voltage of approximately 4.9 V. The FB pin is used in either a normal mode (constant-voltage-
However, the ISSOLP(OLP) is dependent on the SS/OLP pin voltage, control circuit operation) or in a standby mode. Refer to Standby
and ISSOLP(OLP) drops as the SS/OLP pin voltage rises. The actual Operation section for controlling in the standby mode.
Constant voltage control circuit The STR-X6700 series
adopts the current-mode control circuit, which ensures stability
SS/OLP
with a heavy load. The peak value of the MOSFET drain current
5 (at on-time) is changed by comparing the FB pin voltage with the
internal VOCPM. Off-time becomes quasi-resonant operation syn-
V CSS chronized to the reset signal from a transformer. Where no reset
signal is input from the transformer, it becomes fixed oscillation
frequency (approximately 22 kHz) set by the internal oscillator

Figure 11. Reset circuit at power turn off

IDS
GND
SS/OLP SS/OLP
5 5
VOCPM
47 kΩ
VOCPD(LIM) VFB
GND
Overload Normal Load Light Load

Figure 12. OLP deactivation circuit alternative configurations Figure 13. Constant-voltage control at fixed oscillation frequency (quasi-
resonant signal not available)

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circuit. The timing chart is shown in figure 13, and the internal rent sense resistor, ROCP, is connected externally along with R4
circuit diagram of the constant voltage control circuit is shown in and C5. R4 and C5 are to prevent malfunction caused by surges
figure 14. when the MOSFET switches on. When the MOSFET switches
on, switching current occurs, and a voltage is developed across
The constant-voltage-control circuit feeds a control signal (FB
ROCP . After that, the MOSFET turns off when the OCP/BD pin
current) from an error amplifier into pin 6 by way of the isolating
voltage reaches VOCPBD(LIM).
photocoupler. The input FB current is transformed into feedback
voltage VFB by the internal resistor (SW1 is turned on during The threshold voltage of the OCP/BD pin, VOCPBD(LIM), is
normal status). The voltage waveform (VOCPM) from the drain –0.94 V. The OCP circuit adopts negative-detection, which cre-
current waveform is input to the inverting input terminal of the ates the detecting voltage, VOCPM , in the control part by dividing
FB comparator. the voltage (V1 + VROCP) with RB1, RB2, and R4. Because RB1
Figure 13 shows the FB current is decreased to nearly zero in an and RB2 are resistors incorporated in the IC, taking the variance
overload, when the drain current is restricted to below the current of RB1 and RB2 (defined as IOCPBD in the specifications) into
value set by the overcurrent protection circuit. In the period from consideration, the value of R4 should be small, between 100 Ω
normal load to light load in figure 13, the drain current decreases and 330 Ω. Select capacitor C5 (100 to 680 pF target value) for
because the FB current increases and VFB rises. When VFB good thermal behavior type. A high capacitance value results in
exceeds the FB pin threshold voltage (VFB(OFF) , 1.45 V) at light slow response time, ending up with an increase in peak drain cur-
load, the oscillation stops so as not to raise the secondary-side rent during a transient and at start-up.
output voltage.
Operation description
OCP/BD (Pin 7)
The OCP/BD pin functions in overcurrent detection, bottom-skip, Quasi-resonant operation Quasi-resonant operation matches
and quasi-resonant-operation control. Bottom-skip and quasi-res- the timing of the MOSFET turn on to the bottom point of the
onant features are described in the Operation Description section. voltage resonant waveform, namely, ½ cycle of the resonant
frequency after the transformer discharges energy.
Negative-detection type OCP circuit The OCP circuit of
the STR-X6700 series is a pulse-by-pulse type, which detects As shown in figure 16, the voltage resonant capacitor, C4, is
the peak value of the MOSFET drain current for each pulse and connected between the drain and source, and the delay circuit,
inverts the oscillator output. As shown in figure 15, the overcur- C10, D3, D4, and R9 are connected between the bias winding and

IDS
D D
1 P
1 4 Control
V CC
D
STA RT 18V
BUR ST 11 V BURST FB LOGIC DRIVE
㧗 6
㧙 VFB
3
2
SW 1
S
OSC FB
㧗
㧙 3 Filter
Reg.V1 GND
㧙 RB1 VOCPM
ROCP

C5
㧙
VOCPM
㧗
OCP 㧗 RB2
2 S 3 GND 7
OCP/BD
OCP 7 V4
OCP/BD
R4
ROCP
V5

Figure 14. REG circuit functional block diagram Figure 15. OCP functional block diagram

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the OCP/BD pin. When the MOSFET turns off, a quasi-resonant PWM operation is also activated at power supply start-up or at
signal is generated from the flyback voltage in the bias winding, low bias winding voltage due to a winding short, which low-
and the BD comparator inside the IC operates, enabling quasi- ers oscillating frequency and reduces MOSFET stress. After the
resonant operation. Even after the energy of the transformer is quasi-resonant signal exceeds VOCPBD(TH2) at 0.8 V, the MOSFET
discharged by way of the delay circuit, the quasi-resonant signal remains off during VOCPBD(TH1) at 0.4 V and higher. A voltage dif-
imposed on the OCP/BD pin does not drop immediately. This is ference between VOCPBD(TH1) and VOCPBD(TH2) prevents malfunc-
because C10 is discharged by R4, and the voltage drops to the tion.
threshold voltage, VOCPBD(TH1), at 0.4 V after a certain period.
In setting R9 and R4, the quasi-resonant signal imposed on the
The delay time needs to be set by adjusting C10, monitoring the OCP/BD pin needs to be 5 V or less. In a normal condition, it
operating waveform, so that the MOSFET turns on when the VDS should be approximately 1.5 V. The value of R4 is 100 to 330 Ω
of the MOSFET hits the lowest point. and ROCP is small enough to be ruled out. The bias winding out-
put voltage is set at 18 V. To make the OCP/BD pin voltage 1.5 V
In addition to the quasi-resonant operation, the IC incorporates a
or higher, R9 value is to be 1 to 3.3 kΩ. However, R9 needs to be
bottom-skip mode in order to suppress the increase of oscillating
considered together with C10 capacitance relative to setting up
frequency during a light-to-medium load. It lengthens the off time
the delay time. R9 determines the time constant with C10 capaci-
in accordance with the load status. Change-over timing between
tance. Assuming the time constant is 2.2 μs, R4 is 220 Ω, R9 is
the quasi-resonant and bottom-skip modes is described below.
2.2 kΩ and C10 is 1000 pF, then proper selection should be done
When the quasi-resonant signal voltage imposed on the OCP/BD while looking at the quasi-resonant signal and VDS waveform in
pin is below VOCPBD(TH2) at 0.8 V, the IC goes into PWM opera- the actual application.
tion with a fixed oscillating frequency of 22 kHz.
Bottom-skip mode (shift from quasi-resonant opera-
tion) The basic bottom-skip mode is activated at light load by
judging secondary load status by means of the drain current value
(actually OCP/BD pin voltage). If the load status evaluates as
heavy load, the IC goes into quasi-resonant operation. Judging is
made by reading the OCP/BD pin voltage during the falling edge
P of the MOSFET gate voltage. Also, the count of falling edges
(OCP/BD pin voltage is less than VOCPBD(TH1)) of quasi-resonant
signal is counted to be utilized to turn the MOSFET on in accor-
dance with the load status described above.
D VCC D
1 4
• Quasi-resonant operation → bottom-skip mode
Quasi-resonance is operated under the absolute value of VOCP
C4 greater than VOCPBD(BS2) . When the load becomes lighter and
D3
Control the drain current drops to make VOCP less than VOCPBD(BS2) , the
operation is shifted to the bottom-skip mode, and the reference
voltage is automatically changed to VOCPBD(BS1) . Figure 17

㧟 㧟 7 R9 shows shift timing from quasi-resonant operation to bottom-skip
S GND OCP
/BD
mode.
C10
ROCP
• Bottom-skip mode → quasi-resonant operation
R5
C5 Bottom-skip is operated under the absolute condition of VOCP
less than VOCPBD(BS2) . When the load becomes heavier and the
R4 D4 drain current increases to make VOCP greater than VOCPBD(BS2) ,
operation is shifted to quasi-resonant operation mode, and the
Figure 16. Quasi-resonant and delay circuit

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 reference voltage is automatically changed to VOCPBD(BS2) . VOCP
is the OCP/BD pin voltage at the falling edge of the MOSFET
gate voltage.
Quasi-resonant Bottom-skip
As described above, the reference voltages for bottom-skip mode, 0V

VOCPBD(BS1) and VOCPBD(BS2) , has hysteresis to make a stable

operation shift as shown in figure 18.
VOCPBD(BS2)
Standby modes The STR-X6700 series devices incorporate
Hysteresis
standby modes to reduce power consumption. Two modes are
VOCPBD(BS1)
available. One is Auto-Standby mode (except the STR-X6729,
STR-X6759N, and STR-X6768N) and the other is manual
VOCPBD(LIM)
standby mode (external trigger).
Auto-Standby mode The Auto-Standby mode is started by inter-
nally sensing the drain current pulse. Because the minimum drain
pulse width is limited to the minimum on-time pulse width of
tON(MIN) , at light load the power supply can not lower its output Figure 18. Operation mode shift
power any more, and the output voltage starts increasing. When
the FB pin voltage exceeds the the FB terminal threshold voltage,
VFB(OFF) , the IC stops working until VFB drops and then the power
supply starts working again.

Quasi- Resonant BottomSkipQuasi- Resonant

VDS

Detection
IDS level

V OC PB D(TH2 )
OCP/BD V OC PB D(TH1 )
V OCP
V OC PB D(BS2) Hysteresis
V OC PB D(BS1)
V OC PB D(LIM)

MOSFET Gate
(Power IC‫ޓ‬internal)

Bottom detect signal

(Power IC internal)

State signal
(Power IC internal)

Figure 17. Quasi-resonant to bottom-skip operation timing

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Manual standby mode (external trigger) The manual standby NOTE: During transitions between the manual standby and
mode is remotely controlled by a clamp on the secondary side to normal operation, because the STR-X6700 series is not pumping
reduce the output voltage. Then, the transformer winding voltage energy, make sure that normal output load is not applied, oth-
drops and it reduces the bias winding voltage and the VCC pin erwise output voltage will drop significantly and will affect the
(pin 4) voltage decreases. When the VCC pin voltage reaches the entire system operation.
Operation-Stop voltage (9.7 V), the IC stops its operation, and
current consumption of the IC becomes the Standby Non-Oper-
ation Circuit Current, ICC(S) . The IC will not restart its operation
until the VCC pin voltage rises to the Standby Operation Start
Voltage, VCC(S) , by charging the start-up capacitor (C3) through Control IC
the start-up resistor (R2). By repeating this cycle, the IC main- DRIVE
REG 1
㧝
tains a UVLO intermittent oscillation mode. This is illustrated in D
RG2
figure 19. Delay

In order to eliminate the transformer audible noise in the UVLO RG1

intermittent oscillation mode, the voltage difference between the 2
㧟
RG3
Standby Operation Start Voltage, VCC(S) , and the Operation Stop S
Voltage, VCC(OFF) , is designed to be small. By doing this, the 3
operating frequency is increased without increasing the losses in GND
the startup resistor, and the IC is in a mode where switching cur-
rent is reduced to as low a level as possible.
Figure 20. Step drive circuit

Secondary
Output Voltage

Feedback Stand-by
V FB(S)
detection level
Start Voltage
at stand-by
Start VCC(S)
V CC(ON)
VCC Voltage
Stop V CC(OFF)
Voltage

Power MOSFET
Waveform

Normal Operation Standby Operation Normal Operation

Figure 19. Quasi-resonant to bottom-skip operation timing

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Gate step-drive circuit The STR-X6700 series incorporates rent (IDP), corrected duty cycle (Derr), delay time (td), and others
a step-drive circuit (figure 20) for driving the MOSFET, which can be obtained:
reduces noise when the MOSFET turns on. The drive current,
td = π × (LP × C4 )1/2 (4)
when the MOSFET turns on, is at first limited only by RG1,
and the gate voltage is increased gradually, and then rapidly in Derr = D × (1 – [fOSC × td ] ) (5)
approximately 0.9 μs via (RG1 / RG2) . Drive voltage then uses IIN = PO / ( η2 × VIN ) (6)
the constant-voltage drive circuit, maintained at VDRM = 7.5 V,
which is not affected by VCC. The MOSFET gate charge is rap- Idp = 2 × IIN / Derr (7)
1/2
idly discharged through RG3 when the MOSFET turns off. NP = (LP / AL) (8)
Maximum on-time control function The MOSFET on-time NS = NP (VO + Vf ) / Ef (9)
is limited during transients such as at low input voltage and at where:
turn on and turn off of AC input. This is illustrated in figure 21. IIN = average DC input current,
The maximum on-time is set at about 70% (approximately 32 μs) Idp = peak switching current,
of the oscillation cycle (1/fosc = 45 μs). In designing a power C4 = voltage resonance capacitance,
supply, the MOSFET on-time at maximum load and at minimum η2 = power supply efficiency (0.85-0.9 in case of CRT TV),
input voltage should be considered. LP = primary inductance
NP = primary turns
NS = secondary turns, and
Transformer parameters
Vf = forward voltage of the secondary rectifier.
Basically, the same type of transformer is recommended as that
for a conventional quasi-resonant circuit. Examples are shown
in figure 22. The primary inductance, Lp, is determined by the Winding
following: D
B+
P2 S1 S2
(VIN × D)2
LP =

Barrier

Barrier
( [2×PO×fOSC / H] 1/2 (3) P2
+VIN× ×fOSC×D×C14/2 ) 2 P1 LoB S3
where: S3 S1

PO = maximum output power, P1

fOSC = minimum oscillating frequency, D
Audio
D = On duty cycle at minimum VIN(AC) (Bias) Bobbin
S2
= Ef /(VIN +Ef ), given Ef = flyback voltage, Core
η = transformer conversion efficiency (0.9 in the case of
CRT TV , and 0.75 to 0.85 in the case of low output (A)
voltage), and
VIN = rectified and smoothed DC input voltage at minimum Winding
VIN(AC) .
D
Turn-on delay results in duty cycle change in a quasi-resonant
P2 S3 S3
operation, therefore, duty cycle correction is necessary. From the
Barrier

Barrier

following formulas, the number of turns, the peak switching cur- P2

P1 S2
S2
I P1
DS
V S1
DS D
(Bias) S1 Bobbin

Core
Maximum On-time
(B)

Figure 21. Maximum on-time Figure 22. Example of recommended transformers: (A) CRT TV
transformer, (B) low output-voltage transformer.

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In addition, in the design of the transformer, using 130% of the ▫ Wire diameter is determined based on actual current and
estimated peak switching current is recommended to ensure that should be less than 4 A / mm2.
the transformer is not saturated, based on the plot of N × I-limit Single and/or low-voltage output concerns:
(AT) versus AL-value (nH / N2). • Wind so that wires are parallel and with good coupling.
Instead of performing the calculations above, software that pro- • Sandwich winding is recommended.
vides a complete flyback transformer design tool is available.
General considerations
CRT TV application concerns:
• Rather than winding with a single thick wire, a thin and
bifilar or trifilar winding across the entire width of bobbin is Universal AC input correction in OCP
recommended.
With a universal AC input application, as described in the
• For windings where NP and +B are a large number of turns,
Overload Protection (OLP) section, the load conditions for OCP
divisional sandwich winding is recommended.
activation vary according to input voltage level, 110 V or 230 V.
• For an output where a tight regulation is required, winding
with good coupling with S1 (+B) is recommended. Figure 23 illustrates a solution.
• For the +B winding, better coupling by use of litz wire is In the loop surrounded by the dashed line, the negative voltage of
required. In case the litz wire does not fit into a the bobbin the bias winding, which is in proportion to the input voltage level
winding width, reduce the wire size, and use 2 to 3 of them in when the MOSFET switches on, works for the input correction
strands. during OLP.
• For improved thermal design:
▫ Leakage flux of wires close to the core center becomes large. The Zener diode is set to be on with a 230 VAC input, but not to
Eddy current can be reduced by the use of litz wire. be activated with a 110 VAC input. When the bias winding output
▫ In case the entire winding does not fit into the available voltage is 18 V, the resistor, Zener, and diode within the dashed
winding thickness, reduce the size of wires from outer side. line are recommended.

Input
Smoothing P
Capacitor
Start-up P
Resistor Snubber Circuit

Bias
CR D
Voltage
Resonant D VCC
Capacitor STR-X6700
S
Feedback Circuit

GND
OCP SS/
/BD OLP FB 200 V
Bottom-Detection

Fast
Recovery
Delay Circuit

Diode

Bottom-Detection
Current- OCP Delay Circuit
Sense Sense
Resistor Filter

10 to 22 kΩ 16 V
Loop for OCP Matching to Input Voltage

Figure 23. Reference circuit for general application considerations

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OCP on the FB pin After the output voltage is shifted over to a lower level, the IC
goes into a manual standby mode on the primary side. In this
As shown in the feedback circuit portion of figure 23, a Zener mode, sufficient power is not obtained, resulting in audible noises
diode is connected in series with the photocoupler. This is a coun- from the transformer, and deep ripple output voltage is gener-
termeasure against an FB-pin voltage rise over 9 V in the manual ated, a sharp drop of output voltage, and unsustainable regulation,
standby mode. The absolute maximum FB-pin voltage is 9 V, and although a larger output smoothing capacitor reduces this issue.
a Zener diode voltage of 5.6 to 6.2 V is recommended.
Load in an actual manual standby mode ranges between tens of
Output regulation and transformer noise during milliwatts and 0.2 W.
standby and automatic modes
In regard to the audible noise from the transformer, contact a
Figure 24 presents a simplified circuit of the secondary output transformer manufacturer as a precaution against possible varnish
and manual standby circuit by VO drop. dissolving and ferrite core attaching.

Output Smoothing
Capacitors Output

Ground

External Signal
for Standby
Figure 25. High frequency, high current loops

Manual Standby
Sanken Error Amplifier by VO drop
Type SExxx

Figure 24. Output circuit

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Design considerations because traces and paths of high voltage exist, component
layout and trace length should be carefully considered, as
required by safety standards.
Component placement considerations in SMPS circuits • Take into account the positive thermal coefficiency of the
As pattern layout and component position may cause malfunc- MOSFET RDS(on) when preparing the thermal design.
tions of the IC, EMI noises, or power losses, the following guide-
lines should be followed: Layout considerations
• Traces where high frequencies and high current levels flow In order to reduce or eliminate common impedance lines, the
should be kept thick and short to lower line impedance. GND pin (pin 3) and its peripheral components should be located
• The hatched area illustrated in figure 25, where high as close together as possible, as illustrated in figure 26. The trace
frequencies and high currents create a loop, should be kept as from the overcurrent sense resistor to the input smoothing capaci-
small as possible. tor should be kept as short and thick as possible.
• GND and earth ground lines should be kept as thick and short
as possible.
• In off-line SMPS (switch-mode power supply) circuitry,

VCC SS/
OLP
STR-X6700
FB D
OCP Bias
S GND /BD

Figure 26. High frequency, high current loops

Terminal List Table

Number Name Description Functions
1 D Drain MOSFET drain
2 S Source MOSFET source
3 GND Ground terminal Ground
4 VCC Power supply terminal Input of power supply for control circuit
5 SS/OLP Soft Start/Overload Protection terminal Input to set delay for Overload Protection and Soft Start operation
Input for Constant Voltage Control and Burst (intermittent) Mode
6 FB Feedback terminal
oscillation control signals
7 OCP/BD Overcurrent Protection/Bottom Detection Input for Overcurrent Detection and Bottom Detection signals

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 Package dimensions, TO-3P

Leadform 1901 (STR-X6737 and STR-X6769)

15.6 ±0.2
5.5±0.2
2 ±0.2
Gate Burr 6
3.45±0.2
5.5±0.2

Ø3.2 ±0.2
Branding
23 ±0.3

Area XXXXXXXX
XXXXXXXX
XXXXXXXX
3.3±0.5

3.35±0.1

3.3

3
7±0.5
12.5±0.5

+0.2
0.55 –0.1
REF
5.5

View A

2X 2.54±0.1 4X 1.27±0.1 4.5 ±0.7

Terminal dimension at lead tip Terminal dimension at lead tip
+0.2
1.33 –0.1 +0.2
5X 0.75 –0.1
+0.2 +0.2
2X 0.83 –0.1 5X 0.65 –0.1
2 4 6
+0.2
1.89 –0.1
1 3 5 7

Enlargement View A

0.7 0.7 0.7 0.7

Front View (Plan View) Side View

Gate burr: 0.3 mm (max.) Drawing for reference only

Terminal core material: Cu Branding codes (exact appearance at manufacturer discretion):
Terminal treatment: Ni plating and Pb-free solder dip 1st line, type: STR
Leadform: 1901 2nd line, subtype: X6737 or X6769
3rd line, lot: YM DD
Approximate weight: 6 g Where: Y is the last digit of the year of manufacture
M is the month (1 to 9, O, N, D)
Dimensions in millimeters DD is the 2-digit date

Leadframe plating Pb-free. Device composition

includes high-temperature solder (Pb >85%),
which is exempted from the RoHS directive.

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 Leadform 1902 (STR-X6729 and STR-X6768N)

15.6 ±0.2
5.5±0.2

2 ±0.2
Gate Burr 6
3.45±0.2
5.5±0.2

Ø3.2 ±0.2
Branding
23 ±0.3

Area XXXXXXXX
XXXXXXXX
XXXXXXXX
3.3±0.5

3.35±0.1

3.3
7.0±0.5

3
12.5±0.5

+0.2
0.55 –0.1
REF
5.5

View A

2X 2.54±0.1 4X 1.27±0.1 4.5 ±0.7 4.5 ±0.7

Terminal dimension at lead tip Terminal dimension at lead tip
+0.2
1.33 –0.1 +0.2
5X 0.75 –0.1
+0.2 +0.2
2X 0.83 –0.1 5X 0.65 –0.1
1 4 6
+0.2
1.89 –0.1
3 5 7

Enlargement View A

2
0.7 0.7 0.7 0.7
Front View (Plan View) Side View

Gate burr: 0.3 mm (max.) Drawing for reference only

Terminal core material: Cu Branding codes (exact appearance at manufacturer discretion):
Terminal treatment: Ni plating and Pb-free solder dip 1st line, type: STR
Leadform: 1902 2nd line, subtype: X6729 or X6768
3rd line, lot: YM DD
Approximate weight: 6 g Where: Y is the last digit of the year of manufacture
M is the month (1 to 9, O, N, D)
Dimensions in millimeters DD is the 2-digit date

Leadframe plating Pb-free. Device composition

includes high-temperature solder (Pb >85%),
which is exempted from the RoHS directive.

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 Leadform 1905 (STR-X6757 and STR-X6759N)

15.6 ±0.2
5.5±0.2
2 ±0.2
Gate Burr 6
3.45±0.2
5.5±0.2

Ø3.2 ±0.2
Branding
23 ±0.3

Area XXXXXXXX
XXXXXXXX
XXXXXXXX

3.35±0.1

3.3
6.7±0.5

3
12.5±0.5

+0.2
0.55 –0.1
REF
5.8

View A

2X 2.54±0.1 4X 1.27±0.1 4.3 ±0.5 3.6 ±0.5

Terminal dimension at lead tip Terminal dimension at lead tip
+0.2
1.33 –0.1 +0.2
5X 0.75 –0.1
+0.2 +0.2
2X 0.83 –0.1 5X 0.65 –0.1
2 3 5 7
+0.2
1.89 –0.1
1 4 6

Enlargement View A

0.5 0.5
Front View (Plan View)

Gate burr: 0.3 mm (max.) Drawing for reference only

Terminal core material: Cu Branding codes (exact appearance at manufacturer discretion):
Terminal treatment: Ni plating and Pb-free solder dip 1st line, type: STR
Leadform: 1905 2nd line, subtype: X6757 or X6759
3rd line, lot: YM DD
Approximate weight: 6 g Where: Y is the last digit of the year of manufacture
M is the month (1 to 9, O, N, D)
Dimensions in millimeters DD is the 2-digit date

Leadframe plating Pb-free. Device composition

includes high-temperature solder (Pb >85%),
which is exempted from the RoHS directive.

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 WARNING — These devices are designed to be operated at lethal voltages and energy levels. Circuit
designs that embody these components must conform with applicable safety requirements. Precau-
tions must be taken to prevent accidental contact with power-line potentials.

The use of an isolation transformer is recommended during circuit development and breadboarding.

Because reliability can be affected adversely by improper storage Heatsink Mounting Method
environments and handling methods, please observe the following
cautions. • Torque When Tightening Mounting Screws. Thermal resistance
Cautions for Storage increases when tightening torque is low, and radiation effects are
• Ensure that storage conditions comply with the standard decreased. When the torque is too high, the screw can strip, the
temperature (5°C to 35°C) and the standard relative humidity heatsink can be deformed, and distortion can arise in the product
(around 40 to 75%); avoid storage locations that experience frame. To avoid these problems, observe the recommended tightening
extreme changes in temperature or humidity. torques for this product package type, TO-3P: 0.588 to 0.785 N•m
• Avoid locations where dust or harmful gases are present and (6 to 8 kgf•cm).
avoid direct sunlight. • For effective heat transfer, the contact area between the product and
• Reinspect for rust on leads and solderability of products that have the heatsink should be free from burrs and metal fragments, and the
been stored for a long time. heatsink should be flat and large enough to contact over the entire
Cautions for Testing and Handling side of the product, including mounting flange and exposed thermal
When tests are carried out during inspection testing and other pad, and have a minimal mounting hole to prevent possible deflection
standard test periods, protect the products from power surges and cracking of the product case when fastened to the heatsink.
from the testing device, shorts between adjacent products, and Soldering
shorts to the heatsink. • When soldering the products, please be sure to minimize the working
Remarks About Using Silicone Grease with a Heatsink time, within the following limits:
• When silicone grease is used in mounting this product on a 260±5°C 10 s
heatsink, it shall be applied evenly and thinly. If more silicone
grease than required is applied, it may produce stress. 350±5°C 3 s
• Coat the back surface of the product and both surfaces of the • Soldering iron should be at a distance of at least 1.5 mm from the
insulating plate to improve heat transfer between the product and body of the products
the heatsink. Electrostatic Discharge
• Volatile-type silicone greases may permeate the product and • When handling the products, operator must be grounded. Grounded
produce cracks after long periods of time, resulting in reduced wrist straps worn should have at least 1 MΩ of resistance to ground to
heat radiation effect, and possibly shortening the lifetime of the prevent shock hazard.
product.
• Workbenches where the products are handled should be grounded
• Our recommended silicone greases for heat radiation purposes, and be provided with conductive table and floor mats.
which will not cause any adverse effect on the product life, are
indicated below: • When using measuring equipment such as a curve tracer, the
equipment should be grounded.
Type Suppliers
• When soldering the products, the head of soldering irons or the solder
G746 Shin-Etsu Chemical Co., Ltd. bath must be grounded in other to prevent leak voltages generated by
YG6260 Momentive Performance Materials them from being applied to the products.
• The products should always be stored and transported in our shipping
SC102 Dow Corning Toray Silicone Co., Ltd.
containers or conductive containers, or be wrapped in aluminum foil.

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 The products described herein are manufactured in Japan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit im-
provements in the performance, reliability, or manufacturability of its products. Therefore, the user is cautioned to verify that the information in this
publication is current before placing any order.
When using the products described herein, the applicability and suitability of such products for the intended purpose shall be reviewed at the users
responsibility.
Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products
at a certain rate is inevitable.
Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to device failure or malfunction.
Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus
(home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Their use in any application requiring radiation
hardness assurance (e.g., aerospace equipment) is not supported.
When considering the use of Sanken products in applications where higher reliability is required (transportation equipment and its control systems
or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written
confirmation of your specifications.
The use of Sanken products without the written consent of Sanken in applications where extremely high reliability is required (aerospace equip-
ment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited.
The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication are
given for reference only and Sanken and Allegro assume no responsibility for any infringement of industrial property rights, intellectual property
rights, or any other rights of Sanken or Allegro or any third party that may result from its use. The contents in this document must not be transcribed
or copied without Sanken’s or Allegro's written consent.

Copyright ©2003-2009 Allegro MicroSystems, Inc.

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 Worldwide Contacts

Asia-Pacific Singapore
China Sanken Electric Singapore Pte. Ltd.
Sanken Electric Hong Kong Co., Ltd. 150 Beach Road, #14-03 The Gateway West
Suite 1026, Ocean Centre, Canton Road Singapore 189720
Tsimshatsui, Kowloon, Hong Kong
Tel: 852-2735-5262, Fax: 852-2735-5494 Tel: 65-6291-4755, Fax: 65-6297-1744

Sanken Electric (Shanghai) Co., Ltd.

Room 3202, Maxdo Centre, Xingyi Road 8 Europe
Changning District, Shanghai, China Sanken Power Systems (UK) Limited
Tel: 86-21-5208-1177, Fax: 86-21-5208-1757
Pencoed Technology Park
Taiwan Sanken Electric Co., Ltd. Pencoed, Bridgend CF35 5HY, United Kingdom
Room 1801, 18th Floor, 88 Jung Shiau East Road
Sec. 2, Taipei 100, Taiwan R.O.C. Tel: 44-1656-869-100, Fax: 44-1656-869-162
Tel: 886-2-2356-8161, Fax: 886-2-2356-8261
Japan North America
Sanken Electric Co., Ltd. United States
Overseas Sales Headquarters
Metropolitan Plaza Building, 1-11-1 Nishi-Ikebukuro Allegro MicroSystems, Inc.
Toshima-ku, Tokyo 171-0021, Japan 115 Northeast Cutoff
Tel: 81-3-3986-6164, Fax: 81-3-3986-8637 Worcester, Massachusetts 01606, U.S.A.
Korea Tel: 1-508-853-5000, Fax: 1-508-853-7895
Sanken Electric Korea Co., Ltd. Allegro MicroSystems, Inc.
Mirae Asset Life Building, 6F
14 Hughes Street, Suite B105
168 Kongduk-dong, Mapo-ku
Seoul 121-705, Korea Irvine, California 92618, U.S.A.
Tel: 82-2-714-3700, Fax: 82-2-3272-2145 Tel: 1-949-460-2003, Fax: 1-949-460-7837

Allegro MicroSystems, Inc.

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Worcester, Massachusetts 01615-0036 U.S.A.
28103.3013
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