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11 - Behavioral Modeling

The document discusses behavioral modeling in Verilog HDL. It describes sequential and parallel blocks that allow grouping statements. Sequential blocks execute statements sequentially using begin and end. Parallel blocks execute statements concurrently using fork and join. It explains blocking and non-blocking procedural assignments, where blocking assignments complete before next statement and non-blocking allow concurrent execution. Blocking assignments model combinational logic in always blocks while non-blocking model sequential logic in clocked always blocks.

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Rashmi Singh
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59 views

11 - Behavioral Modeling

The document discusses behavioral modeling in Verilog HDL. It describes sequential and parallel blocks that allow grouping statements. Sequential blocks execute statements sequentially using begin and end. Parallel blocks execute statements concurrently using fork and join. It explains blocking and non-blocking procedural assignments, where blocking assignments complete before next statement and non-blocking allow concurrent execution. Blocking assignments model combinational logic in always blocks while non-blocking model sequential logic in clocked always blocks.

Uploaded by

Rashmi Singh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Behavioral Modeling

Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design


Behavioral Modeling
Learning Objectives:
o Describing the sequential block in procedural assignment
o Describing the parallel block in procedural assignment
o Explaining blocking assignments.
o Explaining nonblocking assignments.

Behavioral Modelling EC6203 Reconfigurable System Design


Block Statements
• A block is used to group two or more statements. (to act syntactically like a single statement).
• There are two kinds of blocks in Verilog HDL.
i. Sequential block (begin...end): Statements are executed sequentially in the given order.
ii. Parallel block (fork...join): Statements in this block execute concurrently.
• A block can be labeled optionally (If labeled, registers can be declared locally within the block.)
• Blocks can also be referenced; (a block can be disabled using a “disable” statement)
• A block label, in addition, provides a way to uniquely identify registers.
• All local registers are static, that is, their values remain valid throughout the entire simulation
run.
Begin: P1
x=1;
disable P1; // Second statement will not be executed.
x=2; //Final value of X=1.
end

Behavioral Modelling EC6203 Reconfigurable System Design


Sequential Block
• Statements in a sequential block execute in sequence. (begin…end)
• A delay value in each statement is relative to the simulation time of the execution of the
previous statement.
• Once a sequential block completes execution, execution continues with the next statement
following the sequential block.
Syntax:
begin
[ : block_id { declarations ) ]
procedural_statement (s)
end begin
Example:
begin: SEQ_BLK S = M & D;
reg [0:3] S; F = A ^ B;
S = M & D;
F = A ^ B;
end end

Behavioral Modelling EC6203 Reconfigurable System Design


Sequential Block
Example:

S
// Waveform generation:
begin
#2 S = 1;
#5 S = 0;
#3 S = 1;
#4 S = 0;
#2 S = 1;
#5 S = 0;
end
//Simulation starts at 10 time units.

Behavioral Modelling EC6203 Reconfigurable System Design


Parallel Block
• Statements in a parallel block execute concurrently (fork….join)
• Delay values specified a parallel block are relative to the time the block starts its execution.
• All statements within the parallel block must complete execution before control passes out of
the block.
Syntax:
fork
[ : block__id { declarations } ]
procedural_statement (s)
Fork
join

Example:
P = M1 | M2; F = A & B;
fork
P = M1 | M2;
F = A &B;
join
Join

Behavioral Modelling EC6203 Reconfigurable System Design


Initial Statement
Example:
// Waveform generation:
fork
#2 S = 1;
#7 S = 0;
#10 S = 1;
#14 S = 0 ;
#16 S = 1;
#21 S = 0;
Join
//Parallel block gets executed at 10 time units.
//All statements execute concurrently
//All delay values are relative to 10 time units.

Behavioral Modelling EC6203 Reconfigurable System Design


Mixed sequential and parallel blocks
always
begin: SEQ_A
#4 Dr = 5; //S1 --- 4 time units
fork: PAR_A // S2 ---12 time units
#6 C = 7; // P1
begin: SEQ_B // P2
E = B;// S6
#5 J = E;// S7
end
#2 D =3; // P3
#4 G =2; // P4
#8 P = 4; // P5
join
#8 Bx =1; // S3
#2 Z =52; // S4
#6 $stop; // S5
end

Behavioral Modelling EC6203 Reconfigurable System Design


Procedural Assignments
• A procedural assignment is an assignment within an initial statement or an always statement.
• It is used to assign to only a register data type.
• The right hand side of the assignment can be any expression.
Example:
reg [1:4] Enable , A, B;
#5 Enable = ~ (A & B);
• A procedural assignment executes sequentially with respect to other statements that appear around it.
Example:
always @ (A or B or C or D) Two types of procedural assignment:
begin: AOI
reg Temp1 , Temp2; i. Blocking. (for modeling combinational logic)
Temp1 = A & B; ii. Non-blocking. (for modeling sequential logic)
Temp2 = C & D;
Temp1 = Temp1 | Temp2;
Z= ~ Temp1;
end

Behavioral Modelling EC6203 Reconfigurable System Design


Blocking Procedural Assignment
• A procedural assignment in which the assignment operator is an “=” is a blocking procedural
assignment.
• The assignment statement is executed completely before the next statement is executed.
Example:
A = 52;

Example:
initial
begin
Clr = # 5 0 ;
begin
Clr = # 4 1 ;
A = 0;
Clr = #10 0;
A = 1;
end
end

Behavioral Modelling EC6203 Reconfigurable System Design


Non-blocking Procedural Assignment
• In a non-blocking procedural assignment, the assignment symbol “<=” is used.
• In a non-blocking procedural assignment, the assignment is allowed without blocking flow.

Example:
begin
Load <= 32;
RegA <= Load;
RegB <= Store;
end

initial
begin
Clr <= #5 1;
Clr <= #4 0;
Clr <= #10 0;
end

Behavioral Modelling EC6203 Reconfigurable System Design


Synthesis of Blocking Statements

***Use an always block with blocking assignments to create combinational logic.

Behavioral Modelling EC6203 Reconfigurable System Design


Synthesis of Nonblocking statements

***Use an clocked always block with Nonblocking assignments to create a sequential logic.

Behavioral Modelling EC6203 Reconfigurable System Design


References
Books:
A Verilog HDL Primer: by J Bhasker.
Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
Verilog Digital Design Synthesis: Samir Palnitkar.

website:
asic-world.com
www.xilinx.com

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