VLSI

LAB MANUAL
(15ECL77)

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 VLSI LAB MANUAL

I. VLSI DESIGN FLOW AND THE TOOLS USED IN CADENCE

II. PART A: Digital Simulation

PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND
CADENCE DIGITAL TOOL.
Experiment1: Inverter
Experiment2: Buffer
Experiment3: Transmission Gates(TG)
Experiment4: Logic Gates
AND,OR,NAND,NOR,XOR,XNOR
Experiment5: Flip Flops
JK,MS,SR,D,T
Experiment6: Synchronous Counter
Experiment7: Asynchronous Counter
Experiment8: Parallel Adder
Experiment 9: Serial Adder

III. PART B: Analog Design

PART B[1] : Schematic Simulation

PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION
Experiment 1(a): Inverter Schematic and test Cell View
Experiment 2(a): Common Source Amplifier Schematic and test Cell View
Experiment 3(a): Common Drain Amplifier Schematic and test Cell View
Experiment 4(a): Differential Amplifier Schematic and test Cell View
Experiment 5(a): Operational Amplifier Schematic and test Cell View
Experiment 6(a): R-2R DAC Schematic and test Cell View

PART B[1] : Layout Simulation

Layout Design Rules
PROCEDURE FOR CREATING THE LAYOUT AND SIMULATING
Experiment 1(b): Inverter Layout Design
Experiment 2(b): Common Source Amplifier Layout Design
Experiment 3(b): Common Drain Amplifier Layout Design
Experiment 4(b): Differential Amplifier Layout Design
Experiment 5(b): Operational Amplifier Layout Design
IV. VLSI Viva Questions
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VLSI Design Flow

PDK stands for Process Design Kit. A PDK contains the process technology and needed
information to do device-level design in the Cadence DFII environment.

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PART - A

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2) PART A: Digital Simulation

PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND
CADENCE DIGITAL TOOL.
Open Terminal Window and use the following commands

ü #csh
ü #source cshrc

ü #ls (ls can be skipped if you know which is the next directory to go)-this will list out
the directories like
Cadence_digital_labs
cadence_analog_labs … then

ü #cd Cadence_digital_labs/Workarea

ü Crate a directory for the experiment presently executed by using following command.
mkdir directory name Ex: mkdir Inverter

ü Create the module file/s(Verilog module ):

Vi modulename.v Ex: vi inverter.v
The file name can be changes with respect to the experiments.

ü A Text Editor window will open.To enter text in editor window PRESS “I” and then type
the program and exit to terminal window by save and exit command --- Press Esc :wq!
ü Repeat the steps for test bench by following above TWO steps with different file name.
Ex: vi test_inverter.v

ü Now to compile

Ø Compile the module file/s with message

option: ncvlog modulefilename.v-messages
Ex: ncvloginverter.v –messages (RTL code compilation)

Ø Compile the test bench file with message

option: ncvlog testbenchname.v-message
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Ex: ncvlog inverter.v –messages

Note: Check out for error and warnings. If any then go back to text editor and edit and the
compile
ü Elaborate the top level design(test bench)

Ø ncelab toplevelmodulename-access+rwc-message
Top level module name to be elaborated is the name of test bench module
ncelab inv_test –access +rwc –messages

ü Simulate the top level design

Ø Non GUI mode
ncsim toplevelmodulename
ncsim inv_test

Ø In GUI Mode
Ncsim toplevelmodulename-gui
ncsim inv_test -gui
Now a console and Design Browser windows of Simvision are opened.
In the Design Browser Window,Select the toplevelmodulename scope(Ex:inv_test) and
select all the signals displayed and click on the waveform button in the toolbar.
Waveform Window opens.Press run to run the simulation for a time period specified in
the time field.

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Synthesize procedure using Cadence Tool

ü # cd csh
ü #source cshrc
ü # cd Cadence_digital_labs/Workare
#cd rclabs --- for digital synthesis enter into rclabs
#cd rtl --- The verilog file to be sythesizd must be copied into this
directory form the directory where the simulated code is present. i.e from
your directory created under Workarea.
cd .. --- Come back rclabs directory
#cd work --- Get into work directory under rclabs to synthesize the hdl file
present in rtl directory.
#rc –gui --- this would start a GUI window for synthesizing.
ü rc:/>set_attr lib_search_path ../library
ü rc:/>set_attribute hdl_search_path ../rtl
ü rc:/>set_attr library slow_highvt.lib (if this step gives an error then close the rc
window by closing the GUI window and then type the following)
• #cd /
• #cd root/Cadence_digital_labs
• #tar -xzvf Cadence_digital_labs.tar.gz (this should work and then continue
with RC labs again)
rc:/>read_hdl {file_name.v} Ex:read_hdl {ff1.v} (ff1.v must be in rtl directory of
rclabs)

ü rc:/>read_sdc ../constraints_filename.g (if any constraints file they must be read here)
ü rc:/>elaborate
ü rc:/>synthesize -to_mapped -effort medium ---now you must be able to see the
schematic else go to file and click on update GUI in GUI window.
ü rc:/>write > any_name.v
rc:>report timing - This gives the timing reports like delay, propagation so on
rc:/>report power - This gives the power dissipation report static and dynamic
power dissipation
rc:/>report area - This gives no of cell used and the area used for the calls.

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1. INVERTER
Step by step procedure to be followed for all the digital ASIC designs:
Step 1: Write the RTL code (eg. inverter.v) and testbench code (eg. inverter_tb.v) in rtl
directory:

// Verilog Code: //Test bench

module inv_tb;
wire b;
module inverter(b, a);
reg a;
input a; inverter i1(b,a);
output b; initial
assign b = ~a; begin
endmodule a=1’b0;
#10 a=1’b1;
#10 a=1’b x;
#10 a= 1’bz;
end
endmodule
Step 2: Write the constraints in work directory.
Constraints:
set_input_delay -max 1.0 [get_ports "a"]
set_output_delay -max 1.0 [get_ports "b"]
Step 3: Simulation tool is invoked in rtl directory by the command : nclaunch -64 &
Step 4: Once the tool is invoked, compile the rtl code and testbench code as shown in step 4 &
step 5.

Step 5: Compiling testbench code (eg. inverter_tb.v)

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Step 6: Elaborate the RTL code.

Step 7: Elaborate the testbench code

Step 8: Simulate the testbench code.

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Output Waveform:

2. BUFFER
//Verilog code //Test bench

module buffer(b,a,en); module buffertest;

input a,en; reg a,en;
output b; wire b;
reg b; buffer b1(b,a,en);
always@(a or en) initial
begin begin
if (en==1) en=1’b1;
b=a; a=1'b0;
else #10 a=1'b1;
b=1’bz; #10 a=1'b0;
end #10 a=1'bx;
endmodule #10 a=1'bz;
#10 a=1'b0;
end
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endmodule
Constraints:
set_input_delay -max 1.0 [get_ports "a"]
set_input_delay -max 1.0 [get_ports "en"]
set_output_delay -max 1.0 [get_ports "b"]

Output Waveform:

3. TRANSMISSION GATE
//Verilog code //Test bench
module trans_tb;
module trans(b, a, cntrl1, cntrl2); wire b ;
input a; reg a ;
input cntrl1,cntrl2; reg cntrl1,cntrl2;
output b;
reg b; trans t1(b, a, cntrl1, cntrl2);
always @ (a or cntrl1 or cntrl2) initial
begin begin
if (cntrl1 = = cntrl2) a= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0 ;
b = 1’bx; #10 a= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1;
else if (cntrl1 = = 0 & cntrl2 = = 1) #10 a= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0;
b = a; #10 a= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b1;
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else #10 a= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0;

b = 1'bz; #10 a= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1;
end #10 a= 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0;
endmodule #10 a= 1'b1; cntrl1 = 1'b1 ; cntrl2 = 1'b1;
end
endmodule
Constraints:
set_input_delay -max 1.0 [get_ports "a"]
set_input_delay -max 1.0 [get_ports "cntrl1"]
set_input_delay -max 1.0 [get_ports "cntrl2"]
set_output_delay -max 1.0 [get_ports b"]

Output Waveform:

4. LOGIC GATES

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//Verilog code //Test bench

module logic(f1,f2,f3,f4,f5,f6,a,b); module logictest;

input a,b; reg a,b;
output f1,f2,f3,f4,f5,f6; wire f1,f2,f3,f4,f5,f6;
assign f1=a&b; logic l1(f1,f2,f3,f4,f5,f6,a,b);
assign f2=a|b; initial
assign f3=~a; begin
assign f4=~(a|b); a=1'b0;
assign f5=~(a&b); b=1'b0;
assign f6=a^b; #10 b=1'b1;
endmodule #10 a=1'b1;
b=1'b0;
#10 b=1'b1;
#10;
end
endmodule
Constraints:
set_input_delay -max 1.0 [get_ports a"]
set_input_delay -max 1.0 [get_ports b"]
set_output_delay -max 1.0 [get_ports f1"]"
set_output_delay -max 1.0 [get_ports f2"]"
set_output_delay -max 1.0 [get_ports f3"]"
set_output_delay -max 1.0 [get_ports f4"]"
set_output_delay -max 1.0 [get_ports f5"]"
set_output_delay -max 1.0 [get_ports f6"]"

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Output Waveform:

5. FLIP-FLOPS
a) SR FLIP-FLOP
//Verilog code //Test bench
module srff(q,qb,s,r,clk,rst); module srfftest;
input s,r,clk,rst; reg s,r,clk,rst;
output q,qb; wire q,qb;
reg [1:0] sr; srff s1(q,qb, s,r,clk,rst);
reg q,qb; initial
always @(posedge clk) clk=1'b0;
begin always

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if (rst ==1) #5 clk=~clk;

q=1’b0; initial
else begin
sr={s,r}; rst = 1’b1;
case(sr) #10 rst = 1’b0; s=1'b0;r=1'b1;
2'b00:q=q; #10 s=1'b1;r=1'b0;
2'b01:q=1'b0; #15 s=1'b0;r=1'b0;
2'b10:q=1'b1; #20 s=1'b1;r=1'b1;
2'b11:q=1'bx; #20;
endcase end
qb=~q; endmodule
end
endmodule
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"] set_clock_transition
-fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "s"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "r"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"]

Output Waveform:

b) D FLIP-FLOP

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Constraints:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
//Verilog code //Test bench

module dff(d,clk,rst,q,qb); module dfftest;

input d,clk,rst; reg clk,d,rst;
output q,qb; wire q,qb;
reg q,qb; dff d1(d,clk,rst,q,qb);
always@(posedge clk) initial
begin clk = 1'b0;
if (rst ==1) always
q=1’b0; #5clk=~clk;
else initial
q=d; begin
qb=~d; rst=1’b1;
end #10 rst = 1’b0;d=1'b0;
endmodule #10d=1'b1;
end
endmodule

set_clock_transition -rise 0.1 [get_clocks "clk"]

set_clock_transition -fall 0.1 [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "d"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"]

Output Waveform:

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c) JK FLIP-FLOP
//Verilog code //Test bench

module jkff(q,qbar,j.k,clk,rst); module jkfftest;

input j,k,clk,rst; reg j,k,clk,rst;
output q,qbar; wire q,qbar;
reg q,qbar; jkff jk1(q,qbar,j,k,clk,rst);
reg [1:0] jk; initial
always@(posedge clk) clk=1'b0;
begin always
if(rst) #5 clk=~clk;
q = 1’b0; initial
else begin
jk = {j,k} rst = 1’b1;
case (jk) #10 rst = 1’b0; j=1’b0;k=1’b0;
2’b00: q=q; #10 k=1’b1;
2’b01: q=1’b0; #10 j=1’b1; k=1’b0;
2’b10: q=1’b1; #10 k=1b1;
2’b11: q=~q; end
endcase endmodule
assign qbar =~q;
end
endmodule
Constraints:
create_clock -name clk -period 10 -waveform {0 5} [get_ports
clk"] set_clock_transition -rise 0.1 [get_clocks clk"]
set_clock_transition -fall 0.1 [get_clocks clk"]
set_input_delay -max 1.0 [get_ports j"] -clock [get_clocks clk"]
set_input_delay -max 1.0 [get_ports k"] -clock [get_clocks clk"]
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set_input_delay -max 1.0 [get_ports rst"] -clock [get_clocks clk"]

set_output_delay -max 1.0 [get_ports q"] -clock [get_clocks clk"]
set_output_delay -max 1.0 [get_ports qbar"] -clock [get_clocks clk"]
Output Waveform:

d) Master Slave JK FLIP-FLOP

//Verilog code //Test bench

module ms_jkff (qs,qsb,qm,qmb,j,k,clk,rst); module ms_jkff_test;
output qs, qsb; reg j,k,clk,rst;
inout qm,qmb; wire qs,qsb,qm,qmb;
input j,k,clk,rst; ms_jkff ms1(qs,qsb,qm,qmb,j,k,clk,rst);
wire clkbar; initial
assign clkbar = ~ clk; clk = 1’b0;
jkff jk1 (qm,qmb ,j,k,clk,rst); always
jkff jk2 (qs,qsb,qm,qmb,clkbar,rst); #10 clk = ~clk;
endmodule initial
begin
rst = 1’b1; j = 1’b0; k= 1’b0;
#15 rst = 1’b0;
#25 k = 1’b1;
#25 j = 1’b1; k= 1’b0;
#25 k= 1’b1;
end
endmodule
Constraints:
create_clock -name clk -period 10 -waveform {0 5} [get_ports
clk"] set_clock_transition -rise 0.1 [get_clocks clk"]
set_clock_transition -fall 0.1 [get_clocks clk"]
set_input_delay -max 1.0 [get_ports “rst"] -clock [get_clocks clk"]
set_input_delay -max 1.0 [get_ports j"] -clock [get_clocks clk"]

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set_input_delay -max 1.0 [get_ports k"] -clock [get_clocks clk"]

set_output_delay -max 1.0 [get_ports qs"] - clock [get_clocks clk"]
set_output_delay -max 1.0 [get_ports qsb"] -clock [get_clocks clk"]

Output Waveform:

e) T FLIP-FLOP

//Verilog code //Test bench

module tff(q,qb, rst,clk,t); module tfftest;

input rst,clk,t; reg rst,clk,t;
output q,qb; wire q,qb;
reg q,qb; tff t1(q,qb,rst, clk,t);
always @(posedge clk) initial
begin clk=1'b0;
if (rst ==1) always
q=1’b0; #5 clk=~clk;
else initial
if (t==0) begin
q=q; rst = 1’b1;
else #10 rst = 1’b0;t=1'b0;
q=~q; #10 t=1'b1;
qb=~q; end
end endmodule
endmodule
Constraints
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create_clock -name clk -period 10 -waveform {0 5} [get_ports

clk"] set_clock_transition -rise 0.1 [get_clocks clk"]
set_clock_transition -fall 0.1 [get_clocks clk"]
set_input_delay -max 1.0 [get_ports rst"] -clock [get_clocks clk"]
set_input_delay -max 1.0 [get_ports t"] -clock [get_clocks clk"]
set_output_delay -max 1.0 [get_ports q"] -clock [get_clocks clk"]
set_output_delay -max 1.0 [get_ports qb"] -clock [get_clocks "clk"]

Output Waveform:

6. ADDERS
a) PARALLEL ADDER:

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//Verilog code //Test bench
// Full Adder module patest;
module fa(a,b,cin,sum,cout); reg [3:0]a,b;
input a,b,cin; reg cin=1'b0;
output sum, cout; wire cout;
assign sum=(a^b)^cin; wire [3:0]s;
assign cout=((a&b)|(b&cin)|(cin&a)); pa p1(a,b,cin,s,cout);
endmodule initial
begin
// Parallel Adder a=4'b0; b=4'b0;
module pa(a,b,cin,s,cout); #10 a=4'd1;b=4'd2;
input [3:0]a,b; #20 a=4'd9; b=4'd3;
input cin; #10 a=4'd9; b=4'd7;
output [3:0]s; #10;
output cout; end
wire [2:0]c; endmodule
fa f1(a[0],b[0],cin,s[0],c[0]);
fa f2(a[1],b[1],c[0],s[1],c[1]);
fa f3(a[2],b[2],c[1],s[2],c[2]);
fa f4(a[3],b[3],c[2],s[3],cout);
endmodule

Constraints:
set_input_delay -max 1.0[get_ports a"]
set_input_delay -max 1.0[get_ports b"]
set_input_delay -max 1.0[get_ports cin"]
set_output_delay -max 1.0[get_ports s"]
set_output_delay -max 1.0[get_ports cout"]
Output Waveform:

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b) SERIAL ADDER
//Verilog code //Test bench
module serial_adder(sum,clk,load,a,b); module serialtest;
input clk,load; reg clk,load;
input[3:0] a,b; reg[3:0] a,b;
output[4:0] sum; wire[4:0] sum;
reg[3:0] ina,inb; serial_adder s1(sum,clk,load,a,b);
reg [4:0] org; initial
wire so,co; clk=1'b0;
always@(posedge clk) always #5 clk=~clk;
begin initial
if(load) begin
begin load=1'b1;
ina=a; inb = b; org = 5’b0; a = 4’d9;
end b = 4’d8;
else #10 load = 1’b0;
begin #30 ;
ina = {1’b0,ina[3:1]}; end
inb = {1’b0,inb[3:1]}; endmodule
org[4] = co;
org[3:0] = {so,org [3:1]};
end
end
assign so = ina[0]^inb [0]^org[4];
assign co = (ina[0] & inb[0] |( inb[0] &
org[4])|org[4] & ina[0]);
assign sum = org;
endmodule
Constraints:
create_clock -name clk -period 10 -waveform {0 5} [get_ports
clk"] set_clock_transition -rise 0.1 [get_clocks clk"]
set_clock_transition -fall 0.1 [get_clocks clk"]
set_clock_uncertainty 1.0 [get_ports clk"]
set_input_delay -max 1.0 [get_ports “load"] -clock [get_clocks clk"]
set_input_delay -max 1.0 [get_ports a"] -clock [get_clocks clk"]
set_input_delay -max 1.0 [get_ports b"] -clock [get_clocks clk"]
set_output_delay -max 1.0 [get_ports sum"] -clock [get_clocks clk"]
Output Waveform:

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7. COUNTERS
a) Asynchronous counter

//Verilog code //Test bench

module async(clk,q); module asynctest;

input clk; reg clk;
output q; wire [3:0]q;
reg [3:0]q; async a1(clk,q);
initial initial
q=4'b1111; begin
always @(negedge clk) clk=1'b0;
q[0]=~q[0]; end
always @(negedge q[0]) always
q[1]=~q[1]; #5 clk=~clk;
always @(negedge q[1]) endmodule
q[2]=~q[2];
always @(negedge q[2])
q[3]=~q[3];
endmodule

Constraints:
create_clock -name clk -period 10 -waveform {0 5} [get_ports
clk"] set_clock_transition -rise 0.1 [get_clocks clk"]
set_clock_transition -fall 0.1 [get_clocks clk"]
set_clock_uncertainty 1.0 [get_ports clk"]
set_output_delay -max 1.0 [get_ports q"] -clock [get_clocks clk"]

Output Waveform:

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b) SYNCHRONOUS COUNTER

//Verilog code //Test bench

module sync(clk,reset,q); module synctest;

input clk,reset; reg clk,reset;
output [3:0]q; wire [3:0]q;
reg [3:0]q; sync sc1(clk,reset,q);
always @(negedge clk) initial
if(reset) begin
q=4'b0; clk=1'b0;
else end
q=q+1; always
endmodule #5 clk=~clk;
initial
begin
reset=1'b1;
#10 reset=1'b0;
end
endmodule

Constraints:
create_clock -name clk -period 10 -waveform {0 5} [get_ports
clk"] set_clock_transition -rise 0.1 [get_clocks clk"]
set_clock_transition -fall 0.1 [get_clocks clk"]
set_clock_uncertainty 1.0 [get_ports clk"]
set_input_delay -max 1.0 [get_ports reset"] -clock [get_clocks clk"]
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set_output_delay -max 1.0 [get_ports q"] -clock [get_clocks clk"]

Output Waveform:

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PART – B

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3) PART B[1]: SCHEMATIC SIMULATION

PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION
I. Commands to get into Cadence

1. Right Click and open the terminal window

2. Type the following commands as follows and press enter.
i) csh
ii) source cshrc
iii) ls – shows the directories – check for existence of cadence_analog_labs_613.If
not found inform the system admin else go to next step
iv) cd cadence_analog_labs_613
v) virtuoso &

II. Procedure for Schematic simulation using Cadence

1. Now two windows must open i)virtuoso/command interpreter window ii)”Whats New…”
2. Close the 2nd window

st
3. Use 1 window i.e virtuoso window(CIW) for further processing.

i) Create a New Library

ii) Create Schematic Cell view.
iii) Create the Symbol for schematic Cell view.
iv) Create the test Cell view.
v) Analog simulation by spectre

i) Procedure for Creating New Library.

a. File –New – Library
b. Name : Give name for ur library Ex: VLSILAB
c. Enable Attach to an existing technology library, Click OK
d. Attach the library to the technology library gpdk180.Click OK

ii) Create Schematic Cell view.

st
a. Go to 1 window i.e virtuoso(CIW)
b. File-New-Cell view

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c. Setup the new file form

d. Add the required components from the libraries and make the connections.
1. Go to instance fixed menu or use shortcut key “I” from keypad to go
instances
2. Click on browse. This opens the library browser
3. Now select the appropriate library for components like
Gpdk180 ----------------- nmos, pmos
Analog library ---------- Vdd, Gnd, Vcc, Vpulse, Vsin
4. Make the connections by using fixed narrow wire key
5. Click Check and Save button

iii) Creating the Symbol for schematic Cell view

a. In the schematic window, execute

Crate – Cell view – From Cell view

The cell view from cell view window appears
Check Lib Name, Cell Name, From View name must be schematic
Press ok

b. Now Symbol generation form appears. Click Ok If No changes required

c. A new window with with default symbol is created.
d. Edit the symbol if you want to give actual symbol shape else continue.
i. Execute Create-Cell view-from cell view
ii. Library Name and Cell Name must be same which you have used
for schematic. Press OK
iii. Check for the position of pin side.Prss OK
iv. Edit for the shape by Create-Shape-Choose required options
to edit.

iv) Creating the new test cell view

a. Go to CIW window, Execute File-New-Cell view

b. Setup the new file form

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Library: Select the one you a created.

Cell: Cell name must be different from the name used in schematic cell
view. Ex: Inverter_test
View: Schematic
Type: Schematic press OK
c. Follow the step 3(ii) d to make the required connections

v) Analog simulation by SPECTRE.

a. In test cell view window
Launch – ADE L(Analog Design Environment)
b. Execute Setup—Simulation/directory/Host A new window opens
c. Set the simulation window to spectre and click ok
d. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as
lib and section type as stat then press OK.
e. Execute Analysis – Choose. A window opens.
f. Select the type and set the specifications and press OK
g. Execute Output s—to be plotted – Select on Schematic
h. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from
your test Schematic using mouse
i. Execute Simulation -- Net list and Run

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Experiment 1(a): Inverter Schematic Cell View

Specifications: nmos NM0W=2u L=.180U & NM1W=2U L=.180U

Input Pins Vdd,Vss,Vin,Vbias
Output pin Vout

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Specifications: Vpulse  V1 = 0 Vdd = 1.8

V2 = 1
td = 0,tr=tf=1 n, ton= 10n ,T=20n
Simulation Settings

Setup for transient analysis:

1. Stop time =

Setup for D.C analysis

1. Component to be selected in schematic is_______for d.c analysis
2. Start = -5 Stop = 5 resp.
Setup for A.C analysis

1. Turn on Frequency button

2. In sweep range section – Start ____ stop ______
3. Select point per decade = _____
Check enables and apply

Expected Waveform:
Transient analysis

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DC Analysis

Experiment 2(a): Common source Amplifier schematic Cell view

The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a

voltage amplifier. As a transconductance amplifier, the input voltage is seen as modulating the
current going to the load. As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance according to Ohm's
law. The easiest way to tell if a FET is common source is to examine where the signal enters, and
leaves. The remaining terminal is what is known as "common". In this example, the signal enters
the gate, and exits the drain. The only terminal remaining is the source. This is a common-source
FET circuit.

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Specifications: nmos PM0W=50u L=1U

Pmos NM0W=10U L01U
Input Pins Vdd,Vss,Vin,Vbias
Output pin Vout

Common source Amplifier schematic test Cellview

Specifications: Vsin  a.c magnitude = 1 Vdd = 2.5
d.c voltage =0 Vss = -2.5
offset voltage = 0 Vbias = 2.5
amplitude =5m
frequency =1K

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Simulation Settings

Setup for transient analysis:

2. Stop time = 5m

Setup for D.C analysis

3. Component to be selected in schematic is Vsin for d.c analysis
4. Start = -5 Stop = 5 resp.

Setup for A.C analysis

4. Turn on Frequency button

5. In sweep range section – Start 7 stop – 150 to 100M
6. Select point per decade = 20
Check enables and apply

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Expected Waveform:
Transient analysis

DC Analysis

AC Analysis- Frequency

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Experiment 3(a): Common drain amplifier schematic Cell view

A common-drain amplifier, also known as a source follower, is one of three basic single-stage
field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the
gate terminal of the transistor serves as the input, the source is the output, and the drain is common to
both (input and output), hence its name. The analogous bipolar junction transistor circuit is the
common-collector amplifier. In addition, this circuit is used to transform impedances. For example, the
Thévenin resistance of a combination of a voltage follower driven by a voltage source with high
Thévenin resistance is reduced to only the output resistance of the voltage follower, a small resistance.
That resistance reduction makes the combination a more ideal voltage source. Conversely, a voltage
follower inserted between a small load resistance and a driving stage presents an infinite load to the
driving stage, an advantage in coupling a voltage signal to a small load.

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Specifications: nmos NM0W=50u L=1U & NM1W=10U L=1U

Input Pins Vdd,Vss,Vin,Vbias
Output pin Vout

Common drain amplifier test cellview

Specifications: Vsin  a.c magnitude = 1 Vdd = 2.5

d.c voltage =0 Vss = -2.5
offset voltage = 0 Vbias = 2.5
amplitude =5m
frequency =1K

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Simulation Settings

Setup for transient analysis:

1. Stop time = 5m

Setup for D.C analysis

1. Component to be selected in schematic is Vsin for d.c analysis
2. Start = -5 Stop = 5 resp.

Setup for A.C analysis

1. Turn on Frequency button

2. In sweep range section – Start 7 stop – 150 to 100M
3. Select point per decade = 20
Check enables and apply

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Expected Waveform:
Transient analysis

DC Analysis

AC Analysis- Frequency

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Experiment 4(a): Differential Amplifier schematic Cell view

Specifications: nmos NM0&NM1W=3u L=1U ,

NM2,NM3  4.5U L=1U
Pmos PM0 & PM1W=15U L=1U
Input Pins V1,V2,Idc
Output pin Vout
Bidrectional pins Vdd,Vss

Differential Amplifier schematic test Cellview

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Specifications: Vsin  a.c magnitude = 1 Vdd = 2.5

amplitude =5m Vss = -2.5
frequency =1K Idc = d.c.current=30u
Simulation Settings

Setup for transient analysis:

3. Stop time = 5m

Setup for D.C analysis

5. Component to be selected in schematic is_______for d.c analysis
6. Start = -5 Stop = 5 resp.
Setup for A.C analysis

7. Turn on Frequency button

8. In sweep range section – Start ____ stop ______
9. Select point per decade = _____
Check enables and apply

Expected Waveform:

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Experiment 5(a) : OPAMP schematic Cell view

\
Specifications: Diff_Amplifie From your library
r Cs_amplifier From your library
Input Pins Vinv,Vnoninv,Id.c,Vdd,Vss

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Output pin Vout

OPAMP schematic test Cell view

Specifications: Vsin  a.c magnitude = 1 Vdd =5

d.c voltage =0 Vss = -2.5
offset voltage = 0 Idc = d.c current=30 u
amplitude =0.5m
frequency =1K
Simulation Settings

Setup for transient analysis:

4. Stop time =

Setup for D.C analysis

7. Component to be selected in schematic is_______for d.c analysis
8. Start = -5 Stop = 5 resp.
Setup for A.C analysis

10. Turn on Frequency button

11. In sweep range section – Start ____ stop ______
12. Select point per decade = _____
Check enables and apply

Expected Waveform:

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Experiment 6(a) : R-2R DAC schematic Cell view

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Table for component building:

Lib Name Cell Name Properties
gpdk180 polymer R=2K and 1K
analog lib Idc,gnd idc=30u
My.Library op-amp symbol

D0,D1,D2,D3 –Input pins Vout-output pin Vdd and Gnd –Input pins

R-2R DAC Test Cellview

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Table for component building:

Lib Name Cell Name Properties

analog lib Vpulse V0: V1=0V V2=2 Total period(T)=10n Pulse width(Ton)=5n
V1: V1=0V V2=2 Total period(T)=20n Pulse width(Ton)=10n
V2: V1=0V V2=2 Total period(T)=40n Pulse width(Ton)=20n
V3: V1=0V V2=2 Total period(T)=80n Pulse width(Ton)=40n
Vdc,gnd Vdd=2 Vss=-2

My.Library R-2R DAC symbol

Simulation Settings

Setup for transient analysis:

5. Stop time =

Setup for D.C analysis

9. Component to be selected in schematic is_______for d.c analysis
10. Start = -5 Stop = 5 resp.
Setup for A.C analysis

13. Turn on Frequency button

14. In sweep range section – Start ____ stop ______
15. Select point per decade = _____
Check enables and apply

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Output Waveform:

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PART B[2]:LAYOUT DESIGNING

I) Layout Design Rules

0A Minimum NBURIED width 1.0um
0B Minimum NBURIED space 1.0um
1A Minimum NWELL width 1.0um
1B Minimum NWELL space 1.0um
1C Minimum NBURIED enclosure of NWELL 0.3um
1D Minimum PWELL width 1.0um
1E Minimum PWELL space 1.0um
1F Minimum NBURIED enclosure of PWELL 0.3um
2A Minimum OXIDE width 0.4um
2B Minimum OXIDE space 0.3um
2C Minimum NWELL enclosure of OXIDE 0.5um
2D Minimum NWELL to OXIDE space 0.5um
3A Minimum NIMP width 0.4um
3B Minimum NIMP space 0.4um
3C Minimum NIMP enclosure of OXIDE 0.2um
3D Minimum NBURIED enclosure of NIMP 0.6um
4A Minimum PIMP width 0.4um
4B Minimum PIMP space 0.4um
4C Minimum PIMP enclosure of OXIDE 0.2um
4D Minimum NBURIED enclosure of PIMP 0.6um
4E PIMP and NIMP cannot overlap
5A Minimum POLY width 0.18um
5B Minimum POLY space 0.3um
5C Minimum POLY extension beyond OXIDE (poly endcap) 0.2um
5D Minimum OXIDE extensions beyond gate POLY 0.4um
5E Minimum Poly to OXIDE spacing 0.2um
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6A Minimum and maximum width of CONT 0.2um

6B Minimum CONT space 0.2um
6C Minimum OXIDE enclosure of CONT 0.2um
6D Minimum POLY enclosure of CONT 0.2um
6E Minimum POLY to CONT space 0.2um
6F Minimum NIMP enclosure of CONT 0.2um
6G Minimum PIMP enclosure of CONT 0.2um
6H Minimum CONT to Oxide space 0.2um
7A Minimum METAL1 width 0.3um
7B Minimum METAL1 space 0.3um
7C Minimum METAL1 enclosure of CONT 0.1um
8A Minimum and maximum width of VIA1 0.2um
8B Minimum VIA1 space 0.3um
8C Minimum METAL1 enclosure of VIA1 0.1um
9A Minimum METAL2 width 0.3um
9B Minimum METAL2 space 0.3um
9C Minimum METAL2 enclosure of VIA1 0.1um
10A Minimum and maximum width of VIA2 0.2um
10B Minimum VIA2 space 0.3um
10C Minimum METAL2 enclosure of VIA2 0.1um
11A Minimum METAL3 width 0.3um
11B Minimum METAL3 space 0.3um
11C Minimum METAL3 enclosure of VIA2 0.1um
11D Minimum METAL3 enclosure of VIA2 for metal capacitor 0.1um
12A Minimum CAPMETAL width 0.5um
12B Minimum METAL2 enclosure of CAPMETAL 0.4um
12C Minimum CAPMETAL enclosure of VIA2 0.2um
12D Minimum CAPMETAL enclosure of METAL3 0.3um

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13A Maximum distance from a source/drain OXIDE region to the nearest well tie 10um
14A Minimum and maximum width of VIA3 0.2um
14B Minimum VIA3 space 0.3um
14C Minimum METAL3 enclosure of VIA3 0.1um
15A Minimum METAL4 width 0.3um
15B Minimum METAL4 space 0.3um
15C Minimum METAL4 enclosure of VIA3 0.1um
16A Minimum and maximum width of VIA4 0.2um
16B Minimum VIA4 space 0.3um
16C Minimum METAL4 enclosure of VIA4 0.1um
17A Minimum METAL5 width 0.3um
17B Minimum METAL5 space 0.3um
17C Minimum METAL5 enclosure of VIA4 0.1um
18A Minimum and maximum width of VIA5 0.2um
18B Minimum VIA5 space 0.3um
18C Minimum METAL5 enclosure of VIA5 0.1um
19A Minimum METAL6 width 0.3um
19B Minimum METAL6 space 0.3um
19C Minimum METAL6 enclosure of VIA5 0.1um
20A Minimum BONDPAD width 45.0um
20B Minimum BONDPAD space 10.0um
20C Minimum and Maximum METAL1 enclosure BONDPAD 3.0um
20D Minimum and Maximum METAL2 enclosure BONDPAD 3.0um
20E Minimum and Maximum METAL3 enclosure BONDPAD 3.0um
20F Minimum and Maximum METAL4 enclosure BONDPAD 3.0um
20G Minimum and Maximum METAL5 enclosure BONDPAD 3.0um
20H Minimum and Maximum METAL6 enclosure BONDPAD 3.0um

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Some of the important design rules mentioned above are pictorially represented in next page.

(p.t.o)
N WELL RULE

OXIDE RULE

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N imp/ P imp RULES

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Poly RULE

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PMOS LAYOUT: (W/L) = (2um / .18 um )

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The PMOS is designed with respect to the design rules mentioned. The PMOS is designed
with a respect to the W/L ratio.

W  Width of channel Nimp

L  Width of POLY1

Layout of PMOS: ( W/L ) = (2um/.18um)

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NMOS LAYOUT : (W/L) = (2um / .18 um )

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LAYOUT OF NMOS : (W/L) = ( 2um/.18um)

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II ) LAYOUT GENERATION & TESTING PROCEDURE

1. Open the Inverter schematic window

2. Launch → Lay out XL
3. A window opens, Enable create New option, A New – cell view form open
set the cell Name: Inverter ( Same as Schematic )
View Name : Layout
and click OK.
A LSW [ Layout schematic window] & blank Layout window opens.
4. In Layout window,
Execute Connectivity – Generate – All from source.
In the layout editor window, A Generate Layout form appears. In this form enable Labels
options &
Click OK.
5. Now, we can view the components and Area of silicon [boundary]. The Area defines that
the required layout can be fitted in to that. There for try to restrict to this area.
NOTE: As a beginner extend the height of area by maximum of 2 units.
6. Stretch the area by using stretch Key from edit window.
7. Move the components in to specified area and arrange them at required positions properly.
8. Press shift – F to observe the internal view of the NMOS & PMOS.
9. Now Zoom the layout editor window and align the NMOS & PMOS exactly. [That is poly
of both MOS must match to avoid the DRC errors].
10. Make the required connections by selecting the required material from LSW window like
poly, metal then create the required shapes by executing
Create → Shape → Path / Rectangle
11. Once the required connection are made, the next step is to connect the required overlapping
materials by using corresponding connectors (via)s
Ex: The input ‘A’ in inverter layout
Input A - Contact made up of metal 1
Gate terminal shorted is poly.
As input A is placed on poly, now these two different layers are connected by using
corresponding connectors.

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That is M1 – POLY1 Via

There for Execute Create – Via
In the Vias form, select the corresponding connector required and click Hide and the
place on required position in layout by double click.
12. Finally save the layout.

13. Testing [Running DRC, ERC, LVS & RCX]

A) Running DRC( Design Rule Checker)

i) Execute Assura – Run DRC.

The DRC form opens
Check:
ii) Library: ? Cell: ? View: ? [Layout]. This
should be same what you have set
iii) Technology – gpdk
180. Then click OK.
iv) A progress form appears.[Don’t click on OK]
v) When DRC finishes, a dialog box appears asking you if you want to view your
DRC results, and then click yes to view the results of this form.
vi) If any DRC errors exist, a Error Layer window [ELW] appears. Open ELW
window and rectify the errors by selecting the errors one by one.
vii) Then follow step (i) to (v) mentioned above unit you get a message as “ No
DRC errors found” then clck on close to terminate the DRC run.

B) Running LVS( Layout Vs Schematics) .

i) Assura – LVS in Layout window
ii) A Assura – Run LVS window opens.
Check:

Lib: Cell: View:

→Layout Design Source
Lib: Cell: View:

These should be have Schematic & Layout to be compared CLICK OK.

iii) The LVS begins and progress. Form appears.

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iv) If schematic & Layout matches completely, you will get the form displaying
“Schematic and Layout Match”
If Not matching, a form informs LVS completed successfully and asks if you
want view the results of this run.
CLICK Yes in the form.
v) The LVS debug form opens indicating the mismatches and you need to correct
all these mismatches and Re – run the LVS.

C) Running RCX.
i) Assura – Run RCX.
ii) Assura RCX form opens.

iii) RCX progress form appears, wait until it completes the process.
iv) Whwn RXC complete, a dialog box appears, informs you that Assura RCX run
Completed Successfully.
v) Go to CIW (Virtuso window)
File – open – av- extracted view form the corresponding library.
Then, the av-extracted view window opens with parasitic components (RC).
Observe the view by zooming

III) Creating Configuration View

i) Creating Config View
a. Go to CIW window, Execute File-New-Cell view
b. Setup the new file form
Library: Select the one you a created.
Cell: Cell name must be different from the name used in schematic cell
view. Ex: Inverter_test
View: Config
Type: Schematic press OK
A Hierarchy Editor window and New Configuration Form opens

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c. In the New Configuration form, Click on Use Templates present at the

bottom of form. A use Templates window opens.
d. In Use Template form set Name: SPECTRE by scroll down button, then
Click OK.
e. Now,In the New Configuration window
Change Top Cell View: Schematics and
Set the Library Link: BLANK, Then CLICK OK in New Configuration
window. Now, Hierarchy Editor Window Opens.
f. In Hierarchy Editor Window, Press Table View tab and check cell building.
g. In Hierarchy Editor Window, Press Tree View tab and check occurances.
h. Press Recompute the Hierarchy icon
i. Save the current configuration.
j. Close the hierchy Editor window. Execute File – Close Window
IV) RUNNING circuit without parasites.

a. Go to CIW window and open (Inverter_test) Config view, Top cell view
form opens.
b. Enable Yes and Yes in Top Cell View form
c. Launch – ADE L(Analog Design Environment)
d. Execute Setup—Simulation/directory/Host A new window opens
e. Set the simulation window to spectre and click ok
f. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as
lib and section type as stat then press OK.
g. Execute Analysis – Choose. A window opens.
h. Select the type and set the specifications and press OK
i. Execute Output s—to be plotted – Select on Schematic
j. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from
your test Schematic using mouse
k. Execute Simulation -- Net list and Run

Propagation Delay Calculation

After completing STEP (IV) ,A waveform window will be opened.

a. In the waveform window execute Tool – Calculator. A calculator window

appears

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b. Click on special function tab. A window with different functions open, In

this select delay.
c. A addition form for calculation will be present to select and the parameters for
delay calculation.
i. Place the curser in signal1 text box, Enable Wave button and enable the
input Net(Vin) (Line) in the schematic window.
ii. Repeat above step for Signal 2.
iii. Set threshold values w.r.t experiment ( Ex: For Inverter ; Threshold
Value 1 & Threshold Value 2 to 0.9,this directs the calculator to
calculate the delay at 50% i.e at 0.9 volts( 1.8V/2)
iv. Click OK and observe the expression created in the calculator buffer.
d. Click on the Evaluate the buffer icon to perform the calculation and note
down the valued returned after execution.
e. Close the calculator window.

IV) RUNNING circuit with parasites.

a. Open the same hierarchy Editor window which is already set for config.
b. Select the TREE VIEW tab,this will show the design hierarchy in tree format.
c. CLICK right button on IO (lib name Inverter schematic) in TREE VIEW and
Select set instances view as av_extracted view.
d. Press Recompute the Hierarchy icon, the configuration is now updated from
schematic to av_extracted view
e. Then,go output waveform window( analog design environment) and click
Netlist and RUN
f. Observe the waveform with additional nets and parameters.
g. Calculate the delay again and match with the previous one.

Now you can conclude how much delay is introduced by parasites by comparing delay
with and without parasites and based on this we need to optimize the parasitic effect and reduce
the delay due to parasites. This finally leads to an optimized layout

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LSW
What is LSW?
It is a layout Vs Schematic window which
consists of different layers used for layout.

The layers to drawn or traced has to be

selected from the LSW window and the required
type of shape has to be created by using the

Create  Shape Select the required shapes.

The Shapes may be a Rectangle, Circle, Path so on.

Rectangle: This shape is chosen when the shape to

be drawn is rectangular and but the size is not
defined.

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Path: This shape is chosen when the path to be drawn is with predefined with.

The drawn shapes must follow the design rules.

Experiment 1(b): Inverter layout

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Experiment 2(b): Common Source layout

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Experiment 3(b): Common Drain layout

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Experiment 4(b): Differential Amplifier layout

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Experiment 5(b): Operational Amplifier layout

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