Chapter 1

Introduction to CMOS Circuit

Design

Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Department of Electrical Engineering
National Central University
Taoyuan, Taiwan
 Outline
 Background
 MOS Transistor Switches
 CMOS Logic
 Circuit and System Representation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

 Basics: Voltage
 Voltage
 Voltage is the difference in electrical potential between two
points in space. It is a measure of the amount of energy
gained or lost by moving a unit of positive charge from one
point to another. Voltage is measured in units of Joules per
Coulomb, known as a Volt
V1

Q1 Electric Field

 Kirchoff’s Voltage Law (KVL)

 The sum of voltages around any closed loop is zero
V2

R2
V1 R1 R3 V3 V1+V2+V3+V4=0
V1 R1 V2 R2 V3 R3 V1=V2=V3
R4

V4
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
 Basics: Current
 Current
 Current is the rate at which electric charge flow through a
given area. Current is measured in the unit of Coulombs per
second, which is known as an ampere.

I1

 Kirchoff’s Current Law (KCL)

 The sum of currents entering and existing a node must be
zero

I1 R1 I2 R2 I3 R3 I1+I2+I3=0

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

 Basics: Hydrodynamic Analogy

Height= V1
Height= V2

Current
Height= V

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

 Basics: Resistor
 Resistor
 Resistor is a passive electrical component that has a linear
current-voltage relationship as stated by Ohm’s law. The unit
of resistance is an ohm
 Hydrodynamic model of a resistor is a pipe

Current

Large diameter pipe  low resistance Small diameter pipe high resistance

 Symbol of a resistor

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

 Basics: Resistors in Series & in Parallel
 Resistors in series
R1 Vin
R1
R2
Vout=Vin[R2/(R1+R2)]

R2
R1+R2

 Resistor in parallel

R1 R2

R1R2/(R1+R2)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

 Basics: Capacitor
 Capacitor
 A capacitor is a device that stores energy in the form of
voltage
 The most common form of capacitors is made of two parallel
plates separated by a dielectric material
 Charges of opposite polarity can be deposited on the plates,
which resulting in a voltage V across the capacitor plates
 Capacitance is a measure of the amount of electrical charge
required to build up one unit of voltage across the plates.
Stated mathematically, C=Q/V, where Q is the number of
opposing charge pairs on the capacitor
 The unit of capacitance is the Farad (F)

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

 Basics: Capacitor
 Hydrodynamic analogy

Height= V Height= V

C1 I1 C2 I2

 Current-voltage relationship of the capacitor

 I=dQ/dt=C(dV/dt)
 Q=CV=It

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

 What did you learn?
A B C A B C
0 0 0 0 0 1
A A
C 0 1 0 C 0 1 1
B B
1 0 0 1 0 1
1 1 1 1 1 0

A B A B C
A B 0 1 0 0 1
1 0
A
0 1 0
B C
1 0 0

A B C 1 1 0

0 0 0
A
B C 0 1 1
D Q D Clk Q+
1 0 1 0 0
1 1 1
Clk
1 1
X 0 Q
X 1 Q

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

 Digital Circuit
 Binary counter
a
Present
Next state A
state b

a b A B B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

A = a’b + ab’ CK
B = a’b’ + ab’ CLR

Source: Prof. V. D. Agrawal

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
 Two-Input AND (1-bit Multiplier)

C
B

C=AxB

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

 Switch: MOSFET
 MOSFETs are basic electronic devices used
to direct and control logic signals in IC design
 MOSFET: Metal-Oxide-Semiconductor Field-
Effect Transistor
 N-type MOS (NMOS) and P-type MOS (PMOS)
 Voltage-controlled switches
 A MOSFET has four terminals: gate, source,
drain, and substrate (body)
 Complementary MOS (CMOS)
 Using two types of MOSFETs to create logic
networks
 NMOS & PMOS
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
 P-N Junctions
 A junction between p-type and n-type
semiconductor forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

 NMOS Transistor
 Four terminals: gate, source, drain, body
 Gate–oxide–body stack looks like a capacitor
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal–oxide–semiconductor (MOS) capacitor
 Even though gate is no longer made of metal

Source Gate Drain

Polysilicon
SiO2

n+ n+

p bulk Si

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

 NMOS Operations
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

 NMOS Operations (Cont.)
 When the gate is at a high voltage:
 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

Source Gate Drain

Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

 PMOS Operations
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

 Threshold Voltage
 Every MOS transistor has a characterizing
parameter called the threshold voltage VT
 The specific value of VT is established during
the manufacturing process
 Threshold voltage of an NMOS and a PMOS
NMOS PMOS
VA VA
Drain Source
VDD + VDD VDD VA=1
VGSp
Gate VA=1 VDD-|VTp| Mp Off
VA + Mn VA - Mp
Mn On Gate
VGSn - VA=0
Source VTn Mp On
VA=0
0 Mn Off Drain 0

Gate-source voltage Logic translation Gate-source voltage Logic translation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

 MOS Transistor is Like a Tap…

Source: Prof. Banerjee, ECE, UCSB

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

 MOSFET & FinFET

G
MOSFET
S(D) D(S)
Si-Substrate

D(S) D(S)

G G

S(D) S(D)

Oxide Buried Oxide

Si-Substrate Si-Substrate

Bulk FinFET SOI FinFET

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

 IG & SG FinFETs
 According to the gate structure, FinFET can
be classified as
 Independent-Gate (IG) FinFET
 Short-Gate (SG) FinFET
D(S) D(S)

G
G G
S(D) S(D)

Oxide Oxide

Si-Substrate Si-Substrate

IG FinFET SG FinFET

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

 MOS Switches
 NMOS symbol and characteristics
Vth
5v
5v 5v-Vth
0v 0v

 PMOS symbol and characteristics

0v Vth
5v 5v
0v Vth

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

 CMOS Switch
 A complementary CMOS switch
 Transmission gate

-s -s

Symbols a C b a b a b

s s s

0v
5v 5v
Characteristics 0v 0v
5v

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

 CMOS Logic-Inverter
 The NOT or INVERT function is often
considered the simplest Boolean operation
 F(x)=NOT(x)=x’ Vdd

Vin Vout Vin Vout

Vdd Vdd Vdd

0 1 1 Vdd/2 Indeterminate
0
logic level

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

 Combinational Logic
 Serial structure
S1=0 S1=0 S1=1 S1=1
a S2=0 S2=1 S2=0 S2=1
S1
0 1
S1
0 a!=b a!=b
S2
S2 1 a!=b a=b

b
S1=0 S1=0 S1=1 S1=1
a S2=0 S2=1 S2=0 S2=1
S1
0 1
S1
0 a=b a!=b
S2
1 a!=b a!=b
S2

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

 Combinational Logic
 Parallel structure
S1=0 S1=0 S1=1 S1=1
a S2=0 S2=1 S2=0 S2=1 S1
0 1
0 a!=b a=b
S1 S2 S2
1 a=b a=b

b
S1=0 S1=0 S1=1 S1=1 S1
a S2=0 S2=1 S2=0 S2=1
0 1
0 a=b a=b
S1 S2 S2
1 a=b a!=b

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

 NAND Gate

Output A
A 0 1

0 1 1
B B
1 1 0

A
Output
B

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

 NOR Gate

B A
0 1
Output
0 1 0
B
1 0 0

A
Output
B

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 Compound Gate
 F  (( AB )  (CD ))

A B

A
C D B
F
F C
D
A C

B D

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

 Structured Logic Design
 CMOS logic gates are intrinsically inverting
 The output always produces a NOT operation
acting on the input variables
 For example, the inverter shown below
illustrates this property
1 VDD

a=1 f=0

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

 Structured Logic Design
 The inverting nature of CMOS logic circuits
allows us to construct logic circuits for AOI
and OAI expressions using a structured
approach
 AOI logic function
 Implements the operations in the order AND then
OR then NOT
 E.g., g ( a , b , c , d )  a .b  c .d
 OAI logic function
 Implements the operations in the order OR then
AND then NOT
 E.g., g ( a , b , c , d )  ( a  b )  ( c  d )
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32
 Structured Logic Design
 Behaviors of nMOS and pMOS groups
 Parallel-connected nMOS
 OR-NOT operations
 Parallel-connected pMOS
 AND-NOT operations
 Series-connected nMOS
 AND-NOT operations
 Series-connected pMOS
 OR-NOT operations
 Consequently, wired groups of nMOS and
pMOS are logical duals of another

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

 Dual Property
 If an NMOS group yields a function of the form
g  a  (b  c )

then an identically wired PMOS array gives the

dual function
G  a  (b  c )

where the AND and OR operations have been

interchanged
 This is an interesting property of NMOS-PMOS
logic that can be exploited in some CMOS designs

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

 An Example of Structured Design
 X  a  b  (c  d )

VDD
c
b
d

a Group 1 Group 2

Group 3 X
b
a
c d

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

 An Example of XOR Gate
 Boolean equation of the two input XOR gate
 a  b  a  b  a  b, this is not in AOI form
 But, a  b  a  b  a  b, this is in AOI form
 Therefore, a  b  ( a  b )  a  b  a  b
VDD VDD
a b a b

b a b a
ab ab
a a a a

b b b b

XOR Gate XNOR Gate

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 Multiplexer
A 11
B 10
C 01 Y
A 1 Y D 00
B 0

S S1 S0
-S A

A
B
Y Y
S
B C

-S D

S1 -S1 S0 -S0

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

 Static CMOS Summary
 In static circuits at every point in time (except
when switching), the output is connected to
either Vdd or Gnd through a low resistance path
 Fan-in of n (or n inputs) requires 2n (n N-type and n P-
type) devices
 Non-ratioed logic: gates operate independent of
PMOS or NMOS sizes
 No path ever exists between Vdd and Gnd: low
static power
 Fully-restored logic (NMOS passes “0” only and
PMOS passes “1” only
 Gates must be inverting

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

 Circuit and System Representations
 Behavioral representation
 Functional, high level
 For documentation, simulation, verification
 Structural representation
 System level – CPU, RAM, I/O
 Functional level – ALU, Multiplier, Adder
 Gate level – AND, OR, XOR
 Circuit level – Transistors, R, L, C
 For design & simulation
 Physical representation
 For fabrication

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

 Example: 4-Input NAND
 Behavioral representation
 Y=~(A&B&C&D)
 Structural representation
A
 B
Y
C
D

 Physical representation
Vdd
A B C D

A
Y B
C

D
A B C D Vss

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40