PT6964

LED Driver IC

DESCRIPTION FEATURES
PT6964 is an LED Controller driven on a 1/5 to 1/8 • CMOS technology
duty factor. 10 segment output lines, 4 grid output • Low power consumption
lines, 3 segment/ grid output lines, one display • Multiple display modes (10 segments, 7 grids to 13
memory, control circuit, key scan circuit are all segments, 4 grids)
incorporated into a single chip to build a highly reliable • Key scanning (10 x 2 Matrix)
peripheral device for a single chip microcomputer. • 8-step dimming circuitry
Serial data is fed to PT6964 via a three-line serial • Serial interface for clock, data input, data output,
interface. Housed in a 28 pins SOP Package, PT6964 strobe pins
pin assignments and application circuit are optimized
• Available in 28 pins, SOP
for easy PCB Layout and cost saving advantages.

APPLICATIONS
• Micro-computer peripheral device
• VCR set
• Combo set

BLOCK DIAGRAM

Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
 PT6964

APPLICATION CIRCUIT

Notes:
1. The capacitor (0.1µF) connected between the GND and the VDD pins must be located as close as possible to the PT6964 chip.
2. The PT6964 power supply is separate from the application system power supply.

COMMON CATHODE TYPE LED PANEL

V1.4 2 October 2009

 PT6964

ORDER INFORMATION
Valid Part Number Package Type Top Code
PT6964-S 28 Pins, SOP, 300mil PT6964-S

PIN DESCRIPTION

PIN DESCRIPTION
Pin Name I/O Description Pin No.
Oscillator Input Pin
OSC I A resistor is connected to this pin to determine the oscillation 1
frequency
Data Input Pin
This pin inputs serial data at the rising edge of the shift clock
DI/O I/O 2
(starting from the lower bit)
Data Output Pin (N-Channel, Open-Drain)
Clock Input Pin This pin reads serial data at the rising edge and
CLK I 3
outputs data at the falling edge.
Serial Interface Strobe Pin
STB I The data input after the STB has fallen is processed as a 4
command. When this pin is HIGH", CLK is ignored.
Key Data Input Pins
K1 ~ K2 I The data sent to these pins are latched at the end of the display 5, 6
cycle. (Internal Pull-Low Resistor)
VDD - Power Supply 7, 21
Segment Output Pins (p-channel, open drain)
SG1/KS1 ~ SG10/KS10 O 8 ~ 17
Also acts as the Key Source
SG12/GR7 ~ SG14/GR5 O Segment / Grid Output Pins 18 ~ 20
GND - Ground Pin 22, 25, 28
23, 24,
GR4 ~ GR1 O Grid Output Pins
26, 27,

V1.4 3 October 2009

 PT6964

INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below.

INPUT PINS: CLK, STB INPUT PINS: K1 TO K2

OUTPUT PINS: GR1 TO GR4 OUTPUT PINS: SG1/KS1 TO SG10/KS10

OUTPUT PINS: SG14/GR5, SG13/GR6 AND INPUT PIN & OUTPUT PIN: DI/O
SG12/GR7

V1.4 4 October 2009

 PT6964

FUNCTION DESCRIPTION
COMMANDS
A command is the first byte (b0 to b7) inputted to PT6964 via the DI/O Pin after STB Pin has changed from HIGH to
LOW State. If for some reason the STB Pin is set to HIGH while data or commands are being transmitted, the serial
communication is initialized, and the data/commands being transmitted are considered invalid.

COMMANDS 1: DISPLAY MODE SETTING COMMANDS

PT6964 provides 4 display mode settings as shown in the diagram below: As stated earlier a command is the first one
byte (b0 to b7) transmitted to PT6964 via the DI/O Pin when STB is LOW. However, for these commands, the bit 3 to bit
6 (b2 to b5) are ignored, bit 7 & bit 8 (b6 to b7) are given a value of 0.

The Display Mode Setting Commands determine the number of segments and grids to be used (10 to 13 segments, 7 to
4 grids). A display command ON must be executed in order to resume display. If the same mode setting is selected, no
command execution is take place, therefore, nothing happens.

When Power is turned ON, the 7-grid, 10-segment modes is selected.

MSB LSB
0 0 - - - - b1 b0

Not Relevant Display mode settings:

00: 4 digits, 13 segments
01: 5 digits, 12 segments
10: 6 digits, 11 segments
11: 7 digits, 10 segments

COMMANDS 2: DATA SETTING COMMANDS

The Data Setting Commands executes the Data Write or Data Read Modes for PT6964. The data Setting Command, the
bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of 1 while bit 8 (b7) is given the value of 0. Please refer to
the diagram below.

When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of 0.

MSB LSB
0 1 - - b3 b2 b1 b0

Not Relevant Data write & read mode settings:

00: Write data to display mode
10: Read key data

Address increment mode settings (Display mode):

0: Increment address after data has been written
1: Fixed address
Mode settings:
0: Normal operation mode
1: Test mode

V1.4 5 October 2009

 PT6964
PT6964 KEY MATRIX & KEY INPUT DATA STORAGE RAM
PT6964 Key Matrix consists of 10 x 2 array as shown below:

Each data entered by each key is stored as follows and read by a READ Command, starting from the last significant bit.
When the most significant bit of the data (b7) has been read, the least significant bit of the next data (b0) is read.
K1……………………...K2 K1………………………K2
SG1/KS1 SG2/KS2 x
SG3/KS3 SG4/KS4 x
Reading
SG5/KS5 SG6/KS6 x
Sequence
SG7/KS7 SG8/KS8 x
SG9/KS9 SG10/KS10 x
b0………………………b1 b3………………………..b4 b6………………………b7
Note: b6 and b7 do not care.

COMMANDS 3: ADDRESS SETTING COMMANDS

Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has
a value of 00H to 0DH. If the address is set to 0EH or higher, the data is ignored until a valid address is set. When power
is turned ON, the address is set at 00H.

Please refer to the diagram below.

MSB LSB
1 1 - - b3 b2 b1 b0

Not relevant Address: 00H to 0DH

DISPLAY MODE AND RAM ADDRESS

Data transmitted from an external device to PT6964 via the serial interface are stored in the Display RAM and are
assigned addresses. The RAM addresses of PT6964 are given below in 8 bits unit.

SG1 SG4 SG5 SG8 SG9 SG10 X SG12 SG13 SG14

00HL 00HU 01HL - 01HU DIG1
02HL 02HU 03HL - 03HU DIG2
04HL 04HU 05HL - 05HU DIG3
06HL 06HU 07HL - 07HU DIG4
08HL 08HU 09HL - 09HU DIG5
0AHL 0AHU 0BHL - 0BHU DIG6
0CHL 0CHU 0DHL - 0DHU DIG7

b0 b3 b4 b7
xxHL xxHU
Lower 4 bits Higher 4 bits
Note: X = Not relevant

V1.4 6 October 2009

 PT6964

COMMAND 4: DISPLAY CONTROL COMMANDS

The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to
the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the
key scanning is started).

MSB LSB
1 0 - - b3 b2 b1 b0

Not relevant Dimming quantity settings:

000: Pulse width=1/16
001: Pulse width=2/16
010: Pulse width=4/16
011: Pulse width=10/16
100: Pulse width=11/16
101: Pulse width=12/16
110: Pulse width=13/16
111: Pulse width=14/16

Display settings:
0: Display off (Key scan continues)
1: Display on

SCANNING AND DISPLAY TIMING

V1.4 7 October 2009

 PT6964

SERIAL COMMUNICATION FORMAT

The following diagram shows the PT6964 serial communication format. The DI/O Pin is an N-channel, open-drain output
pin, therefore, it is highly recommended that an external pull-up resistor (1KΩ to 10KΩ) must be connected to DI/O.

RECEPTION (DATA/COMMAND WRITE)

TRANSMISSION (DATA READ)

where: twait (waiting time) ≥ 1µs

It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the
command and the falling of the first clock that has read the data is greater or equal to 1µs.

V1.4 8 October 2009

 PT6964

SWITCHING CHARACTERISTIC WAVEFORM

PT6964 Switching Characteristics Waveform is given below.

where:
fosc = Oscillation Frequency PWCLK (Clock Pulse Width) ≥ 400ns
PWSTB (Strobe Pulse Width) ≥ 1µs tCLK-STB (Clock - Strobe Time) ≥ 1µs
tsetup (Data Setup Time) ≥ 100ns thold (Data Hold Time) ≥ 100ns
t TZH (Segment Rise Time) ≤ 1µs t THZ (Segment Fall Time) ≤ 10µs
tTZL (Grid Fall Time) ≤ 1µs tTLZ (Grid Rise Time) ≤ 10 µs
tPZL (Propagation Delay Time) ≤ 100ns tPLZ (Propagation Delay Time) ≤ 300ns

Note:
Test Condition Under
tTHZ (Pull low resistor=10KΩ, Loading capacitor=300pF)
tTLZ (Pull high resistor=10KΩ, Loading capacitor=300pF)

V1.4 9 October 2009

 PT6964

APPLICATIONS
Display memory is updated by incrementing addresses. Please refer to the following diagram.

where:
Command 1: Display mode setting command
Command 2: Data setting command
Command 3: Address setting command
Data 1 to n: Transfer display data (14 bytes max.)
Command 4: Display control command

The following diagram shows the waveforms when updating specific addresses.

where:
Command 2: Data setting command
Command 3: Address setting command
Data: Data display data

V1.4 10 October 2009

 PT6964

RECOMMENDED SOFTWARE FLOWCHART

Notes:
1. Command 1: Display Mode Commands
2. Command 2: Data Setting Commands
3. Command 3: Address Setting Commands
4. Command 4: Display Control Commands
5. When IC power is applied for the first time, the content of the Display RAM is not defined; thus, it is strongly suggested that the contents of the Display
RAM be cleared during the initial setting.

V1.4 11 October 2009

 PT6964

SOP 28 (300MIL) THERMAL PERFORMANCE IN STILL AIR

JUNCTION TEMPERATURE: 100℃

V1.4 12 October 2009

 PT6964

ABSOLUTE MAXIMUM RATING

(Unless otherwise stated, Ta=25℃, GND=0V)
Parameter Symbol Rating Unit
Supply voltage VDD -0.3 to +7 V
Logic input voltage VI -0.3 to VDD+0.3 V
IOLGR +200 mA
Driver output current
IOHSG -50 mA
Maximum driver output current/total ITOTAL 400 mA
Operating temperature Topr -40 ~ +85 ℃
Storage temperature Tstg -65 ~ +150 ℃

RECOMMENDED OPERATING RANGE

(Unless otherwise stated, Ta=25℃, GND=0V)
Parameter Symbol Min. Typ. Max. Unit
Logic supply voltage VDD 4.5 5 5.5 V
Dynamic current (see Note) IDDdyn - - 5 mA
High-level input voltage VIH 0.8VDD - VDD V
Low-level input voltage VIL 0 - 0.3VDD V
Note: Test Condition: Set Display Control Commands=80H (Display Turn OFF State & under no load)

ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD=5V, GND=0V, Ta=25℃)
Parameter Symbol Test Condition Min. Typ. Max. Unit
VO=VDD-2V
IOHSG(1) SG1/KS1 to SG10/KS10, -20 -25 -40 mA
SG12/GR7 to SG14/GR5
High-level output current
VO=VDD-3V
IOHSG(2) SG1/KS1 to SG10/KS10, -25 -30 -50 mA
SG12/GR7 to SG14/GR5
VO=0.3V
Low-level output current IOLGR GR1 to GR4 100 140 - mA
SG14/GR5 to SG12/GR7
Low-level output current IOLDI/O VO=0.4V 4 - - mA
VO=VDD-3V
Segment high-level output current
ITOLSG SG1/KS1 to SG10/KS10, - - ±5 %
tolerance
SG12/GR7 to SG14/GR5
High-level input voltage VIH - 0.8VDD - 5 V
Low-level input voltage VIL - 0 - 0.3VDD V
Oscillation frequency fosc R=51KΩ 350 500 650 KHz
K1 to K3 pull down resistor RKN K1 to K2; VDD=5V 40 - 100 KΩ

V1.4 13 October 2009

 PT6964

PACKAGE INFORMATION
28 PINS, SOP, 300MIL

Symbol Min. Nom. Max.

A - - 2.65
A1 - - 0.30
b 0.31 - 0.51
c 0.20 - 0.33
D 17.90 BSC
E 10.30 BSC
E1 7.50 BSC
e 1.27 BSC
L 0.38 - 1.27
θ 0° - 8°
Notes:
1. All controlling dimensions are in millimeters.
2. Refer to JEDEC MS-012AE

V1.4 14 October 2009

 PT6964

IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.

Princeton Technology Corp.

2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw

V1.4 15 October 2009