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Experiment 4

The document describes an experiment to implement an 8x3 encoder and 3x8 decoder circuit in VHDL using the Xilinx tool. It includes the truth tables, circuit diagrams, VHDL code for the encoder and decoder using structural and behavioral modeling, respectively. It also includes the test benches and simulation results. The synthesis report shows that the encoder uses 1 slice and the decoder uses 5 slices out of 768 available on the FPGA board. Both the encoder and decoder have a delay of approximately 7 ns.

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Himanshu Rajan jain
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© © All Rights Reserved
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65 views

Experiment 4

The document describes an experiment to implement an 8x3 encoder and 3x8 decoder circuit in VHDL using the Xilinx tool. It includes the truth tables, circuit diagrams, VHDL code for the encoder and decoder using structural and behavioral modeling, respectively. It also includes the test benches and simulation results. The synthesis report shows that the encoder uses 1 slice and the decoder uses 5 slices out of 768 available on the FPGA board. Both the encoder and decoder have a delay of approximately 7 ns.

Uploaded by

Himanshu Rajan jain
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment-4

Aim:-implement VHDL code for 8x3 encoder and decoder circuit using Xilinx tool.
Software Used:-Xilinx 12.1,ISim Simulator.
Activity1:-Write a VHDL code for 8x3 encoder circuit using structural modeling.
Truth Table:

Circuit Diagram:

VHDL CODE(Implementation):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder8X3 is
Port ( d0,d1,d2,d3,d4,d5,d6,d7 : in STD_LOGIC;
y0,y1,y2 : out STD_LOGIC;
e : in STD_LOGIC);
end encoder8X3;
architecture Behavioral of encoder8X3 is
begin
y0<=(e AND d1) OR(e AND d3) OR(e AND d5) OR(e AND d7) ;
y1<=(e AND d2) OR(e AND d3) OR(e AND d6) OR(e AND d7) ;
y2<=(e AND d4) OR(e AND d5) OR(e AND d6) OR(e AND d7) ;
end Behavioral;

Synthesis Report:-
Number of Slices: 2 out of 768 0%
Delay: 7.850ns (Levels of Logic = 3)
Schematic Diagram:-

VHDL CODE(Test Bench):-


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY encoder_tb IS
END encoder_tb;
ARCHITECTURE behavior OF encoder_tb IS
COMPONENT encoder 8x3
PORT(
d0 : IN std_logic;
d1 : IN std_logic;
d2 : IN std_logic;
d3 : IN std_logic;
d4 : IN std_logic;
d5 : IN std_logic;
d6 : IN std_logic;
d7 : IN std_logic;
q0 : OUT std_logic;
q1 : OUT std_logic;
q2 : OUT std_logic
);
END COMPONENT;
signal d0 : std_logic := '0';
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';
signal d3 : std_logic := '0';
signal d4 : std_logic := '0';
signal d5 : std_logic := '0';
signal d6 : std_logic := '0';
signal d7 : std_logic := '0';
signal q0 : std_logic;
signal q1 : std_logic;
signal q2 : std_logic;
BEGIN
uut: encoder 8x3 PORT MAP (
d0 => d0,
d1 => d1,
d2 => d2,
d3 => d3,
d4 => d4,
d5 => d5,
d6 => d6,
d7 => d7,
q0 => q0,
q1 => q1,
q2 => q2
);
stim_proc: process
begin
d7<='0';d6<='0';d5<='0';d4<='0';d3<='0';d2<='0';d1<='0';d0<='1';
wait for 100 ns;
d7<='0';d6<='0';d5<='0';d4<='0';d3<='0';d2<='0';d1<='1';d0<='0';
wait for 100 ns;
d7<='0';d6<='0';d5<='0';d4<='0';d3<='0';d2<='1';d1<='0';d0<='0';
wait for 100 ns;
d7<='0';d6<='0';d5<='0';d4<='0';d3<='1';d2<='0';d1<='0';d0<='0';
wait for 100 ns;
d7<='0';d6<='0';d5<='0';d4<='1';d3<='0';d2<='0';d1<='0';d0<='0';
wait for 100 ns;
d7<='0';d6<='0';d5<='1';d4<='0';d3<='0';d2<='0';d1<='0';d0<='0';
wait for 100 ns;
d7<='0';d6<='1';d5<='0';d4<='0';d3<='0';d2<='0';d1<='0';d0<='0';
wait for 100 ns;
d7<='1';d6<='0';d5<='0';d4<='0';d3<='0';d2<='0';d1<='0';d0<='0';
wait;
end process;
END;
Simulation Result:-

Activity2:-Write a VHDL code for 3x8 decoder circuit using Behavioral Modeling.
Truth Table:-
Circuit Diagram:-

VHDL CODE(Implementation):-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decode_beh is
Port ( a2,a1,a0 : in STD_LOGIC;
d7,d6,d5,d4,d3,d2,d1,d0 : out STD_LOGIC);
end decode_beh;
architecture Behavioral of decode_beh is
begin
process(a2,a1,a0)
begin
if(a2='0' and a1='0' and a0='0') then
d7<='0';d6<='0';d5<='0';d4<='0';d3<='0';d2<='0';d1<='0';d0<='1';
elsif(a2='0' and a1='0' and a0='1') then
d7<='0';d6<='0';d5<='0';d4<='0';d3<='0';d2<='0';d1<='1';d0<='0';
elsif(a2='0' and a1='1' and a0='0') then
d7<='0';d6<='0';d5<='0';d4<='0';d3<='0';d2<='1';d1<='0';d0<='0';
elsif(a2='0' and a1='1' and a0='1') then
d7<='0';d6<='0';d5<='0';d4<='0';d3<='1';d2<='0';d1<='0';d0<='0';
elsif(a2='1' and a1='0' and a0='0') then
d7<='0';d6<='0';d5<='0';d4<='1';d3<='0';d2<='0';d1<='0';d0<='0';
elsif(a2='1' and a1='0' and a0='1') then
d7<='0';d6<='0';d5<='1';d4<='0';d3<='0';d2<='0';d1<='0';d0<='0';
elsif(a2='1' and a1='1' and a0='0') then
d7<='0';d6<='1';d5<='0';d4<='0';d3<='0';d2<='0';d1<='0';d0<='0';
else
d7<='1';d6<='0';d5<='0';d4<='0';d3<='0';d2<='0';d1<='0';d0<='0';
end if;
end process;
end Behavioral;
Schematic Diagram:-

VHDL CODE(Test Bench):-


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decoder_tb IS
END decoder_tb;
ARCHITECTURE behavior OF decoder_tb IS
COMPONENT decoder_beh
PORT(
a2 : IN std_logic;
a1 : IN std_logic;
a0 : IN std_logic;
d7 : OUT std_logic;
d6 : OUT std_logic;
d5 : OUT std_logic;
d4 : OUT std_logic;
d3 : OUT std_logic;
d2 : OUT std_logic;
d1 : OUT std_logic;
d0 : OUT std_logic
);
END COMPONENT;
signal a2 : std_logic := '0';
signal a1 : std_logic := '0';
signal a0 : std_logic := '0';
signal d7 : std_logic;
signal d6 : std_logic;
signal d5 : std_logic;
signal d4 : std_logic;
signal d3 : std_logic;
signal d2 : std_logic;
signal d1 : std_logic;
signal d0 : std_logic;
BEGIN
uut: decoder_beh PORT MAP (
a2 => a2,
a1 => a1,
a0 => a0,
d7 => d7,
d6 => d6,
d5 => d5,
d4 => d4,
d3 => d3,
d2 => d2,
d1 => d1,
d0 => d0
);
stim_proc: process
begin
a2<='0';a1<='0';a0<='0';
wait for 100 ns;
a2<='0';a1<='0';a0<='1';
wait for 100 ns;
a2<='0';a1<='1';a0<='0';
wait for 100 ns;
a2<='0';a1<='1';a0<='1';
wait for 100 ns;
a2<='1';a1<='0';a0<='0';
wait for 100 ns;
a2<='1';a1<='0';a0<='1';
wait for 100 ns;
a2<='1';a1<='1';a0<='0';
wait for 100 ns;
a2<='1';a1<='1';a0<='1';
wait;
end process;
END;
Simulation Result:-

Synthesis Report:-

decoder encoder
Number of Slices: 5 out of 768
0% Number of Slices: 1 out of 768
Number of 4 input LUTs: 8 out of 0%
1536 0% Number of 4 input LUTs: 2 out of
Number of bonded IOBs: 11 out of 1536 0%
97 11% Number of bonded IOBs: 5 out of
97 5%

Conclusion:- in 8x3 encoder and decoder Number of Slices: 1 out of 768 0% and in
decoder Delay: 7.622ns (Levels of Logic = 3)and in encoder delay is 7.340ns
(Levels of Logic = 3)

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