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Digital System Design Lab 7

This lab document outlines tasks for students to design and implement an arithmetic logic unit (ALU) using data flow modeling on an FPGA. The tasks include: 1) implementing a Boolean function, 2) designing a 1-bit full adder, 3) designing a 4-bit ripple-bit full adder, 4) designing a two to four line decoder, and 5) designing a four to one multiplexer. The main design problem is to create an ALU that performs addition, subtraction, multiplication, or division on two 6-bit operands depending on a 2-bit control signal provided by the user.

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ziafat shehzad
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79 views

Digital System Design Lab 7

This lab document outlines tasks for students to design and implement an arithmetic logic unit (ALU) using data flow modeling on an FPGA. The tasks include: 1) implementing a Boolean function, 2) designing a 1-bit full adder, 3) designing a 4-bit ripple-bit full adder, 4) designing a two to four line decoder, and 5) designing a four to one multiplexer. The main design problem is to create an ALU that performs addition, subtraction, multiplication, or division on two 6-bit operands depending on a 2-bit control signal provided by the user.

Uploaded by

ziafat shehzad
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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DIGITAL SYSTEM DESIGN LAB 7

DESIGN AND IMPLEMENTATION OF ARITHIMATIC LOGIC UNIT USING


DATA FLOW MODELLING

Objectives:
On successful completion of this lab, students will be able to:
a. Design of arithmetic logic unit able to perform basic arithmetic operation.
b. Implementation of Multiplexer and Decoders.
c. Take multi bit inputs from user.

Task 1: Implement the Boolean function on FPGA using data flow modeling.

F=A`C+A`B+AB`C+BC

Task 2: Design and implement a bit full adder using data flow modeling.

Task 3: Design and implement a 4 bit full adder (Ripple bit adder) using data flow modeling.

Task 4: Design and implement a two to four line decoders.

Task 5: Design and implement four to one line multiplexer.

Design Problem: Design digital Arithmetic Logic Unit which perform the basic operations.
ALU takes two 6 bits operands from the user and perform addition between them when control
input from user is 00, perform subtraction when control signal is 01 and multiplication when 10.
If the control signal is 11 ALU should perform division. Implement the design on FPGA and show
the required output.

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