DIGITAL LOGIC DESIGN

VHDL Coding for FPGAs

Unit 6
FINITE STATE MACHINES (FSMs)
 Moore Machines
 Mealy Machines
 Algorithmic State Machine (ASM) charts

Daniel Llamocca
 FINITE STATE MACHINES (FSMs)
 Classification:
 Moore Machine: Outputs depend only on the current state of the
circuit.
 Mealy Machine: Outputs depend on the current state of the
circuit as well as the inputs of the circuit.
 The circuit must always start from an initial state. Thus, there should be
a ‘resetn’ signal. The figure depicts a generic state machine:
Only for Mealy Machine

Inputs Combinatorial Q (States) Combinatorial Outputs

Flip Flops
Circuit Circuit

clock

resetn
Daniel Llamocca
 FINITE STATE MACHINES (FSMs)
 VHDL Coding: There exist many different
styles. The style explained here considers two processes: one for
the state transitions, and another for the outputs.
 The first step is to have the state diagram ready. The coding
then just simply follows the state diagram.
 We need to define a custom user data type (e.g., “state”) to
represent the states
type state is (S1, S2, ... S10) – example with 10 states
signal y: state;

Then, we define a signal of type “state” (e.g. ‘y’). This signal

can only take values from S1 to S10.
 Two processes must be considered:
 One where state transitions occur on the clock edge.
 One where the outputs are defined based on the current
state and input signals.

Daniel Llamocca
 Example: 2-bit counter
 Moore-type FSM
 Count: 00  01  10  10  00 … 2-bit 2 Q
clock counter
library ieee;
use ieee.std_logic_1164.all; resetn
Custom datatype definition: ‘state’
entity my_2bitcounter is with 4 possible values: S1 to S4
port ( clock, resetn: in std_logic; resetn = '0'
Q: out std_logic_vector (1 downto 0)); S1 S2
end my_2bitcounter;
Q= 0 Q= 1
architecture bhv of my_2bitcounter is

type state is (S1,S2,S3,S4);

S4 S3
signal y: state; Definition of signal ‘y’
of type ‘state’. Q= 3 Q= 2
begin

Transitions: process (resetn, clock)

begin Process that
defines the
if resetn = '0' then -- asynchronous signal
state transitions
y <= S1; -- initial state
...
Daniel Llamocca
Example: 2-bit counter
...
elsif (clock'event and clock='1') then
case y is
Process that defines the
when S1 => y <= S2;
when S2 => y <= S3; state transitions.
when S3 => y <= S4; Note that the state
when S4 => y <= S1; transitions only occur on
end case; the rising clock edge
end if;
end process;
Note that the outputs only
Outputs: process (y)
depend on the current
begin
case y is
state, hence this is a Moore
when S1 => Q <= "00"; machine
when S2 => Q <= "01";
when S3 => Q <= "10"; Process that defines the
when S4 => Q <= "11"; outputs.
end case;
end process; Note that the output is not
end bhv; controlled by the clock
 my_2bitcounter.zip: edge, only by the current
my_2bitcounter.vhd, state
Daniel Llamocca tb_my_2bitcounter.vhd
 Example: BCD counter with
stop signal
 Moore-type FSM stop
BCD 4 Q
 If the ‘stop’ signal is asserted, the counter
clock
count stops. If ‘stop’ is not asserted,
the count continues. resetn

resetn = '0' stop=0 0 0 1

S1 S2 S3 S4

Q= 0 Q= 1 Q= 2 Q= 3
1

S10 S5
stop=1 1 1 0
Q= 9 Q= 4
0 1 1 1
S9 S8 S7 S6
1 0
Q= 8 Q= 7 Q= 6 Q= 5

1 0 0 0
Daniel Llamocca
 BCD Counter with stop signal
 VHDL code: Moore FSM
library ieee;
use ieee.std_logic_1164.all;

entity bcd_count is
port ( clock, resetn, stop: in std_logic;
Q: out std_logic_vector (3 downto 0));
end bcd_count;
Custom datatype definition: ‘state’
with 10 possible values: S1 to S10
architecture bhv of bcd_count is

type state is (S1,S2,S3,S4,S5,S6,S7,S8,S9,S10);

signal y: state; Definition of signal ‘y’ of type ‘state’.

begin

Transitions: process (resetn, clock, stop)

begin Process that
if resetn = '0' then -- asynchronous signal defines the
state transitions
y <= S1; -- initial state
...
Daniel Llamocca
...
elsif (clock'event and clock='1') then
case y is
when S1 => Note that the
if stop='1' then y<=S1; else y<=S2; end if; state transitions
when S2 => depend on the
if stop='1' then y<=S2; else y<=S3; end if; stop signal ‘stop’
when S3 =>
if stop='1' then y<=S3; else y<=S4; end if;
when S4 =>
if stop='1' then y<=S4; else y<=S5; end if;
when S5 =>
if stop='1' then y<=S5; else y<=S6; end if;
when S6 =>
if stop='1' then y<=S6; else y<=S7; end if; Process that
when S7 => defines the state
if stop='1' then y<=S7; else y<=S8; end if; transitions
when S8 =>
if stop='1' then y<=S8; else y<=S9; end if; Note that the
when S9 =>
state transitions
if stop='1' then y<=S9; else y<=S10; end if;
only occur on the
when S10 =>
if stop='1' then y<=S10; else y<=S1; end if; rising clock edge
end case;
end if;
end process;
...
Daniel Llamocca
 BCD Counter with stop signal
 VHDL code:
stop Q
... BCD
4

Outputs: process (y) clock counter

begin
resetn
case y is
when S1 => Q <= "0000"; Note that the outputs only
when S2 => Q <= "0001"; depend on the current state,
when S3 => Q <= "0010"; hence this is a Moore machine
when S4 => Q <= "0011";
when S5 => Q <= "0100"; Process that defines
when S6 => Q <= "0101"; the outputs
when S7 => Q <= "0110";
when S8 => Q <= "0111";
when S9 => Q <= "1000";
Note that the output is not
when S10 => Q <= "1001"; controlled by the rising clock
end case; edge, only by the current state.
end process;
end bhv;  bcd_count.zip:
bcd_count.vhd,
Daniel Llamocca tb_bcd_count.vhd
 Example: LED sequence
 Moore-type FSM
 Sequence: 0001100, 00111100, 01111110, 11100111,
11000011, 10000001.
 The FSM includes an enable that allows for state transitions.
 This FSM requires 6 states, i.e. 3 flip flops. The 6-bit output is
generated by a combinational circuit (decoder).
8
E E DO
00011000 00111100 01111110 11100111 11000011 10000001
resetn Finite State
Machine
clock

resetn = 0 E=0 E=0

S1 E=1 S2 E=1 S3
E=0 DO=00011000 DO=00111100 DO=01111110

 my_ledseq.zip:
E=1 E=1
my_ledseq.vhd,
S6 E=1 S5 E=1 S4 tb_my_ledseq.vhd
DO=10000001 DO=11000011 DO=11100111

E=0 E=0 E=0

Daniel Llamocca
 Example: Sequence detector
with overlap
 Mealy-type FSM x
Detector z
 It detects the sequence 11010 clock '11010'

 State Diagram: 5 states

resetn
resetn = '0'
0/0 1/0

Notation: x/z
S1 S2
1/0
0/0 1/0

1/0 S3
0/1

0/0 0/0

S5 S4

1/0
Daniel Llamocca
 Example: Sequence detector
with overlap
 VHDL Code: Mealy FSM x
Detector z
library ieee; clock '11010'
use ieee.std_logic_1164.all;
resetn
entity my_seq_detect is
port ( clock, resetn, x: in std_logic;
z: out std_logic);
end my_seq_detect; Custom datatype definition: ‘state’
with 5 possible values: S1 to S5
architecture bhv of my_seq_detect is

type state is (S1,S2,S3,S4,S5);

signal y: state; Definition of signal ‘y’ of type ‘state’.

begin

Transitions: process (resetn, clock, x) Process that

begin defines the state
if resetn = '0' then -- asynchronous signal transitions
y <= S1; -- initial state
...
Daniel Llamocca
 Example: Sequence detector
with overlap
 VHDL Code: Mealy FSM x z
Detector
clock '11010'

...
elsif (clock'event and clock='1') then Note that the
case y is state transitions
when S1 =>
depend on the
if x = '1' then y<=S2; else y<=S1; end if;
input signal ‘x’
when S2 =>
if x = '1' then y<=S3; else y<=S1; end if;
when S3 =>
if x = '1' then y<=S3; else y<=S4; end if; Process that
when S4 => defines the state
if x = '1' then y<=S5; else y<=S1; end if; transitions
when S5 =>
if x = '1' then y<=S3; else y<=S1; end if;
end case; Note that the
end if; state transitions
end process; only occur on the
... rising clock edge

Daniel Llamocca
 Example: Sequence detector
with overlap
 VHDL Code: Mealy FSM x z
Detector
clock '11010'

...
Outputs: process (x,y)
begin Note that the output
depends on the
z <= '0';
current state and the
case y is
input ‘x’, hence this is
when S1 => a Mealy machine.
when S2 =>
when S3 =>
when S4 =>
Process that
when S5 =>
defines the
if x = '0' then z <= '1'; end if; outputs
end case;
end process;
end bhv;

 my_seq_detect.zip:
my_seq_detect.vhd,
Daniel Llamocca tb_my_seq_detect.vhd
 ALGORITHMIC STATE MACHINE
(ASMs) charts
 This is an efficient way to represent Finite State Machines.
 We use the 11010 detector as an example here.
resetn=0
x z S1
Detector
clock '11010'
0
x
resetn 1
S2
resetn = '0'
0/0 1/0
0
x
Notation: x/z
1
S1 S2 S3
1/0
0/0 1/0
1
x

1/0 S3 0
S4
0/1

0/0 0/0
0
x
S5 S4 1
S5
1/0

1 0
x z1

Daniel Llamocca