1.

Design a 4 to 1 MUX using Verilog HDL and verify using timing

diagram.

Code:
module lab1exp1 (
input in1, in2, in3, in4,
input [1:0] s,
output out);
assign out = s[1] ? (s[0] ? in4 : in3) : (s[0] ? in2 : in1);
endmodule

Output:

Discussion:
4 to 1 mux is about giving 4 inputs and in the output there will be one output.
We select the output by 2 selector bits. Here, s0 & s1 are two selectors.
s0=1,s1=1 then in4 has selected in output.

1. Design a priority encoder (3>1>0>2) using Verilog HDL and verify

using timing diagram
Code:
module lab1exp2(w,f);

input [3:0]w;
output reg[1:0]f;

always @(w)

casex (w)
4'b1xxx: f=3;
4'b0x1x: f=1;
4'b0x01: f=0;
4'b0100: f=2;

endcase
endmodule

Output:
Discussion:
Here we set the priority w3>w1>w0>w2. When w3=0,w1=1 then w2 & w0 will
be don’t care w1 will be selected for output. It will go like this for other inputs.

3. Design a 2 to 4 Decoder using Verilog HDL and verify using timing

diagram.

Code:
module lab1exp3 (
input i0, i1,
output [3:0] out );
assign out = i1 ? (i0 ? 8 : 4) : (i0 ? 2 : 1);
endmodule

Output:

Discussion:
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2^n
output lines. Here when we give an input that i0=0, i=0 then output=0. When
we give i0=1, i1=1 then output=1

4. Design a 4 bit adder-sub tractor using Verilog HDL and verify using
timing diagram.

Code:
module lab1exp4(A0,A1,A2,A3,B0,B1,B2,B3,S0,S1,S2,S3,C0,C4,S);
input A0, A1, A2, A3;
input B0, B1, B2, B3;
input C0;

output S0, S1, S2, S3;

output C4, S;

wire A0, A1, A2, A3;

wire B0, B1, B2, B3;
wire C0; wire S0, S1, S2, S3;
wire C4, S; wire C1, C2, C3;

assign X0 = C0^B0;
assign X1 = C0^B1;
assign X2 = C0^B2;
assign X3 = C0^B3;
assign S = C3^C4;
 fulladder Y0(C0,X0,A0,S0,C1);
fulladder Y1(C1,X1,A1,S1,C2);
fulladder Y2(C2,X2,A2,S2,C3);
fulladder Y3(C3,X3,A3,S3,C4);
endmodule

module fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign {cout,sum} = a+b+cin;
endmodule

Output:

Discussion:
Here we can add or subtract two number by using adder-sub tractor. In C0 & C4
we save the carry which used to add with the next bit.
5. 1 to 4 Demultiplexer :
Code:
module lab2exp1 (in, s0, s1, o0, o1, o2, o3);

output o0, o1, o2, o3;

input in;
input s0;
input s1;

assign o0 = in & (~s0) & (~s1);

assign o1 = in & (~s0) & s1;
assign o2 = in & s0 & (~s1);
assign o3 = in & s0 & s1;

endmodule

Output:
Discussion:
A Demultiplexer is a process of taking information from one input and transmitting
over one of many outputs. Here input is high and when we give select line s0=0 &
s1=0 then output o0=1. Again s0=1 & s1=0 then o1=1.

6 Up-Down Counter:

Code:
module lab2exp2 ( clk, up, out);
input clk, up;
output[3:0] out;
reg [3:0]
out = 4'b0000;

always @(posedge clk)

if(up)
 begin
out = out + 4'b0001;
end
else
begin
out = out - 4'b0001;
end
endmodule

Output:

Discussion:
A counter is a device which can count any particular event on the basis of how
many times the particular event(s) is occurred. Here when we give up value then
the input has passed to the output.

3. Ring Counter:

Code:
module lab2exp3 (out, clk, clr);

input clk, clr;

output [3:0] out;
reg [3:0] out_t;

always @(posedge clk)

if(clr==1)
out_t <= 4'b1000;
else
begin
out_t[3] <= out_t[0];
out_t[2] <= out_t[3];
out_t[1] <= out_t[2];
out_t[0] <= out_t[1];
end
assign
out = out_t;
endmodule

Output:
Discussion:
Ring counter, a type of counter in which the output of the last flip-flop is
connected as an input to the first flip-flop is known as a Ring counter. The input is
shifted between the flip-flops in a ring shape which is why it is known as a Ring
counter.

4. Johnson Counter:

Code:
module lab2exp4(clk, clr, out);

input clk, clr;

output [3:0] out;
reg [3:0] out_t;
always @(posedge(clk) or posedge(clr))
begin
if(clr == 1'b1)
begin out_t = 4'b0000;
 end
else if(clk == 1'b1)
begin out_t = {out_t[2:0],~out_t[3]};
end
end

assign out = out_t;

endmodule

Output:

Discussion:
In other words, feedback from the last flip-flop is fed inversely to the data input of
the first flip-flop. For example, for a D Flip-Flop shift register, the ~Q output of the
last flip-flop is fed to the D input of the first flip-flop. These can be used as Divide
by n counters as well.

1. A sequential circuit has two inputs, w1 and w2, and an output, z. Its
function is to compare the input sequences on the two inputs. If w1 = w2
during any four consecutive clock cycles, the circuit produces z = 1; otherwise,
z = 0. For example
 w1 : 0 1 1 0 1 1 1 0 0 0 1 1 0
w2 : 1 1 1 0 1 0 1 0 0 0 1 1 1
z: 0000100001110
Code:
module lab3exp1 (Clock, Resetn, w1,w2, z);

input Clock, Resetn, w1,w2;

output reg z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C=2'b10, D=2'b11;
assign w = w1^w2;
// Define the next state and output combinational circuits
always @(w, y)
case (y)

A: if (w)
begin
z = 0;
Y = A;
end
else
begin
z = 0;
Y = B;
end
B: if (w)
begin
z = 0;
Y = A;
end
else
begin
z = 0;
Y = C;
end

C: if (w)
begin
z = 0;
Y = A;
end
else
begin
z = 0;
Y = D;
end

D: if (w)
begin
 z = 0;
Y = A;
end
else
begin
z = 1;
Y = D;
end
default: begin z=1'bx; Y=3'bxxx;
end
endcase
// Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y <= A;
else y <= Y;
endmodule

Output:
Discussion:
Here we give 4 same input then output will be high. Otherwise it will be 0.

2. An FSM is defined by the state-assigned table in Figure:

Code:
module lab3exp2 (Clock, Resetn, w, z);
input Clock, Resetn, w;
output reg z;
reg [1:0]y, Y;
parameter [1:0] S0 = 0, S1 = 1, S2 = 2, S3 = 3;
always @(w, y)
case (y)
S0: if (w)
begin
z = 0;
Y = S3;
end
else
begin
z = 0;
Y = S2;
end

S1: if (w)
begin z = 0;
Y = S0;
end
else
begin
z = 0;
Y = S1;
end

S2: if (w)
begin z = 0; Y = S0;
end
else
begin
z = 0;
Y = S3;
 end

S3: if (w)
begin
z = 1;
Y = S1;
end
else
begin
z = 1;
Y = S1;
end
default:
begin z=1'bx; Y=3'bxxx;
end

endcase
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y <= S0;
else y <= Y;
endmodule

Output:
Discussion:
Here if we get two same input in a row then the output will be 1. Otherwise it will
be 0.