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Assignment#2 Solution

The document describes the pipeline stages for several instructions in a 5-stage pipeline processor. It provides the values of registers and variables for instructions in each stage of the pipeline. In the 8th cycle: Instruction 7 is in the IF/ID stage; Instruction 6 is in the ID/EXE stage with values of registers Rs and Rt; Instruction 5 is in the EXE/MEM stage with the program counter value and result of the ALU. The MEM/WB stage contains values from Instruction 4.

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62 views

Assignment#2 Solution

The document describes the pipeline stages for several instructions in a 5-stage pipeline processor. It provides the values of registers and variables for instructions in each stage of the pipeline. In the 8th cycle: Instruction 7 is in the IF/ID stage; Instruction 6 is in the ID/EXE stage with values of registers Rs and Rt; Instruction 5 is in the EXE/MEM stage with the program counter value and result of the ALU. The MEM/WB stage contains values from Instruction 4.

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Q1

(a)(3)
I1 -> 5 cycles

2 stalls -> 2 cycles

I2 -> 1 cycle

I3 -> 1 cycle

I4 -> 1 cycle

I5 -> 1 cycle

I6 -> 1 cycle

2 stalls -> 2 cycles

I7 -> 1 cycle

1 stall (can be ignore for single iteration)

Total 16 cycles. 16*300 = 4800ps = 4.8ns

(Single Iteration) Total 15 cycles. 15*300 = 4500ps = 4.5ns

(b)(3)
I1 -> 5 cycles

1 stall -> 1 cycle

I2 -> 1 cycle

I3 -> 1 cycle

I4 -> 1 cycle

I5 -> 1 cycle

I6 -> 1 cycle

2 stalls -> 2 cycles

I7 -> 1 cycle

1 stall (can be ignore for single iteration)


Total 15 cycles. 15*300 = 4500ps = 4.5ns

(Single Iteration) Total 14 cycles. 14*300 = 4200ps = 4.2ns

(c)(3)
I1 -> 5 cycles

1 stall -> 1 cycle

I2 -> 1 cycle

I3 -> 1 cycle

I4 -> 1 cycle

I5 -> 1 cycle

I6 -> 1 cycle

1 stall -> 1 cycle

I7 -> 1 cycle

1 stall (can be ignore for single iteration)

Total 14 cycles. 14*300 = 4200ps = 4.2ns

(Single Iteration) Total 13 cycles. 13*300 = 3900ps = 3.9ns

(d)(6)
ld R2, 20 (R6)

add R4, R1, R3

addi R2, R2, 4

addi R6, R6, 4

addi R5, R6, 4

bne R6, R7, Loop

sw R2, 26 (R6)

No stall required after rescheduling and changing immediate values


Q2
Let’s assume there are total 100 instructions.

For X(3)
30 Integer Instructions take = 30*2 = 60 cycles

40 Memory Instructions take = 40*3 = 120 cycles

30 F.P. Instructions take = 30*5 = 150 cycles

Total Cycles = 330 cycles

Total Execution Time of X = Total Cycles/Clock Rate = 330/(3*10 9) = 1.1 * 10-7s

For Y (Option 1)(3)


30 Integer Instructions take = 30*2 = 60 cycles

40 Memory Instructions take = 40*4 = 160 cycles

30 F.P. Instructions take = 30*5 = 150 cycles

Total Cycles = 370 cycles

Total Execution Time of X = Total Cycles/Clock Rate = 370/(3.2*10 9) = 1.156 * 10-7s

Speed Up from X = (1.1 * 10-7)/( 1.156 * 10-7) = 0.95

For Y (Option 2)(3)


30 Integer Instructions take = 30*2 = 60 cycles

40 Memory Instructions take = 40*3 = 120 cycles

30 F.P. Instructions take = 30*4 = 120 cycles

Total Cycles = 300 cycles

Total Execution Time of X = Total Cycles/Clock Rate = 300/(2.5*10 9) = 1.2 * 10-7s

Speed Up from X = (1.1 * 10-7)/( 1.2 * 10-7) = 0.92

Processor Y should go for option 1 as it is 0.95/0.92 = 1.032 times faster than option 2
Q3

Q4
1) [1st Stage] MUX (20ps) + Instruction Memory (250ps) -> Ignore (Adder)
[2nd Stage] Register File (150ps) -> Ignore (Sign-Extension)
[3rd Stage] MUX (20ps) + ALU (120ps) -> Ignore (Shift-Left + Adder)
[5th Stage] MUX (20ps) + Register File (150ps)
Total = 270+150+140+170 = 730ps
Mux can be ignored in 1st and 5th stage
Total = 250+150+140+150 = 690ps

2) Maximum time taken by 1st Stage i.e. 270ps, so clock cycle time will be 270ps.
(If Mux ignored) Maximum time taken by 1st Stage i.e. 250ps, so clock cycle time will be 250ps.
3) Between branch and Memory instruction, memory instruction uses all 5 stages and load
instruction critical instruction determines the critical path. For Load,
1st Stage (270) + 2nd Stage (150) + 3rd Stage (140) + 4th Stage (250) + 5th Stage (170) = 980ps

4) Maximum time taken by 1st Stage i.e. 270ps, so clock cycle time will be 270ps.
Maximum time taken by 1st Stage i.e. 250ps, so clock cycle time will be 250ps.

5) Total Stages * Clock Cycle Time = 5 * 270ps = 1350ps


Total Stages * Clock Cycle Time = 5 * 250ps = 1250ps

Q5
a) (IF -> Inst. 7), (ID -> Inst. 6), (EXE -> Inst. 5), (MEM -> Inst. 4), (WB -> Inst. 3) (10)
b) 8th cycle values
IF/ID (1)
Variable Name Value
PC (Program counter value of the instruction 6) + 4
Inst. 6 from Inst. Memory addi R6, R6, 4
Instruction Bits (I-Type) 001000 00110 00110 0000000000000100

ID/EXE (Instruction 5 values) (3)


Variable Name Value
PC (Program counter value of the instruction 5) + 4
Rs (Read Data of Rs) 00110 (6)
Rt (Read Data of Rt) 00010 (2)
Instruction [bit 16-21] Same as Rt but of no use for this instruction 00010 (2)
Sign Extended Bit 30
Instruction [bit 15-11] 0
RegDest X
Branch 0
MemRead 0
MemWrite 1
RegWrite 0
MemToReg X
ALUSrc 1
ALUOp 00 (0)

EXE/MEM (Instruction 4 values) (3)


Variable Name Value
PC
Result of Adder PC (Program counter value of the instruction 4 + 4) + 8
(extended signed bit) * 4 = PC + 32
Result of ALU 8 + 6 = 14
Address for Data Reading 14 (Don’t care)
Memory Write Data Address 5 (Don’t care)
Zero 0
Destination Register 5 (R5)
Branch 0
MemRead 0
MemWrite 0
RegWrite 1
MemToReg 0

MEM/WB (Instruction 3 values) (3)


Variable Name Value
PC Src 0
Read Data from ALU result for 4
Address
ALU result for Address 4
RegWrite 1
MemToReg 0
IF/ID (1)
Variable Name Value
PC (Program counter value of the instruction 6) + 4
Inst. 7 from Inst. Memory bne R6, R26, Loop
Instruction Bits (I-Type) 000101 00110 11010 xxxxxxxxxxxxxxxx

ID/EXE (Instruction 6 values) (3)


Variable Name Value
PC (Program counter value of the instruction 5) + 4
Rs (Read Data of Rs) 00110 (6)
Rt Same as Rd but of no use for this instruction (6)
Instruction [bit 20-16] (Rd) 00110 (6)
Sign Extended Bit 4
Instruction [bit 15-11] 0
RegDest 0
Branch 0
MemRead 0
MemWrite 0
RegWrite 1
MemToReg 0
ALUSrc 1
ALUOp 00 (0)

EXE/MEM (Instruction 5 values) (3)


Variable Name Value
PC
Result of Adder PC (Program counter value of the instruction 4 + 4) + 30
(extended signed bit) * 4 = PC + 120
Result of ALU 6 + 30 = 36
Address for Data Reading 36
Memory Write Data Address 2
Zero 0
Destination Register x (either 6 or 0)
Branch 0
MemRead 0
MemWrite 1
RegWrite 0
MemToReg X

MEM/WB (Instruction 4 values) (3)


Variable Name Value
PC Src 0
Read Data from ALU result for 14
Address
ALU result for Address 14
RegWrite 1
MemToReg 0

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