TEST&MEASUREMENT

Programmable
Pulse Generator
simple hardware with lots of features
Design by B. Oehlerking

This pulse generator, which can be programmed using Visual Basic 5.0,
employs the simplest imaginable hardware but offers capabilities that are
usually found only in microprocessor controlled equipment.

The circuit presented here is a programmable The pulse frequency and pulse switch S1 (SPL) and potentiometer
pulse generator (PPG) that can be pro- length of the PPG are set using the P1 (PTL), as shown in Figure 1. It is
grammed via a serial interface. It has a fre- combination of switch S2 (SPF) and possible to program arbitrary pulse
quency range of 0.1 Hz to around 100 kHz. potentiometer P2 (PF) along with sequences, ranging in length from 1

60 Elektor Electronics 3/2001

 TEST&MEASUREMENT

+5V +5V +5V

C4
R5 +5V
S1

560Ω
C7
16 16 16 SPL 1µ
16 16
P1 C3 R7
IC1 IC2 100n
9 9 9

560Ω
RCR C RCR C RCR C
8 8
IC3 IC4 IC5 2M 1n
11 12 11 12 11 12 PL 2 1
SR IN SR OUT SR IN SR OUT SR IN SR OUT AP
6 4 6 4 6 4 RCX CX
IC6.C 10 SL IN SL OUT SL IN SL OUT SL IN SL OUT 4 6
3 3 3
CLK CLK CLK
≥1 R6 T4
IC1 = 4027 & 40100 40100 40100 5 IC2.A 7
4k7
IC2 = 4098 CI L/R C CI L/R C CI L/R C R
8 9 C9
IC6 = 4011 2 8 13 2 8 13 2 8 13 3 BC547
IC7 = 4093
1n

5 6
IC6.D 11 IC6.A 3
+5V
+5V UB
+5V
& +
& &
IC7.B 4
12 13 1 2 +5V
14 C8 14
IC6 IC7 R10 0 R9
IC6.B IC7.D 11 IC7.A 3

560Ω
1k
7 7 4 5
100n & &
& 6
AN
12 13 1 2
P2
PF
+5V 1M R8 T5
+5V 6k8
K1 S2
C10
C5 R2 BC547
1 SPF
10k
6 C1 C2 1n
R3 100n +5V
2 12
10k
R 470p 1µ
7 RTS 10 J 15
R1 R12
3 TxD 13 IC1.A R13 T3
C

33k
10k
8 CTS 11 14 10k
R4 K T2
4 DTR S AG
10k
9 D1 D2 D3 9 BC547C
5 T1 R14
R11 BC547C C6

1k
4V7 4V7 4V7 47k
100µ
BC547C
000200 - 11

Figure 1. Only a few standard logic ICs are needed for the hardware of the programmable pulse generator.

to 48 pulses, and the only involve- Operating principle the state of the CTS line. The High level at
ment of the PC CPU is to load new pin 15 of IC1a reaches the input of the shift
pulse patterns. The circuit is other- The software loads a specific pulse register chain (SR_IN) via gate IC6d and
wise fully independent. pattern into three 32-bit shift regis- inverter IC6c. The software now sets RTS
The following signals are present on ter ICs (IC3–IC5, type 40100). After briefly High and then switches it back to
the three outputs (AN, AG and AP): the pattern has been loaded, the Low. This produces a complete pulse on the
the programmed pulse sequence, a software enables a clock generator, clock line of the shift register, so that the High
DC voltage smoothed by a low-pass and the pulse sequence recirculates level at its input is transferred to the first
filter (dimming function) and a pulse through the shift registers, whose stage. Following this, pin 15 of IC1a must be
whose width can be set using a output is coupled back to the input. set Low by a suitable signal on the TxD line.
monostable multivibrator (MMV). To better understand how this A series of 95 zeroes is then clocked into the
The software, which has been gener- works, consider an example in which shift register by 95 clock pulses supplied via
ated using VB 5.0, consists of a BAS a single pulse is loaded and then the RTS line. This means that 95 stages of the
module and three Form modules. Two recirculates through the shift regis- shift register are Low, with the final stage
of the Form modules represent the ter chain. Once the PC and +5-V being High.
pulse generator and a user interface supply voltage have been switched Up to now, the DTR signal has remained Low
for testing, while the third Form mod- on and the serial interface cable has and thus held the voltage at the AN and AG
ule indicates whether the interface been connected, the DTR signal lies outputs at zero (via T1 and T2). Pin 15 of IC1a
connector is properly connected and at a low voltage, which disables the is now set High via the TxD line, and then the
the correct operating voltage is pre- oscillator circuit formed by IC7a, P2, clock generator is enabled by setting DTR
sent. The BAS module contains pro- R10, C1 and C2. Pin 2 of gate IC6a is High. This allows a single pulse to recirculate
cedures and functions that are useful then High. Since the RTS line also through the shift register chain via gates
for putting together a graphical user supplies a Low level, the common IC7b, IC6b, IC6d and IC6c. This can all be
interface. The processing speed of the clock line for the shift register clearly represented using a table or flow
PC affects only the loading of a new (IC3–IC5) is also held Low (pin 3). chart, as shown in the text box.
pulse sequence, so it does not matter The software now sends pulses via Since the voltages provided by PC serial inter-
as far as the actual operation of the TxD until pin 15 of IC1a is set. This faces are usually greater than +5 V or nega-
circuit is concerned. is recognised by the software from tive, all of the inputs to the circuit (TxD, DTR

3/2001 Elektor Electronics 61

TEST&MEASUREMENT

+5 V). With other component types,

it might be possible to improve the
performance in this regard.

Graphical user interface

All 96 bits in
shift register
The software modules that have
are set already been mentioned include a
user interface for testing the finished
Tests
circuit (see Figure 2). This text win-
FF (IC1.A)
and
dow should be self-explanatory.
CTS line The main window of the PPG is
shown in Figure 3. This displays a
Set and clear
Automatically Dimmer individual configured pulse pattern in the Burst
opens first functions bits
free interface
window, above which the resulting
oscillogram can be seen. The upper
channel shows the pulse pattern,
000200- 12 while the lower channel shows a
monostable pulse sequence that has
been configured at the AP output of
Figure 2. The user interface of the test program, with comments. the circuit using potentiometer P2.
Pulse patterns can be simply
selected from the Burst window
and RTS) are protected by resistors and Zener upper frequency limit of the circuit is using the mouse and then loaded
diodes. The DCD line (pin 1) is used to show determined by the maximum clock into the hardware with ‘Start’. A
the user whether the interface is connected rate of the 40100 shift register IC, complete group of pulses can be
and the power supply is switched on. The which is specified to be 1 MHz (at selected by clicking on the group
with the left mouse button, dragging
the mouse to the right and then
clicking with the right mouse button.
Such a group can subsequently be
deleted by clicking on a pulse in the
group, moving the mouse to the left
MMV
output and then clicking with the right
mouse button.

Board layout
Digital
output Such an interesting piece of test and
measurement equipment certainly
deserves its own circuit board lay-
out. As can be seen in Figure 4, this
is an uncomplicated design with
plenty of space between the tracks
and the individual components.
Since the board is single sided, a few
(well, ten) wire bridges are unavoid-
Square able. You should start board assem-
wave
generator bly with these items, followed by the
low-profile components and then
(good) sockets for all ICs. Finally, fit
Predefined
pulse solder posts for AG, AN and AP and
distribution add the Sub-D connector and the
potentiometers. Then insert the ICs
Field for and check the orientations of all
loadable
pulse
polarised components. Before fitting
distribution the circuit board into an inexpensive
plastic enclosure, you should solder
000200 - 13
1-nF capacitors across R6 and R8 on
the bottom side of the circuit board.
Figure 3. The main window for the programmable pulse generator, with the associated After the board layout had already
oscillogram representation. been completed, it was found that

62 Elektor Electronics 3/2001

 TEST&MEASUREMENT

H1
000200-1
P2 C1
S2 C6 H2
Freeware!
The program and source code for the pro-

R14
AG
R10 grammable pulse generator are available free
IC6 IC7 T3
C8 of charge from the Free Downloads page of
K1 AN
C2
R11
the Elektor Electronics website at
T1 AP
http://www.elektor-electronics.co.uk. Look

R13
T5
for item 000200-11 under March 2001. You

R12
R8

R9
R3
R4

IC3 0 can also obtain the circuit board layout in

IC4

IC5
C10 + PDF format from the website. If you do not
C9 T2 have access to the Internet, you can obtain
R1

P1 the software from the Publishers’ Readers

R6 T4
D3
D1

1-002000 Services on two diskettes (order numbers

C7
D2 C4 000200-11a/b), as well as a blank circuit

R5
C5 board (order number 000200-1).

R7
R2 IC1 IC2
C3

H3
H4

S1

Programming
sequence
000200-1

1) Disable clock generator. DTR Low

2) Load 96 states:
0 IC1a Low, RTS = High–Low clock
1 IC1a HIgh, RTS = High–Low clock
3) Enable gate IC6d IC1a High
4) Enable IC6b and clock generator.
DTR High

COUNT = 0

Figure 4. A printed circuit board layout for the hardware. DTR = LOW oscillator stops

CTS
TxD = = HI HI to FF IC1.A
this measure has a beneficial effect assembly, use an oscilloscope to ?

on the performance at frequencies check the operation of the hardware

above 100 kHz. After completing the and software. (000200-1) RTS = HI

one clock pulse

RTS = LOW

COMPONENTS LIST Semiconductors:

D1,D2,D3 = 4V7, 500mW zener diode CTS
LOW to FF IC1.A
TxD = = LOW
Resistors: T1-T5 = BC547C ?

R1-R4,R13 = 10kΩ IC1 = 4027

R5,R7,R9 = 560Ω IC2 = 4098 RTS = HI

R6 = 4kΩ7 IC3,IC4,C5 = 40100

R8 = 6kΩ8 IC6 = 4011 loading 95 times
RTS = LOW
R10,R14 = 1kΩ IC7 = 4093 LOW

R11 = 47kΩ
R12 = 33kΩ Miscellaneous: COUNT ++

P1 = potentiometer, 2MΩ, linear law K1 = 9-way Sub-D socket (female),

P2 = potentiometer, 1MΩ, linear law PCB mount COUNT
S1,S2 = switch, 1 on/off contact = 95
?
Capacitors: 3 solder pins
C1 = 470pF Disk, project software, order code
CTS
C2,C4 = 1µF 000200-11a/b (see Readers Ser- TxD = = HI
?
C3 = 1nF vices page)
C5,C7,C8 = 100nF PCB, order code 000200-1 (see rotating
DTR = HI
C6 = 100µF 16V radial Readers Services page) 000200 - 14

3/2001 Elektor Electronics 63