Set - A

1. CONVERT THE FOLLOWING

i. 101010110.10011 = ___________9, ___16,H
ii. 726.58 = _______4, 2, H
iii. 67AD.EF = ___________2,8,7
2. PERFORM THE FOLLOWING
i. 1001101 – 1110011 using 1’s complement subtraction
ii. 1100011 – 10110011 using 2’s complement subtraction
iii. 93 – 65 using both 1’s and 2’s complement
iv. 57 - 99 using both 1’s and 2’s complement

3. Simplify the following using Boolean expression

 
i.  A  C  AD  A D  AC  C

ii. W X  X Y  YZ  W Z

iii. ab  bc  ca  a b  bc  c a

4. find the SOP for the following using K –Map

i. f(a,b,c,d) = ∑(0,2,3,4,7,8,14)
ii. f = ∏(0,2,4,6,8)∙D(1,12,9,15)
iii x' z  w' xy ' w( x' y  xy' )

5. A half adder is a circuit that adds two bits to give a sum and a carry. Give the truth table for a half
adder, and design the circuit using only two gates. Then design a circuit which will find the 2’s
complement of a 4-bit binary number. Use four half adders and any additional gates.

6. Design a Code converter to convert BCD to 8421 code.

7. Draw a state diagram for a Moore type state machine specified as follows:
- Denote "a" the initial state of the machine
- set the initial output to the initial input (the input is presented to the machine bit by bit)
- The output changes value only when three successive inputs have the same value and that value is
opposite to the current output. For example, if the current output is 1 and the machine detects three
consecutive 0 it changes the output to 0.
design the circuit using RS – FF and write the verilog HDL.
8. Design the 4 bit 7311 code to 53-1-1 code and write the Verilog HDL using case statement.
 SET – B

1. CONVERT THE FOLLOWING

i. 101011110.11101 = ___________9, ___16,H
ii. 467.238 = _______4, 2, H
iii. C49D.B7 = ___________2,8,7
2. PERFORM THE FOLLOWING
i. 1010101 – 1010011 using 1’s complement subtraction
ii. 1110001 – 10010111 using 2’s complement subtraction
iii. 87 – 55 using both 1’s and 2’s complement
iv. 23 - 91 using both 1’s and 2’s complement

3. Simplify the following using Boolean expression

i.[ x( xy)' ][ y( xy)' ]
ii.(ab  cd  e f )
iii.(a  c)(a  c)(a  b  cd )tofourliterals

4. find the SOP for the following using K – map

i. A' B' C ' D' BC' D  A' C ' D  A' BC  AD'
ii. f = ∏(1,3,5,9,11,12,14)
iii. f = ∑(0,1,2,5,7,8,10,15)

5. A flow rate sensing device used on a liquid transport pipeline functions as follows. The device
provides a 5-bit output where all five bits are zero if the flow rate is less than 10 gallons per minute. The
first bit is 1 if the flow rate is at least 10 gallons per minute; the first and second bits are 1 if the flow rate
is at least 20 gallons per minute; the first, second, and third bits are 1 if the flow rate is at least 30 gallons
per minute; and so on.The five bits, represented by the logical variables A, B, C, D, and E, are used as
inputs to a device that provides two outputs Y and Z.
(a) Write an equation for the output Y if we want Y to be 1 iff the flow rate is less than 30 gallons per
minute.
(b) Write an equation for the output Z if we want Z to be 1 iff the flow rate is at least 20 gallons per
minute but less than 50 gallons per minute.

6. Design a code converter to convert 84-1-2 to 5311 code.

7. Design a finite state machine (FSM) for a counter that counts through the 3-bit prime numbers
downwards. Assume the counter starts with initial prime value set to 010 as its first 3 bit prime number.
You need to provide the state transition table and the state transition diagram. Assume that the
state is stored in three D-FFs. Write the HDL code and simulate Hint: The set of all 3-bit prime
numbers includes 2, 3, 5 and7.
8. Gray codes have the useful property that consecutive numbers differ in only a single bit osition.
Design a 3-bit Gray code counter FSM with no inputs and three outputs. When reset, the output should
be 000. On each clock edge, the output should advance to the next Gray code. After reaching 100, it
should repeat with 000. Draw a schematic for this counter using T flip-flops.
 SET – C

1. Perform the following conversions

(i) (67.24)8 = ( ? )2
(ii) (11100.1001)2 = ( ? )16
(iii) (BC1.30)16 = ( ? )2
(iv) (10111.0111)2 = ( ? )8
2. Perform the following
(i) 1001100-110011 using 1’s complement subtraction
(ii) 93 – 14 using 1’s complement
(iii) 87 – 6 using 2’s complement

3. Simplify the following using Boolean expression

i.a ' bcd  a ' bc' d  b' ef  cde' g  a ' def  a ' b' ef ( reduced to sum of 3 terms)
ii.( x  y )( y  z )( x  z )  ( x' y ' )( y ' z ' )( x' z ' ) (give the algebraic proof)
iii. F = ∏(3,5,8,11)
4. A combinational circuit is divided into two subcircuits N1 and N2 as shown. The truth table for N1
is given. Assume that the input combinations ABC = 110 and ABC = 010 never occur. Change as
many of the values of D, E, and F to don’t-cares as you can without changing the value of the

output Z.
5. Find the minimum product of sums and sum of Product for
(a) F(a, b, c, d, e) =∑ m(1, 2, 3, 4, 5, 6, 25, 26, 27, 28, 29, 30, 31)
(b) F = M(1,4,5,8,10,13)
6. Design a home security system as follows. There are 3 input sensors called, e (enable), w
(window) and d (door). There is one output called s (alarm sound). After reset the system is
disarmed. The system stays in the disarmed state until e is pressed, when it will move to the armed
state. In this state, if e is pressed again the system will move back to the disarmed state. If
however, w or d sensors are sensed while the system is in the armed state, the system will activate
the alarm sound as follows. Signal s will be turned on for 500 clock cycles then it will shut down
for 300 clock cycles. This sequence will repeat itself until e becomes 1, in which case the system
returns to the disarmed state. Derive the data-path elements and the FSM in the control-path.
Write/simulate the Verilog code to verify the entire design.
7. An up-down mod-4 binary counter has a single input x, such that the it counts up if x=0 and counts
down if x=1:
Draw the Mealy state diagram of the circuit.
* Draw the state Moore diagram of the circuit.
* Implement both circuits using negative-edge triggered D-FFs.
 SET – D
1. Convert the following
i. (10111.0111)2 = ( ? )8
ii. (67.67)8 = ( ? )10
iii. (10110.0101)2 = ( ? )4
iv. (155)10 = ( ? )2
2. Perform the following
i. 1100011 – 1011011 using 1’s and 2’s complement subtraction
ii. 98 – 24 using 1’s complement
iii. 14 – 86 using 2’s complement
3. Simplify the following using Boolean expression
i. AB ( D  C D )  B ( A  ACD ) to one literal
ii. ABCD + A’B’C’D + A’BCD + AB’CD + A’B’CD + ABCD’
iii. F = ∏(2,4,5,7,8,10) , write the SOP
4. Simplify using K – Map
i. f = ∑(0,6,8,13,14)+d(2,4,10)
ii. (A’+B+D’)(A’+B’+C’)(A’+B’+C)(B’+C+D’)
iii. F(v, w, x, y, z) = ∑m(4, 5, 8, 9, 12, 13, 18, 20, 21, 22, 25, 28, 30, 31)
5. A combinational circuit has four inputs (A, B, C, D) and four outputs (W, X, Y, Z). WXYZ
represents an excess-3 coded number whose value equals the number of 1’s at the input. For
example, if ABCD = 1101, WXYZ = 0110.
(a) Find the minterm expansions for X, Y, and Z.
(b) Find the maxterm expansions for Y and Z.
6. Design a code converter to convert Excess – 1 Code to 8421 code.
7. Design a sequential circuit using RS - FFthat has 1 data input (w) and 1 data output (z). The
output z will become 1 if in the last 3 clock cycles the number of 1s on the input w has been
greater than 1. Draw the FSM diagram and write/simulate the Verilog code to verify it.
8. Design the 4 bit 2421 code to 53-1-1 code and write the Verilog HDL using case statement.
 SET – E
1. Convert the following
i. 1111111012 = _______4,10, H
ii. 8AF2.E9 = _________2, 8, 10
2. Perform the following
i. 11110011 – 1110011 using 1’s and 2’s complement subtraction
ii. 88 – 43 using 1’s complement
iii. 35 – 95 using 2’s complement
3. Reduce the combinational logic circuit in Fig. to a minimum form.

4. Simplify the following using Boolean algebra

i. f=m(1,2,4,7,10,12)
ii. f = M(0,3,4,8,9,12)
5. Identify each of the following expression as SOP, POS and its canonical form respectively
i. AB  ABD  AC D
ii. A ‘B’ + AB’ + C’ D’ + CD’
6. Evaluate the following expression
a. ( P  Q) R S  T  U
b. Simplify using K – map and give the SOP and POS
F = π(0,1,3,5,6,9,10,13,14)
7. Design an excess-3 code converter to drive a seven-segment indicator. The four inputs (A, B,
C, D) to the converter circuit represent an excess-3 digit. Input combinations representing the
numbers 0 through 9 should be displayed as decimal digits. The input combinations 0000,
0001, and 0010 should be interpreted as an error, and an “E” should be displayed. Assume that
the input combinations 1101, 1110, and 1111 will never occur. Design your circuit using only
two-, three-, and four input NOR gates and inverters. Any solution with 18 or fewer gates and
inverters (not counting the four inverters for the inputs) is acceptable.

8. Given the enclosed source code, draw the equivalent hardware circuit.
module setr(input logic clock,
output logic[7:0] f);
logic[7:0] a, b, c;
always_ff @(posedge clock)
begin
a <= b + c;
b = c + a;
 c = a + b;
end
assign f = c;
endmodule
9. Draw the Moore state diagram and state table for a serial even parity checker. The circuit
receives a word of 4-bits serially on its single input X and produces the even parity bit after
the fourth bit is received. The single output Z remains 0 except when the final (fourth) bit is
received and the total number of 1’s in the word is odd. The machine returns to the reset initial
state after the 4th input bit. Design the circuit using RS – FF and write the code using gate
level and dataflow.
 SET – F
1. Convert the following:
a. 10101001.110112 = ____3, _______8, __________16
b. 111011011G = _______________B
c. A25FE.DC8 = _______10,______7,______2
2. Subtraction using 1’s and 2’s complement
a. 673 – 76
b. 87 – 534
3. Simplify the following using Boolean law with minimum literals and implement using
Universal gates `
a. Y  A  AB  ( A  B)C  ( A  B  C )D
b. prove that A BC  A BC  ABC  ABC  A BC  A  B  C
4. Simplify the following Using K –map,
a. F = ∑(0,2,3,6,7)+d(8,12,15)
b. F = ∑(0,2, 8,10,14,16,18,19,24)+d(4,11,15,23,27,28)
5. Design a circuit which can convert BCD to 2421 code.
6. In an application 4 inputs A, B, C, D are available in true and complement Form .These
are fed at a logic circuit which operates a relay. The relay is ON for ABCD = 0000, 0010,
0101, 0110, 1101 and 1110. The states 1000 and 1001 don’t occur. For remaining states
the relay is OFF.
i. prepare truth table and minimize outputs F using K map
ii. Realize F using 3 input NAND gates.
7. Show that A  B  C  D = ∑(0,3,5,6,9,10,12,15)
8. Given the enclosed source code, draw the equivalent hardware circuit.
module setq(input logic clock,
output logic[7:0] f);
logic[7:0] a, b, c;
always_ff @(posedge clock)
begin
a = b + c;
b <= c + a;
c = a + b;
end
assign f = c;
endmodule
9. Draw a state diagram for a mealy type state machine specified as follows:

- Denote "a" the initial state of the machine

- set the initial output to the initial input (the input is presented to the machine bit by bit)
- The output changes value only when three successive inputs have the same value and that value is
opposite to the current output. For example, if the current output is 1 and the machine detects three
consecutive 0 it changes the output to 0.
design the circuit using T – FF and write the verilog HDL.
 SET – G
1. Convert the following
a. 11110010.1110012 = __________8,5,H
b. 32134 = __________2,10,8
c. 34D.EFF = _______4,2,O

2. Prove that:
a. A  B  AB  A  B
b. [(A+B)’ + (C+D)’]’ = (A+B)(C+D)

3. Design a Code converter to convert 4241 to excess 2 code using only NOR gates.
4. Do the following subtractions: (a) 1100 - 1001; (b) 101101 – 11010 using 1’s complement and 2’s
complement.
5. Simplify logic function using k – map minimization technique
Y( A , B , C, D) = ∑ m ( 0, 1, 3, 7, 8, 9,11,15)
b. Simplify the Boolean expression using four variables:
w’ z + x z + x’ y + w x’ z
6. Use algebraic techniques to determine whether or not the following Boolean equation is valid:

(abd  ab  bd  c)(c  ab  bd )  b(a  c)(a  c)  d (b  c)

7. I want to schedule a meeting among 6 individuals Alice, Brian, Charles, David, Elise and Frank.
The meeting must be scheduled so that the following rules are satisfied: • Exactly one of Alice and
Brian must be in the meeting. • Charles and David must be present in the meeting together. If
Charles is not available, David and Frank must be in the meeting together. However, all three of
Charles, David and Frank must not be present. • Elise is the manager of the group, so she must be
present in the meeting. Each of the 6 team members indicates to me their availability for the
meeting. I would like to construct a logic netlist with a single output g, such that g is equal to ′1 ′
whenever the meeting can be scheduled. (a) List the Boolean variables (b) Write down what both
values of each variable indicate. (c) Draw the circuit using logic gates. (d) implement the same
using only NOR gates
8. Given the enclosed source code, draw the equivalent hardware circuit.
module setp(input logic c1, c2, c3, a, b,
output logic f, g);
always_latch
begin
if (c1) begin
f = a;
g = b;
end else if (c2) begin
f = b;
end else if (c3) begin
g = a;
end
end
endmodule
9. Design a 1-bit decrementer (a circuit which subtracts 1). Give
(a) the arithmetic relationship between input and out put signals
(b) the truth table,
(c) logic diagram.
Design a logic diagram of a 1-bit increment/decrement circuit controled by an id signal (increment
when id = 1, decrement otherwise). Write the HDL.
And Design a block diagram of a 4-bit increment/decrement circuit. Use the above HDL and
concatenate.
 SET – H
1. Design a circuit that compares two binary numbers X and Y, each having two bits (X=x2x1;
Y=y2y1). It has a single output c which is supposed to be 1 when X > Y, and 0 otherwise. Do not
use adders/subtractors for this design; instead use a fundamental design process. Draw the
minimum sum-of-products circuit using the correct circuit symbols for all gates. Assume
complemented inputs are NOT available, but multiple input gates are. What is the delay of this
circuit, assuming the delay for each gate is d?
2. Consider a function f on three variables a, b and c. Suppose f is completely specified, and written
as
f  abc  abc  abc  abc  abc  abc
(a) Is the above expression a canonical SOP? If so, state why. If not, state why not.
(b) Construct a K-map for f
(c) Write down the prime implicants of f
(d) Write down a minimum SOP expression for f.
(e) If the input combination abc was a don’t care, then what write down the new prime
implicants of f. Also, write down a minimum SOP expression for f. What is the benefit of using
this minimum SOP for f over the one from part d)?
3. Convert the following
a. 12367.12310 = __________2,5,16
b. 11101001.101 = _________o,H,9
c. 654.128 = ______2,H
4. Using 1’s complement and 2’s complement do the following i.(-12-65), ii. 97 – 143
5. Consider the following circuit:

a. Give the algebraic expression of the function

b. Simplify the algebraic expression
c. Draw using only NAND gates
6. Find a minimum POS for the following
i. F(a,b,c,d,e) = m (4,5,8,9,12,13,18,20,21,22,25,28,30,31)
ii. F = M(9,10,4,7,2,8,13).d(0,2,15)
7. Design a code converter to convert 5311 to 24-2-1 code.
8. Design a serial subtractor with accumulator for 5-bit binary numbers. Assume that negative
numbers are represented by 2’s complement. Use a circuit of the form of Figure 18-1, except
implement a serial subtractor using a D-CE flip-flop and any kind of gates. Give the state
graph for the control circuit. Assume that St will remain 1 until the subtraction is complete,
and the circuit will not reset until St returns to 0.write the HDL using behavioural level.
9. Derive the state table and state diagram of the synchronous sequential circuit shown (X is an
input to the circuit). Explain the circuit function.
 SET – I
1. Find the complements for the following numbers:
a. (100111.1100)2 = _______8,9,H
b. (751.33)8 = _____4,9,2
c. (52,784,630)10 = _____2,8,H
2. Simplify each of the following expressions:
ABCD  ABCD  BEF  CDEG  ADEF  ABEF
(reduce to a sum of three terms). Draw using only a. NAND gates, b. NOR gates
3. a. Perform the subtraction 64 – 31 and 99 – 7 in 1’s and 2’s complement method.
b. Simplify the following expression to a sum of two terms and then factor the result
to obtain a product of sums:
ab d f  bceg h  abd f  ac d e  bce
4. Each of three coins has two sides, heads and tails. Represent the heads or tails status of each
coin by a logical variable (A for the first coin, B for the second coin, and C for the third) where
the logical variable is 1 for heads and 0 for tails. Write a logic function F(A, B, C) which is 1 iff
exactly one of the coins is heads after a toss of the coins. Express F
a. as a minterm expansion.
b. as a maxterm expansion.
Draw the circuit using only NOR gate.
5. Find the minimum minterms using K – map
F(a, b, c, d, e) =π M(2, 4, 5, 6, 8, 10, 12, 13, 16, 17, 18, 22, 23, 24) • πD(0, 11, 30, 31)
6. Design a network of NAND gates and inverters that converts from 8-4-2-1 BCD code to 6-3-1-
1 code.
7. Design and write the Verilog HDL for 4 bit parallel multiplier.
8. Draw the Mealy state diagram and state table for a serial even parity checker. The circuit
receives a word of 4-bits serially on its single input X and produces the even parity bit after the
fourth bit is received. The single output Z remains 0 except when the final (fourth) bit is
received and the total number of 1’s in the word is odd. The machine returns to the reset initial
state after the 4th input bit. Design the circuit using D – FF and write the code using gate level
and dataflow.
 SET – J
1. The adder-subtractor circuit of Fig. below has the following values for mode input M and data
inputs A and B:

in each case determine the values of the four SUM outputs, the carry C, and overflow V.

2. Convert the following

a. 1110100101.111012 = _________8,7,H
b. 65317 = __________10,2,8
3. Design a code converter to convert 53-1-1 to 8421
4. Perform the subtraction 52 – 73 and 111011 - 100101 using 1’s and 2’s complement method.
5. simplify the following using Boolean laws
a. AB  AC  A BC ( AB  C )
b. ABCD + A’B’C’D + A’BCD + AB’CD + A’B’CD + ABCD’ (Terms 4,5, and 6 are Don’t Care)
6. A combinational circuit has four inputs (A, B, C, D), which represent a binary coded- decimal
digit. The circuit has two groups of four outputs S, T, U, V, and W, X, Y, Z. Each group represents a
BCD digit. The output digits represent a decimal number which is five times the input number. For
example, if ABCD = 0111, the outputs are 0011 0101. Assume that invalid BCD digits do not occur as
inputs.
(a) Construct the truth table.
(b) Write down the minimum expressions for the outputs by inspection of the truth table.
7. Given the enclosed source code, draw the equivalent hardware circuit. Draw also
the periodic waveforms on the output signals f and g. If the reference clock is 200 MHz, then what are the
frequencies of signals f and g ?
module setm(input logic resetn, clock,
output logic f, g);
logic[9:0] counter;
always_ff @(posedge clock or negedge resetn)
if (!resetn) begin
counter <= 10'h000;
f <= 1'b0;
g <= 1'b0;
end else begin
 f <= 1'b1;
if (counter > 10'd50 && counter < 10'd250) f <= 1'b0;
g <= 1'b0;
if (counter > 10'd150 && counter < 10'd400) g <= 1'b1;
if (counter < 10'd900) counter <= counter + 10'd1;
else counter <= 10'd0;
end
endmodule
8. Design a sequential circuit using D - FF to convert excess-3 code to BCD. This circuit adds three to a
binary-coded-decimal digit in the range 0 to 9.The input and output will be serial with the least
significant bit first.
 SET – K
1. The output of a majority circuit is 1 if a majority (more than half) of its inputs are equal to 1, and
the output is 0 otherwise. Construct a truth table for a three input majority circuit and derive a
simplified sum-of-products expression for its output.
2. Design a code convert to convert 8421 to 2421.
3. You are presented with a set of requirements under which an insurance policy can be issued. The
applicant must be:
a. a married female 25 years old or over , or
b. a female under 25 , or
c. a married male under 25 who has not been involved in a car accident , or
d. a married male under 25 who has been involved in a car accident, or
e. a married male 25 year or over who has not been involved in a car accident.
Find an algebraic expression which assumes a value 1 whenever the policy is issued. Simplify the
expression obtained.

4. Convert the Following

i. 86753.12 = ___________2,H
ii. 11110001.11 = ______________O,9,4
iii. AED.87 = ______________9,2
5. Perform the following using 1’s and 2’s complement i. -21-43, ii. 76 - 111011
6. Simplify using K – map and give the SOP and POS
F = ∏(2,30,5,4,7,19,28,21,15,0,6).d(1,11,13,18,29)
f = (9,5,2,7,15,14,0,3)
7. Reduce the following using Boolean Algebra
f = m(0,2,3,5,7,12,15)
F = a’cd+ab’+ac’e+cd’+b’d’
8. Given the enclosed hardware circuit, write/simulate the equivalent Verilog code.

9. Design a sequential circuit using T - FF to convert BCD to excess-3 code. This circuit adds three
to a binary-coded-decimal digit in the range 0 to 9.The input and output will be serial with the
least significant bit first.
 SET – L
1. Convert the following
i. 11011010.110 = __________o,H,9
ii. 751.338 = __________2,5,9
iii. AFF.EEF = ____________2,o,9
2. Perform the following using 1’s and 2’s complement
i. 92 – 5
ii. 7 – 85
3. Simplify the following using Boolean Algebra
i. F = M(1,9,2, 5, 10,11,7,8)
ii. F  ( A  B  CD E )  BC D
iii. F = (BC’+A’D)(AB’+CD’)
4. Simplify using K – Map and give the SOP and POS
i. F = m(7,13,5,30,17,5,27,8,14,19)+d(0,11,12,15,21)
ii. Y = C ( A B D  D)  A BC  D
iii. Determine the minimum expression for each K map given below

5. Fig. below shows a diagram for an automobile alarm circuit used to detect certain undesirable
conditions. The three switches are used to indicate the status of the door by the driver’s seat, the
ignition, and the headlights, respectively. Design the logic circuit with these three switches as
inputs so that the alarm will be activated whenever either of the following conditions exists:

i. The headlights are on while the ignition is off.

ii. The door is open while the ignition is on.
6. Design a Code converter to convert 53-1-1 to excess 1 code.
7. Write the Verilog code using if else condition and truth table for the circuit given below.

8. Given the enclosed hardware circuit, write/simulate the equivalent Verilog code.
 SET - M

1. Convert the following

i.789.26 = __________2,H,7
ii. 1111111011.1101111 = ___________O,H
iii. 8EA.59 = ____O,9
2. Perform the following using 1’s and 2’s complement
i. 11101101 – 10010
ii. 87 – 34
3. Simplify the Following using Boolean Algebra
i. ( w  x  y  z )( w  x  y  z )( w  x  y  z )( w  x  y  z )( w  x  y  z )( w  x  y  z )
ii. Q  RST ( R  S  T )
iii. Change each gate into NOR gate and simplify the Boolean algebra

4. Simplify the following using K – map to SOP and POS

i. f = M(0,3,5,6,8,10)+d(11,13,14)
ii. F ( A, B, C , D)  A  B  D
iii. F = ∑(21,7,30,2,8,15,19,3) + d(0,18,15,6)
5. Design a Code Converter to convert 2421 code to 24-2-1 code
6. A manufacturing plant needs to have a horn sound to signal quitting time. The horn should be
activated when either of the following conditions is met:
i. It’s after 5 o’clock and all machines are shut down.
ii. It’s Friday, the production run for the day is complete, and all machines are shut down.
Design a logic circuit that will control the horn. (Hint: Use four logic input variables to
represent the various conditions; for example, input A will be HIGH only when the time of
day is 5 o’clock or later.)

7. For the given code give the hardware equivalent circuit and convert the code using case
statement.
module setj(input logic resetn, clock,
input logic start, stop,
input logic load, serial_in,
input logic [7:0] parallel_in,
output logic parity);
logic shift_left;
logic[7:0] shift_register;
always_ff @(posedge clock or negedge resetn)
begin
if (!resetn) begin
shift_left <= 1'b0;
shift_register <= 8'd0;
 end else begin
if (start) shift_left <= 1'b1;
if (stop) shift_left <= 1'b0;
if (shift_left) shift_register <= {shift_register[6:0],serial_in};
else if (load) shift_register <= parallel_in;
end
end
always_comb begin
parity = ^shift_register;
end
endmodule
8. Write Verilog code that represents the circuit in Figure below. Use the dec2to4 module as a
subcircuit in your code using case statement.
 SET – N
1. A computer interface to a line printer has seven data lines that control the movement of the
paper and the print head and determine which character to print. The data lines are labeled A,
B, C, D, E, F, and G, and each represents a binary 0 or 1. When the data lines are interpreted
as a 7-bit binary number with line A being the most significant bit, the data lines can represent
the numbers 0 to 12710. The number 1310 is the command to return the print head to the
beginning of a line, the number 1010 means to advance the paper by one line, and the numbers
3210 to 12710 represent printing characters.
(a) Write an equation for the variable X which is 1 iff the data lines indicate a command
to return the print head to the beginning of the line.
(b) Write an equation for the variable Y which is 1 iff there is an advance paper command on
the data lines.
(c) Write an equation for the variable Z which is 1 iff the data lines indicate a printable
character. (Hint: Consider the binary representations of the numbers 0–31 and 32–127 and
write the equation for Z with only two terms.)

2. Design a Code converter to convert 5311 code to gray code

3. Simplify the following using Boolean algebra
i. Y  (C  D) AC D  A BC  A BCD  AC D
ii.

iii. F = m(3,7,8,10,12,13)
4. Simplify the following using K – Map
i. f = m(31,0,4,6,19,25,17,7,2) + d(1,14,15,21,22)
ii. F = f  ab(cd )  abd  bc d
5. Perform the Following
i. Determine the value of the base x, (225)x = (341)8
ii. A9CF.B6116 = ________________8,9,2 `
iii. 1110000011.1001 = ______6,9,H
iv. 100100 – 1111111 and 98 – 43 using 1’s and 2’s complement
6. A bank vault has three locks with a different key for each lock. Each key is owned by a different
person. To open the door, at least two people must insert their keys into the assigned locks. The signal
lines A, B, and C are 1 if there is a key inserted into lock 1, 2, or 3, respectively. Write an equation for
the variable Z which is 1 iff the door should open.
7. For the given code give the hardware equivalent circuit and convert the code using case
statement
module problem(input logic resetn, clock,
input logic x, y, z, c1, c2,
output logic f, g);
always_ff @(posedge clock or negedge resetn)
begin
 if (!resetn) begin
f <= 1'b0;
end else begin
f <= x;
if (c1) f <= y;
if (c2) f <= z;
end
end
always_comb begin
if (c2) g = z;
else if (c1) g = y;
else g = x;
end
endmodule
8. Design a 4 bit serial adder with accumulator and write the Verilog HDL code.
 SET – O
1. Convert the following
i. 875.18 = ___________8,h,2
ii. 10000110.00101 = ___________4,9,H
iii. FFEE.DDB = _______10,2,O
2. 10011 – 1111101 and 76 – 9 using 1’s and 2’s complement subtraction
3. Simplify the following using Boolean law with minimum literals and implement using Universal
gates `
a. Y  A  AB  ( A  B )C  ( A  B  C )D
b. prove that A B C  A BC  AB C  ABC  A B C  A  B  C
4. Simplify the following using K – map to SOP and POS
i. f = M(0,3,5,6,8,10)+d(11,13,14)
ii. F ( A, B, C , D)  A  B  D
iii. F = ∑(21,7,30,2,8,15,19,3) + d(0,18,15,6)
5. Design a Code converter to convert BCD to Binary.
6. Simplify the following circuit and draw the optimized circuit using Boolean logic

7. Four large tanks at a chemical plant contain different liquids being heated. Liquid-level sensors
are being used to detect whenever the level in tank A or tank B rises above a predetermined level.
Temperature sensors in tanks C and D detect when the temperature in either of these tanks drops
below a prescribed temperature limit. Assume that the liquid-level sensor outputs A and B are
LOW when the level is satisfactory and HIGH when the level is too high. Also, the temperature-
sensor outputs C and D are LOW when the temperature is satisfactory and HIGH when the
temperature is too low. Design a logic circuit that will detect whenever the level in tank A or tank
B is too high at the same time that the temperature in either tank C or tank D is too low.
8. Design a 1-bit decrementer (a circuit which subtracts 1). Give
(a) the arithmetic relationship between input and out put signals
(b) the truth table,
(c) logic diagram.
Design a logic diagram of a 1-bit increment/decrement circuit controled by an id signal (increment
when id = 1, decrement otherwise). Write the HDL.
And Design a block diagram of a 4-bit increment/decrement circuit. Use the above HDL and
concatenate.
9. Design a sequential circuit that works as a traffic light controller. The circuit does
not have any data inputs (the clock and asynchronous reset are obviously available) and it has
three data outputs: Red, Green and Yellow. After reset the circuit will activate Red for 200 clock
cycles, then it will activate Green for 200 clock cycles and then it will activate Yellow for 20 clock
cycles (this sequence will repeat itself). While one output signal is turned on the other two output
signals are deactivated. Derive the data-path elements and the FSM in the control-path.
Write/simulate the Verilog code to verify the entire design.
 SET – P

1. Simplify the following using Boolean expression

 
i.  A  C  AD  A D  AC  C

ii. W X  X Y  YZ  W Z

iii. ab  bc  ca  ab  b c  c a

2. Find the SOP and POS for the following using K – map
i. A' B' C ' D' BC' D  A' C ' D  A' BC  AD'
ii. f = ∏(1,3,5,9,11,12,14)
iii. f = ∑(0,1,2,5,7,8,10,15)

3. Design a logic circuit whose output is HIGH whenever A and B are both HIGH as long as C and D are
either both LOW or both HIGH. Try to do this without using a truth table. Then check your result by
constructing a truth table from your circuit to see if it agrees with the problem statement.

4. Design a code converter to convert 2421 to 5311 code.

5. Perform the following

(i) 1001100-110011 using 1’s complement subtraction
(ii) 93 – 14 using 1’s complement
(iii) 87 – 6 using 2’s complement
6. Convert the following
i. 1111111012 = _______4,10, H
ii. 8AF2.E9 = _________2, 8, 10

7. You need to design a synchronous sequential circuit in the form of a positive edge-triggered
Moore machine using RS - FF. The input signal w is synchronized with the clock pulses C.
The output signal z should become 1 each time the value of the input signal w had not
changed for two clock pulses. This change in the output value will appear at the clock pulse
following the two pulses with the identical w values. See the example below for
clarification.
w: 001100011011100111111000010110 ...
z: 001010100100100101000001000001 ...
Set up the circuit’s state table and draw the state diagram

8. As an example of an unstructured combinational circuit design a circuit that divides a 3-bit

positive binary number a = (a2a1a0)2 by a 2-bit positive binary number b = (b1b0)2 calculating a
3-bit quotient q = (q2q1q0)2 and a 2-bit remainder r = (r1r0)2 so that

To make the task easier, take into account the following:

a. Complete the above table.
b. Derive logic equations for q and r. Aim at minimal implementation. Use
Karnaugh maps when it makes the job easier.
c. Draw logic diagrams and write the HDL code using gate level and dataflow.
 SET – Q
1. CONVERT THE FOLLOWING
i. 101011110.11101 = ___________9, ___16,H
ii. 467.238 = _______4, 2, H
iii. C49D.B7 = ___________2,8,7
2. Find the minimum product of sums and SOP for
(a) F(a, b, c, d, e) =∑ m(1, 2, 3, 4, 5, 6, 25, 26, 27, 28, 29, 30, 31)
(b) π(0,1,3,5,6,9,10,13,14)
3. Perform the following
i. 11110011 – 1110011 using 1’s and 2’s complement subtraction
ii. 88 – 43 using 1’s complement
iii. 35 – 95 using 2’s complement
4. Each of the following sentences has two possible interpretations depending on whether the AND
or OR is done first. Write an equation for each interpretation. (a) The buzzer will sound if the key
is in the ignition switch, and the car door is open, or the seat belts are not fastened. (b) You will
gain weight if you eat too much, or you do not exercise enough, and your metabolism rate is too
low. (c) The speaker will be damaged if the volume is set too high, and loud music is played, or
the stereo is too powerful. (d) The roads will be very slippery if it snows, or it rains, and there is
oil on the road.
5. Simplify the following using Boolean law with minimum literals and implement using Universal
gates `
a. Y  A  AB  ( A  B )C  ( A  B  C )D

b. prove that A B C  A BC  AB C  ABC  A B C  A  B  C

6. Show that A  B  C  D = ∑(0,3,5,6,9,10,12,15)

7. A synchronous sequential circuit based on a shift register is used as a "Majority voter". The
value of the input signal w that occurred most of the times in the past three clock pulses is
displayed at the output y. The gate denoted by the "M" is a so-called majority gate, it’s output
takes the same value as the majority of its inputs.

8. Analyze the shift register and draw state diagram and state table for the que 1. (Please take the
help of the initiated state diagram with eight states shown below, but draw your own figure to
answer).
 SET – R
1. Convert the following
a. 11110010.1110012 = __________8,5,H
b. 32134 = __________2,10,8
c. 34D.EFF = _______4,2,O
2. Perform the subtraction 64 – 31 and 99 – 7 in 1’s and 2’s complement method.
b. Simplify the following expression to a sum of two terms and then factor the result
to obtain a product of sums:
ab d f  bceg h  abd f  ac de  bce
3. The adder-subtractor circuit of Fig. below has the following values for mode input M and data
inputs A and B:

in each case determine the values of the four SUM outputs, the carry C, and overflow V.
4. Fig. below shows a diagram for an automobile alarm circuit used to detect certain undesirable
conditions. The three switches are used to indicate the status of the door by the driver’s seat,
the ignition, and the headlights, respectively. Design the logic circuit with these three switches
as inputs so that the alarm will be activated whenever either of the following conditions exists:
 iii. The headlights are on while the ignition is off.
iv. The door is open while the ignition is on.
5. Design a code converter to convert gray code to 2421.
6. Draw a state diagram for a mealy type state machine specified as follows:
- Denote "a" the initial state of the machine
- set the initial output to the initial input (the input is presented to the machine bit by bit)
- The output changes value only when three successive inputs have the same value and that value is
opposite to the current output. For example, if the current output is 1 and the machine detects three
consecutive 0 it changes the output to 0.
Design the circuit using D – FF and write the Verilog HDL.
7. Design the 4 bit 7311 code to 53-1-1 code and write the Verilog HDL using if else statement.
 SET – S
1. CONVERT THE FOLLOWING
i. 101010110.10011 = ___________9, ___16,H
ii. 726.58 = _______4, 2, H
iii. 67AD.EF = ___________2,8,7
2. PERFORM THE FOLLOWING
i. 1001101 – 1110011 using 1’s complement subtraction
ii. 1100011 – 10110011 using 2’s complement subtraction
iii. 93 – 65 using both 1’s and 2’s complement
iv. 57 - 99 using both 1’s and 2’s complement
3. Simplify the following using Boolean algebra
i. Y  (C  D) AC D  A BC  A BCD  AC D
ii.

iii. F = M(3,7,8,10,12,13)
4. Simplify the following using K – map to SOP and POS
i. f = M(0,3,5,6,8,10)+d(11,13,14)
ii. F ( A, B, C , D)  A  B  D
iii. F = ∑(21,7,30,2,8,15,19,3) + d(0,18,15,6)
5. Design a Code Converter to convert 24-2-1 code to 2421 code
6. Figure below shows the intersection of a main highway with a secondary access road. Vehicle-
detection sensors are placed along lanes C and D (main road) and lanes A and B (access road). These
sensor outputs are LOW (0) when no vehicle is present and HIGH (1) when a vehicle is present. The
intersection traffic light is to be controlled according to the following logic:
 1. The east-west (E-W) traffic light will be green whenever both lanes C and D are occupied.
2. The E-W light will be green whenever either C or D is occupied but lanes A and B are not both
occupied.
3. The north-south (N-S) light will be green whenever both lanes A and B are occupied but C and
D are not both occupied.
4. The N-S light will also be green when either A or B is occupied while C and D are both vacant.
5. The E-W light will be green when no vehicles are present. Using the sensor outputs A, B, C, and
D as inputs, design a logic circuit to control the traffic light.There should be two outputs, N-S and E-
W, that go HIGH when the corresponding light is to be green. Simplify the circuit as much as possible
and show all steps.
7. Write an HDL dataflow description of a 4-bit adder/subtractor of unsigned numbers. Use the
FOR loop.
8. Design a sequential circuit using T - FF that has 1 data input (w) and 1 data output (z). The
output z will become 1 only if the input w has been 1010 over the last 4 clock cycles. Draw the
FSM diagram and write/simulate the Verilog code to verify it.
 SET – T
1. A manufacturing plant needs to have a horn sound to signal quitting time. The horn should be
activated when either of the following conditions is met:
i. It’s after 5 o’clock and all machines are shut down.
ii. It’s Friday, the production run for the day is complete, and all machines are shut down.
iii. Design a logic circuit that will control the horn. (Hint: Use four logic input variables to
represent the various conditions; for example, input A will be HIGH only when the
time of day is 5 o’clock or later.)
2. Simplify using K – Map and give the SOP and POS i. F =
m(7,13,5,30,17,5,27,8,14,19)+d(0,11,12,15,21) ii. Y =
C ( A B D  D)  A BC  D iii. Determine the
minimum expression for each K map given below

3. Convert the Following i.

86753.12 = ___________2,H ii. 11110001.11 =
______________O,9,4 iii. AED.87 = ______________9,2
4. Design a code converter to convert 53-1-1 to 84-2-1
5. Perform the subtraction 52 – 73 and 111011 - 100101 using 1’s and 2’s complement method.
6. i. Reduce the combinational logic circuit in Fig. to a minimum form.

7. Simplify the following using Boolean algebra

i. f=m(1,2,4,7,10,12)
ii. F = M(1,2,3,8,9,10,11,14)
8. Identify each of the following expression as SOP, POS and its canonical form respectively

a. AB  ABD  AC D
b. (A’+B) (A+B+D)D’
9. Write an HDL dataflow description of a 4-bit adder/subtractor of unsigned numbers. Use the
conditional operator.
10. Design a sequential circuit using JK - FF that has 1 data input (w) and 1 data output (z). The
output z will become 1 only if the input w has been 1 for the last 5 clock cycles. Draw the FSM
diagram and write/simulate the Verilog code to verify it.
REG NO NAME SET
19BEC0807 A KEVIN GEORGE A
19BEC0339 AASTHA SINGH B
19BEC0417 ABHIRUP GHOSH C
19BEC0328 ABHISHRI ANANDRAO PATIL D
19BEC0254 ADDALA PADMINI REETHI E
19BEC0768 AJITHESH S F
19BEC0836 AKSHAD PATEL G
19BEC0285 AKSHUNI RAGHUWANSHI H
19BEC0295 AMAN KUMAR TRIVEDI I
19BEC0319 AMISHA RATHORE J
19BEC0838 ANMOL KRISHNA NARAIN K
19BEC0314 ANURAG MUKHERJEE L
19BEC0632 APPANI KAUSHIK M
19BEC0293 ARATRIK ROY N
19BEC0710 ARCHISMAN HOTA O
19BEC0553 ARYAN PANDEY P
19BEC0241 ASHWIN V PILLAI Q
19BEC0411 B MOHAN PRAKASH R
19BEC0312 B N PRADEETH S
19BEC0826 BARATH BALAJI T
19BEC0196 BODDUPALLI V S R G S N ADITYA A
18BEC0369 BOGGAVARAPU ROSHINI LAKSHMI B
19BEC0063 BOLLINENI PAWAN KUMAR C
19BEC0308 BOYA SAI NITHISH D
19BEC0747 BOYI VENKATA SRI SAI VIVEK E
19BEC0448 CHEBOLU BHANU NANDINI F
18BEC0817 CHENGISH AHMED RAZDAN G
19BEC0422 CHIKKA MANJUNATH H
19BEC0778 CHINNAKOTLA MOHAMMED JUNAID I
19BEC0102 CHINTHAPALLI NAGA VENKATA AKHIL J
19BEC0808 D ABISHEK K
19BEC0857 DABBADA VARUN KUMAR L
19BEC0812 DEVAKINANDAN PALLA M
19BEC0805 DHANUSH ROHIT S N
19BEC0405 DINESH KUMAR P O
19BEC0431 DWARSALA TEJASWINI P
19BEC0721 E SIVASIDHARTH Q
19BEC0825 ELENTA SUZAN JACOB R
19BEC0313 ENNAPUREDDY SATHWIK S
18BEC0230 GAURAV BOSE T
19BEC0019 GOUDAPPAGARI AKHILESWAR REDDY A
19BEC0717 GOWRAM SAI YASHWANTH REDDY B
19BEC0349 GUJJULA YASHWANTH REDDY C
19BEC0246 GUNDREDDY NIRANJAN REDDY D
19BEC0278 GURRAM SAI VIKRAM E
19BEC0412 HARSHIT TYAGI F
19BEC0811 J RAJA CHIDAMBARAM G
19BEC0696 JERNIGAN ANTONY M H
19BEC0080 K MOHAMMED FAZIL I
19BEC0734 K S JAWAHAR SACHIN J
19BEC0111 K SHAKTHI DHAR REDDY K
19BEC0311 KAMIREDDY CHINMAYEE L
19BEC0213 KARANAM SRI HARITH M
19BEC0464 KOLLIPARA KARTHIKEYA N
19BEC0751 KOMMINENI SHANMUKESH O
19BEC0469 KOTTURU VARUN SHRIDHAR P
19BEC0769 LOHITH KUMAR REDDY AVUTHU Q
19BEC0786 M G POOJITHA R
19BEC0507 MEKA BHAVANI PRAKASH VYAS S
19BEC0082 MERWIN SANKAR J S T
19BEC0321 MIRYALA ACHYUTH A
19BEC0317 MOHD KABIR HAIDER B
19BEC0765 MOTUPALLI VENKATA SAI VINAY C
19BEC0686 MUDIT SHARMA D
19BEC0231 MUDRAKOLA MANIPREETHAM E
19BEC0641 NADIMINTI SATYA SAI SUJAN F
19BEC0117 NAVIN DHARAMPAL POONIA G
19BEC0224 NAVIN R S H
19BEC0700 NIKHIL KUMAR I
19BEC0399 PATIL GAURAV PRASHANT J
19BEC0222 PATRICK TONY PETER P K
19BEC0441 PAVANKUMAR M L
19BEC0010 POLAKI VIVEKSAGAR M
19BEC0326 POTHAPRAGADA SAI SATWIKA N
19BEC0215 PUJARI YASWANTH KALYAN O
19BEC0039 PULI NAVEEN REDDY P
19BEC0098 PULIPATI BHARGAV Q
19BEC0708 PUSPENDU ROY R
19BEC0712 R SARAVANAN S
19BEC0445 RALLABANDI VISHNU VARDHAN T
19BEC0552 RATHI HRITIKA PANKAJ A
19BEC0798 RISHI RANJAN B
19BEC0531 RITVIK ROSHAN S C
19BEC0589 ROBINS EDINBOROUGH J D
19BEC0780 RUDRAPAKA SRI SAI GOVIND E
19BEC0324 RUPAKULA SAI PRIYANKA F
19BEC0743 S MUNWAR ALI G
19BEC0661 S TARUN H
19BEC0631 SAGI S S PAVAN KUMAR VARMA I
19BEC0360 SAI TEJA KONDABALA J
19BEC0529 SARVESH PRASATH K
19BEC0372 SHINJINI SINHA L
19BEC0797 SHREYA GUNANITHI M
19BEC0388 SHRI SHARAN R N
19BEC0281 SHUBHAM KUMAR O
19BEC0375 SINGH AGNEYA KUMAR P
17BEC0532 SIRIGINEEDI VENKATA NAVEEN Q
19BEC0511 SOHAM ROY R
19BEC0746 SOMA YASWANTH KUMAR REDDY S
19BEC0843 SOMALARAJU CHENCHU BABU T
19BEC0237 SOUBHAGYA ROUTRAY A
19BEC0803 SOURODIPTO BHOWMICK B
19BEC0782 SRI P KANTHAN C
19BEC0828 SUBASH CHAKRA VARTHY SUGUMARAN D
19BEC0244 SYAGALETI VIKAS REDDY E
19BEC0527 T PRAWANTH REDDY F
19BEC0356 TANGIRALA SAKETH RAM G
19BEC0676 THARUN PRATHAPAN H
TOTLAPALLI SHAIK MOHAMMED
19BEC0626 KHALID I
19BEC0274 UPPALA PATI DHANUSH J
19BEC0463 UTKARSH SINHA K
19BEC0567 V J VENKAT AKASH L
19BEC0394 V SARVESH PRASANTH M
19BEC0755 VADDIRAJU ABHINAV N
18BEC0007 VADLA SUCHARAN REDDY O
19BEC0539 VANGAVEETI THANMAY P
19BEC0748 VARUN KARTHIK P Q
19BEC0536 VARUN VAIBHAV ANILKUMAR R
19BEC0309 VENKATA NITIN VOONA S
19BEC0292 VISHAL SINGH T
19BEC0658 VUYYURI NIKITH VARMA A
19BEC0599 YASH AGARWAL B
19BEC0783 YEDDULA SREYA REDDY C
19BEC0208 YERRAGUNTLA SAI PRASHANTH REDDY D
19BEC0471 YERRI SAI DHANUSH KUMAR REDDY E