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Freescale Cortex.m0.code - Density

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Freescale Cortex.m0.code - Density

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Get Better Code Density than 8/16 bit

MCU’s
NXP LPC1100 Cortex M0

Oct 2009
Outline
Introduction

ARM Cortex-M0 processor

Why processor bit width doesn’t matter

– Code size
– Performance
– Cost

Conclusions

2
ARM Cortex-M Processors
Cortex-M family optimised for deeply embedded
– Microcontroller and low-power applications

ARM Cortex-A Series:

Applications processors for
feature-rich OS and user applications

ARM Cortex-R Series:

Embedded processors for
real-time signal processing
and control applications

ARM Cortex-M Series:

Deeply embedded processors
optimized for microcontroller
and low-power applications

3
ARM Cortex-M0 Processor

32-bit ARM RISC processor

– Thumb 16-bit instruction set

Very power and area optimized

– Designed for low cost, low power

Automatic state saving on interrupts and exceptions

– Low software overhead on exception entry and exit

Deterministic instruction execution timing

– Instructions always takes the same time to execute*

*Assumes deterministic memory system

4
Thumb instruction set

32-bit operations, 16-bit instructions

– Introduced in ARM7TDMI (‘T’ stands for Thumb)
– Supported in every ARM processor developed since
– Smaller code footprint

Thumb-2
– All processor operations can all be handled in ‘Thumb’ state
– Enables a performance optimised blend of 16/32-bit instructions
– Supported in all Cortex processors

Thumb®
Thumb instruction set upwards compatibility

ARM7 ARM9 Cortex-M0 Cortex-M3 Cortex-R4 Cortex-A9

5
Instruction set architecture
Based on 16-bit Thumb ISA from ARM7TDMI
– Just 56 instructions, all with guaranteed execution time
– 8, 16 or 32-bit data transfers possible in one instruction

Thumb Thumb-2
User assembly code, compiler generated System, OS
ADC ADD ADR AND ASR B NOP

BIC BL BX CMN CMP SEV WFE

EOR LDM LDR LDRB LDRH LDRSB WFI YIELD

LDRSH LSL LSR MOV MUL MVN DMB

ORR POP PUSH ROR RSB SBC DSB

STM STR STRB STRH SUB SVC ISB

TST BKPT BLX CPS REV REV16 MRS

REVSH SXTB SXTH UXTB UXTH MSR

6
Program registers r0
r1
r2
All registers are 32-bit wide r3
– Instructions exist to support 8/16/32-bit data
r4
r5
13 general purpose registers r6
– Registers r0 – r7 (Low registers) r7
– Registers r8 – r12 (High registers) r8
r9
r10
3 registers with special meaning/usage
– Stack Pointer (SP) – r13 r11
– Link Register (LR) – r14 r12
– Program Counter (PC) – r15 r13 (SP)
r14 (LR)
r15 (PC)
Special-purpose registers - xPSR
xPSR

7
Instruction behaviour

Most instructions occupy 2 bytes of memory

a = a * b; C code 15 0

MUL r0, r1; Assembler MUL

When executed, complete in a fixed time

– Data processing (e.g. add, shift, logical OR) take 1 cycle
– Data transfers (e.g. load, store) take 2 cycles
– Branches, when taken, take 3 cycles

The instructions operate on 32-bit data values

– Processor registers and ALU are 32-bit wide!

8
Thumb instructions

Cortex M0 requires instruction fetches to be half word

aligned
Thumb instructions are aligned on a two-byte boundaries

32 bit instructions are organized as 2 half words

9
Nested Vectored Interrupt Controller
NVIC enables efficient exception handling
– Integrated within the processor - closely coupled with the core
– Handles system exceptions & interrupts

The NVIC includes support for

– Prioritization of exceptions
– Tail-chaining & Late arriving interrupts

Fully deterministic exception handling timing behavior

– Always takes the same number of cycles to handle an exception
– Fixed at 16 clocks for no jitter
– Register to trade off latency versus jitter

Everything can be written in C

10
Interrupt behaviour

r0
r1
r13 (SP)
r2
r3
r12 Push Stack
r14 (LR)
r15 (PC) Growth
xPSR
Memory

On interrupt, hardware automatically stacks corruptible state

Interrupt handlers can be written fully in C
– Stack content supports C/C++ ARM Architecture Procedure Calling Standard

Processor fetches initial stack pointer from 0x0 on reset

11
Writing interrupt handlers
Traditional approach ARM Cortex-M family

Exception table NVIC automatically handles

– Fetch instruction to branch – Saving corruptible registers
– Exception prioritization
Top-level handler – Exception nesting
– Routine handles re-entrancy
IRQVECTOR
LDR PC, IRQHandler ISR can be written directly in C
. . – Pointer to C routine at vector
IRQHandler PROC
STMFD sp!,{r0-r4,r12,lr} – ISR is a C function
MOV r4,#0x80000000
LDR r0,[r4,#0]
SUB sp,sp,#4
CMP r0,#1
Faster interrupt response
BLEQ C_int_handler – With less software effort
MOV r0,#0
STR r0,[r4,#4]
ADD sp,sp,#4
LDMFD sp!,{r0-r4,r12,lr} WFI, sleep on exit
SUBS pc,lr,#4
ENDP

12
Software support for sleep modes

ARM Cortex-M family has architected support for sleep states

– Enables ultra low-power standby operation
– Critical for extended life battery based applications
– Includes very low gate count Wake-Up Interrupt Controller (WIC)

Power Management Unit

Sleep
– CPU can be clock gated
– NVIC remains sensitive to interrupts
Cortex-M0
Deep
Wake-up Deep sleep
Sleep – WIC remains sensitive to selected interrupts
– Cortex-M0 can be put into state retention
WIC
NVIC
WIC signals wake-up to PMU
– Core can be woken almost instantaneously
Wake-up – React to critical external events
sensitive
Interrupts
External interrupts
13
Instruction set comparison

14
Code Size

15
Code size of 32 bits versus 16/8bit MCU’s
The instruction size of 8 bit MCU’s is not 8 bits
– 8051 is 8 to 24 bits
– PIC18 is 18 bits
– PIC16 is 16 bits
The instruction size of 16 bit MCU’s is not 16 bits
– MSP430 can be up to 32bits and the extended version can be up to 64 bits
– PIC24 is 24 bits

The instruction size for M0 is mostly 16 bits

16
Code size of 32 bits versus 16/8bit MCU’s

17
16-bit multiply example
Consider an device with a 10-bit ADC
– Basic filtering of data requires a 16-bit multiply operation
– 16-bit multiply operation is compared below

8-bit example 16-bit example ARM Cortex-M0

MOV A, XL ; 2 bytes MUL AB; 1 byte
MOV B, YL ; 3 bytes ADD A, R1; 1 byte MOV R1,&MulOp1 MULS r0,r1,r0
MUL AB; 1 byte MOV R2,&MulOp2
MOV R1, A; 1 byte
MOV R0, A; 1 byte
MOV R1, B; 3 bytes MOV A, B ; 2 bytes MOV SumLo,R3
MOV A, XL ; 2 bytes ADDC A, R2 ; 1 bytes MOV SumHi,R4
MOV B, YH ; 3 bytes MOV R2, A; 1 byte
MUL AB; 1 byte
MOV A, XH ; 2 bytes
ADD A, R1; 1 byte
MOV R1, A; 1 byte MOV B, YH ; 3 bytes
MOV A, B ; 2 bytes MUL AB; 1 byte
ADDC A, #0 ; 2 bytes ADD A, R2; 1 byte
MOV R2, A; 1 byte
MOV R2, A; 1 byte
MOV A, XH ; 2 bytes
MOV A, B ; 2 bytes
MOV B, YL ; 3 bytes
ADDC A, #0 ; 2 bytes
MOV R3, A; 1 byte

Time: 48 clock cycles* Time: 8 clock cycles Time: 1 clock cycle

Code size: 48 bytes Code size: 8 bytes Code size: 2 bytes
* 8051 need at least one cycle per instruction byte fetch as they only have an 8-bit interface
18
What about Data ?
8 bit microcontrollers do not just process 8 bit data
– Integers are 16 bits
– 8 bit microcontroller needs multiple instructions integers
– C libraries are inefficient
– Stack size increases
– Interrupt latency is affected
Pointers take multiple Bytes.
M0 can handle Integers in one instruction
M0 can efficiently process 8 and 16 bit data
– Supports byte lanes
– Instructions support half words and bytes.
LDR, LDRH, LDRB

M0 has efficient Library support

– Optimized for M0

19
What about Data ?
For 16 bit processors have issues with
– Long integers
– Floating point types
– Data transfers between processor registers and memory

16 bit processors have 16 bit registers

– Two registers required for 32 bit transfers
– Increased stack requirements

M0 has 32 bit registers and 32 bit memories

– Less cycles for long integers
– Good floating point performance
– Less cycles for data transfers

20
What addressing modes?
16/8 bit processors are limited to 64K of space
– Data memory limited and segmented
– Requires banking or extensions to instruction set
– Memory pointers are extended
Require multiple instructions and registers

All cause increased code space

M0 has a linear 1G address space
– 32-bit pointers
– unsigned or signed 32-bit integers
– unsigned 16-bit or 8-bit integers
– signed 16-bit or 8-bit integers
– unsigned or signed 64-bit integers held in two registers.

21
Code size increase due to paging

22
Code size increase for large memory model
(Extended program counter and Registers)

23
Code Size Performance

2.50

2.00

1.50
HC08
M0 using microlib
1.00

0.50

0.00

puwmod
bitmnp

pntrch

rspeed
canrdr
a2time

iirflt
aifirf

aiifft

24
Code Size Performance
M0 code size is on average 10% smaller than best MSP430 average
Code size for basic functions

350
MSP430

MSP430F5438
300
MSP430F5438 Large model

Cortex M0
250
Code Size (Bytes)

200

150

100

0
Math8bit

Math16bit

Math32bit

Matrix2dim8bit

Matrix2dim16

Matrixmult

Switch8bit

Switch16bit
25
Code Size Performance
M0 code size is 42% and 36% smaller than best MSP430 generic

Floating Point and Fir Filter Code Size

1400
1200
Code Size(bytes)

1000
800 MathFloat
600 Firfilter
400
200
0

Cortex-M0
MSP430

MSP430F5438

MSP430F5438
Generic

large data
model

26
Code Size Performance
M0 code size is 30% smaller than MSP430F5438

Whet

7000

6000
Code Size (Bytes)

5000

4000

3000

2000

1000

0
MSP430
Generic

MSP430F5438

Cortex-M0
large data
model

27
What is CoreMark?

Simple, yet sophisticated

– Easily ported in hours, if not minutes
– Comprehensive documentation and run rules
Free, but not cheap
– Open C code source download from EEMBC website
– Robust CPU core functionality coverage
Dhrystone terminator
– The benefits of Dhrystone without all the shortcomings
• Free, small, easily portable
• CoreMark does real work

28
CoreMark Workload Features
Matrix manipulation allows the use of MAC and common math ops
Linked list manipulation exercises the common use of pointers
State machine operation represents data dependent branches
Cyclic Redundancy Check (CRC) is very common embedded function

Testing for:
– A processor’s basic pipeline structure
– Basic read/write operations
– Integer operations
– Control operations

29
Code Size Performance (CoreMark)
M0 code size is 16% smaller than generic MSP430