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DLD MCQS

This document contains information about a college course on digital logic design taught by Ateeq ur Rehman at Superior college. It includes the college name, course code ELE-401, teacher contact information, and 50 multiple choice questions related to digital logic design topics like binary, hexadecimal, logic gates, flip-flops, counters, and memory.

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515 views

DLD MCQS

This document contains information about a college course on digital logic design taught by Ateeq ur Rehman at Superior college. It includes the college name, course code ELE-401, teacher contact information, and 50 multiple choice questions related to digital logic design topics like binary, hexadecimal, logic gates, flip-flops, counters, and memory.

Uploaded by

ranaateeq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as XLSX, PDF, TXT or read online on Scribd
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College ID

College name Superior college M.B.Din


College Code ELE-401
College Title Digital Logic Design
Teacher Name Ateeq ur Rehman
Teacher CNIC 34403-0494472-7
Teacher Contact 3035153000

QUESTION_NO COURSE CODE


1 ELE-401
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Short question
1
2
QUESTION TEXT
For the binary number 1000, the weight of the column with the 1 is
The 2’s complement of 1000 is
The fractional binary number 0.11 has a decimal value of
The hexadecimal number 2C has a decimal equivalent value of
The number 1010 in BCD is
An example of an unweighted code is
Adjacent cells on a Karnaugh map differ from each other by
The output of a D latch will not change if
To cause a D flip-flop to toggle, connect the
A 4-bit binary counter has a terminal count of
A 4-bit parallel-in/parallel-out shift register will store data for
An advantage of a ring counter over a Johnson counter is that the ring counter
A possible sequence for a 4-bit ring counter is
Static RAM is
The first step in a read or write operation for a random access memory is to
When data is read from RAM, the memory location is
A device that is used to switch one of several input lines to a single output line is called a
The invalid state in an SR flip-flop using NOR gate arises when:
How many data select lines are required for selecting eight inputs?
A 3-bit binary counter has a maximum modulus of
Asynchronous counter are known as
In a JK Flip-Flop, toggle means
How many flip-flops are required to construct a decade counter?
Assign the proper odd parity bit to the code 111001 is
The BCD number for decimal 473 is
The Boolean expression X = (A + B)(C + D) represents
A full-adder is characterized by
Data distributors are basically the same as
For what combinations of the inputs D and EN will a D latch reset?
To enter a byte of data serially into an 8-bit shift register, there must be
A modulus-8 Johnson counter requires
To parallel load a byte of data into a shift register with a synchronous load, there must be
A decade counter with a count of zero (0000) through nine (1001) is known as
The modulus of a counter is
A 5-bit binary counter has a maximum modulus of
Which of the following is a valid state in an 8421 BCD counter?
A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN
Which one of the following is an example of a counter with a truncated modulus?
Two types of SPLDs are
The term LAB stands for
The output of an EX-NOR gate is 1. Which input combination is correct?
The time required for a gate or inverter to change its state is called __________
A variable on its own or in its complemented form is known as a __________
How many AND gates are required for a 1-to-8 multiplexer?
What is the difference between a shift-right register and a shift-left register?
ROM has the capability to perform _____________
Monostable multivibrator is/has ________ state.
Each product term of a group, w’.x.y’ and w.y, represents the ________in that group.
A combinational logic circuit which generates a particular binary word or number is
Latch is a device with ___________

Reduce AB + (AC)' + AB’C (AB + C)


What is Asynchronous counters. Explain Decade Asynchronous counter
CORRECT OPTION OPTION 1
8 6
1000 111
¾ ¼
44 14
invalid 12
Gray code BCD
one variable one variable
Enable is not active D is low
Ǭoutput to the D input clock to the D input
10 4
1 clock period 2 clock period

is self-decoding allows only one bit to change at a time


… 1000, 0100, 0010 … … 0001, 0011, 0111 …
volatile read only memory non-volatile read only memory
place a valid address on the address bus
enable the memory
unchanged
cleared after the read operation
multiplexer decoder
Both inputs are 1 Both inputs are 0
3 2
8 3
ripple counter multiple clock counter
Change the output to the opposite state Set Q = 1 and Q’ = 0
4 8
1111001 1111011
10001110011 10011110011
two ORs ANDed together two ANDs ORed together
three inputs and two outputs two inputs and three outputs
demultiplexers decoders
D = LOW, EN = HIGH D = LOW, EN = LOW
eight clock pulses one clock pulse
four flip-flops eight flip-flops
one clock pulse one clock pulse for each 1 in the data
A BCD counte an ASCII counter
the actual number of states in its sequence the number of flip-flops
32 16
1000 1111
1111 1001
Modulus 14 Modulus 8
PAL and GAL CPLD and PAL
logic array block logic AND block
A = 0, B = 0 A = 0, B’ = 1
Propagation time Rise time
Literal Product Term
8 5
The direction of the shift Propagation delay
 Read operation only Write operation only
Unstable  Stable
Sum-of-Minterms Sum of Maxterms
Decoder Multiplexer
Two stable state One stable state
OPTION 2
10
1001
¾
64
10
decimal
one variable
the output is low
Q output to the D input
15
3 clock period

is cleared after each cycle


… 0000, 0001, 0010 …
volatile read/write memory
send or obtain the data
set to all 1’s after the read operation
comparator
S=0,R=1
4
6
decade counter
Set Q = 0 and Q’ = 1
10
111111
11100010000
A 4-input AND gate
two inputs and one output
multiplexers
D = HIGH, EN = LOW
two clock pulses
five flip-flops
eight clock pulses
a binary counter
the number of times it recycles in a second
8
1011
1110
Modulus 16
PAL and FPGA
last asserted bit
A = 0, B = 1
Decay time
Sum Term
6
There is no difference
Both write and read operation
One stable and another unstable
POS
Encoder
Three stable state
OPTION 3
4
1010
none of the above
none of the above
8
Binary
Depends on size of map
all of the above
Clock to preset input
16
4 clock period
has more possible states for a given number of flip-flops
… 1111, 1110, 1101 …
nonvolatile read only memory
start a refresh cycle
destroyed
counter
S=1,R=0
1
16
modulus counter
No change in output.
5
11111
111011010
4-input OR gate
two inputs and two outputs
encoders
D = HIGH, EN = HIGH
four clock pulses
twelve flip-flops
one clock pulse for each 0 in the data
a decimal counter
the maximum possible number of states
4
1010
1000
Modulus 32
GAL and SRAM
logic assembly block
A = 1, B = 0
Charging time
Word
2
The clock input
Erase operation
Independent
Input
Demultiplexer
Four stable state

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