1

CMOS –Inverters
Lecture 2

Dr. Jerry L. Hudgins

Department of Electrical Engineering
University of South Carolina

Transistor Review 8/12/03

 2

Supply Voltage Effects

Transistor Review 8/12/03

 3

Gain as a Function of VDD

2.5 0.2

2
0.15

1.5

Vout (V)
Vout (V)

0.1

0.05
0.5

Gain = -1
0 0
0 0.5 1 1.5 2 2.5 0 0.05 0.1 0.15 0.2
V (V) V (V)
in
in

The gain can be improved by lowering the supply voltage,

however, below a few tenths of a volt, the gain deteriorates.

Transistor Review 8/12/03

 4

Effects of Reducing the Supply Voltage

ƒ Gain improves
ƒ Energy dissipation is lowered
ƒ Reduces internal noise (crosstalk)

ƒ dc characteristics become sensitive to

variations in device parameters
ƒ Increases sensitivity to external noise
ƒ Increases the propagation delay times!

Transistor Review 8/12/03

 5

Supply Voltage Effect on Propagation Delay

Average equivalent resistance during the load capacitance
discharge.
VDD
1 V 3VDD  7λVDD 
VDD / 2 VDD∫ / 2 I Dsat (1 + λV )
Req = dV ≈ 1 − 
4 I Dsat  9 

W  2
VDSsat 
I Dsat = k' (VDD − Vt )VDSsat − 2 
L  

Ignoring channel-length modulation factor:

3C LVDD C LVDD
t pHL = 0.69 Reqn C L − HL = 0.69 = 0.52
4 I Dsatn (Wn / Ln )k n' VDsatn (VDD − VTn − VDsatn / 2)
VDD
t pHL = t po ×
VDD − VTn − VDsatn / 2

Transistor Review 8/12/03

 Supply Voltage Effect on
6

Propagation Delay
VDD VDD
t pHL = t po × = t po ×
VDD − VTn − VDsatn / 2 VDD − 0.733

Note that supply

voltages below 1.1 V
cause an enormous
increase in the
propagation delay.

Transistor Review 8/12/03

 7

Propagation Delay Effects

from Sizing

Transistor Review 8/12/03

 8

Transient Response
3. 0V

2. 0V

tpHL tpLH

0V

- 1. 0V
0s 100ps 200ps 300ps 400ps 500ps
V( 2) V( 3)
Ti me

Transistor Review 8/12/03

A CMOS Inverter
9
*
.MODEL nch NMOS
+ LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=1
+ VTO=0.8 DELTA=2.5E-01 LD=4.0E-08 KP=1.88E-04
+ UO=545 THETA=2.5E-01 RSH=2.1E+01 GAMMA=0.62
+ NSUB=1.4E+17 NFS=7.1E+11 VMAX=1.9E+05 ETA=2.2E-02
+ KAPPA=9.7E-02 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.0E-10
+ CJ=5.4E-04 MJ=0.6 CJSW=1.5E-10 MJSW=0.3 PB=0.99
*
.MODEL pch PMOS
+ LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=-1
+ VTO=-0.9 DELTA=2.5E-01 LD=6.7E-08 KP=4.45E-05
+ UO=130 THETA=1.8E-01 RSH=3.4E+00 GAMMA=0.52
+ NSUB=9.8E+16 NFS=6.5E+11 VMAX=3.1E+05 ETA=1.8E-02
+ KAPPA=6.3E+00 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.3E-10
+ CJ=9.3E-04 MJ=0.5 CJSW=1.5E-10 MJSW=0.3 PB=0.95
*
M1 3 2 0 0 nch W=4u L=0.6u AS=7.2p PS=7.6u AD=7.2p PD=7.6u
M2 3 2 1 1 pch W=5.5u L=0.6u AS=9.9p PS=9.1u AD=9.9p PD=9.1u
CL 3 0 0.006pF
*
VDD 1 0 2.5V
VIN 2 0 PULSE(0 2.5 0 10p 10p 150p 1n)
*
.TRAN 0.005n 1n
*
.DC VIN 0V 2.5V 0.01V
*
.PROBE
* Transistor Review 8/12/03
.END
 10

NMOS/PMOS Ratios

For equal resistance values, the width ratio, β = Wp/Wn ,

should be 3 to 3.5. If symmetry and reduced noise
margins are not primary, then reducing the PMOS
channel width can reduce the propagation delay.

Consider two identical cascaded inverters where the drain

diffusion capacitances of the first inverter and the gate
capacitances of the second inverter plus the interconnect
capacitance between them are included :
CL = (Cdp1 + Cdn1 ) + (C gp 2 + C gn 2 ) + CW

Transistor Review 8/12/03

 11

NMOS/PMOS Ratios

When the PMOS are made β times larger than the

NMOS, then all capacitances scale the same way.

CL = (1 + β )(Cdn1 + C gn 2 ) + CW
Propagation delay then becomes: (where Reqn and Reqp
are resistances of identically sized transistors):
0.69  Reqp 
tp = [(1 + β )(C dn1 + C gn 2 ) + CW ] Reqn + 
2  β 
Optimal β then becomes :
∂t p
Reqp  C  =0
β opt = 1 + W  ∂β
Reqn  C dn1 + C gn 2 

Transistor Review 8/12/03

 NMOS/PMOS Ratio Effects on 12

-1 1
Propagation Delay
x 10
5

tpLH tpHL
4.5

The smallest delay

tp
is for β=1.9. Equal
t (s e c)

4
propagation delays
p

require β=2.4.
3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5
β

Transistor Review 8/12/03

 13

Inverter Sizing
•Assume a symmetrical inverter (PMOS and NMOS are
sized to give identical rise and fall times).

•Load capacitance can be divided into intrinsic and

extrinsic components: C =C +C L int ext

•Intrinsic capacitance represents the intrinsic output

capacitance of the inverter or the self-loading.
•It is composed of the diffusion capacitances of
transistors and gate-drain overlap (Miller)
capacitances.
•Extrinsic capacitance is the extrinsic load capacitance
made up of the input gate capacitances (fan-out) and
wiring capacitance.

Transistor Review 8/12/03

 14

Inverter Sizing
ƒ Let Req be the equivalent resistance of
the gate. Then the propagation delay is:
t p = 0.69 Req (Cint + Cext ) = 0.69 Req Cint (1 + Cext / Cint ) = t po (1 + Cext / Cint )

tpo is the intrinsic or unloaded delay.

Transistor Review 8/12/03

 15

Sizing a Chain of Inverters

ƒ Increasing an inverter’s size decreases
the delay, but it increases the input
capacitance. The intrinsic output
capacitance is proportional to the gate
capacitance and both are proportional
the transistor/inverter sizing.

Cint = ηC g
η is the proportionality factor and is near to unity in value.

Transistor Review 8/12/03

 16

Sizing of Inverter Chain

Therefore, the delay of an inverter is only a function

of the ratio, f, between its external load capacitance
and its input capacitance!!

t p = t po (1 + Cext / ηC g ) = t po (1 + f / η )

Transistor Review 8/12/03

 17

Inverter Chain Sizing

Input Output

Cg1 CL
N

Cg1 is the input capacitance of the 1st inverter.

CL is the load capacitance at the end of the fixed chain.

Transistor Review 8/12/03

 18

Inverter Chain Sizing

Input Output

Cg1 j CL
N

Delay expression for the jth stage is:

t p , j = t po (1 + C g , j +1 / ηC g , j ) = t po (1 + f j / η )
Total delay for the chain is:
N N
t p = ∑ t p , j =t po ∑ (1 + C g , j +1 / ηC g , j ) For Cg,N+1 = CL
j =1 j =1

Transistor Review 8/12/03

 19

Inverter Chain Sizing

N N
t p = ∑ t p , j =t po ∑ (1 + C g , j +1 / ηC g , j )
j =1 j =1

There are N-1 unknowns, given Cg1 and CL. The

minimum delay is found by taking N-1 partial
derivatives and setting them each to 0:
∂t p / ∂C g , j = 0
Result is:
C g , j +1 / C g , j = C g , j / C g , j −1
Or:
C g , j = C g , j −1C g , j +1

Transistor Review 8/12/03

 20

Inverter Chain Sizing

C g , j = C g , j −1C g , j +1

This expression means that each inverter in the chain

is sized up by the same factor, f, with respect to the
preceding gate, has the same effective fan-out (fj=f),
and therefore the same delay.

Thus, given Cg,1 and CL, the sizing factor for each
stage to give the same delay through each stage,
and the minimal total delay is:
f = C L / C g ,1 ≡ F
N N

Transistor Review 8/12/03

 21

Inverter Chain Sizing

The minimal delay through the inverter chain is then:

t p = Nt po (1 + N F / η )
F represents the overall effective fan-out of the circuit
and is equal to:
F = C L / C g ,1

Transistor Review 8/12/03

 22

Inverter Chain Sizing:

The Problem Posed One way
Usually Cg,1 is associated with a minimally-sized gate.

t p = Nt po (1 + N F / η )
For a given F (e.g. given a load capacitance to drive
from a minimally-sized gate), what is the number of
stages that obeys the minimal propagation delay
expression derived above?
If N is too large then the first term dominates
(intrinsic delay of the stages dominates). If N is too
small then the effective fan-out of each stage
becomes too large and the second term dominates.

Transistor Review 8/12/03

 23

Inverter Chain Sizing: The Solution

Differentiate the delay expression with respect to N

and set to 0.
 N
F  − 1 

∂t p / ∂N = t po (1 + F / η ) + Nt po (ln F )
N  2  = 0
 N 
 η 
F = f N = e N (1+η / f )
N
F = f = e (1+η / f )

Transistor Review 8/12/03

 24

Inverter Chain Sizing: The Solution

Given the first gate (usually minimally-sized), then

we know its input capacitance, Cg,1 and its intrinsic
output capacitance, Cint.

η = Cint / C g ,1
Knowing η, iteratively solve for f using the derived
expression: (1+η / f )
f =e
We know the load capacitance we are trying to drive,
CL, so we also know F = CL/Cg,1.

Transistor Review 8/12/03

 25

Inverter Chain Sizing: The Solution

Finally, having values for f and F, we can find N;

the number of stages needed to drive the load
capacitance that gives a minimal propagation delay
of the signal through the stages.
f =NF

Also, we can compute the delay time using

the expression previously derived:

t p = Nt po (1 + N F / η )

Transistor Review 8/12/03

 Example 1
26

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f = 3 C L / C1 = 3 8 = 2

Transistor Review 8/12/03

Example 2: Optimum Number of Stages
27

For a given load, CL and given input capacitance Cin

Find optimal sizing f and minimal delay.
ln F
C L = F ⋅ Cin = f Cin N
with N =
ln f
t p 0 ln F  f η 
(
t p = Nt p 0 F 1/ N
)
/η + 1 =  +
η  ln f ln f



Transistor Review 8/12/03

 Number of Stages to Minimize tp
28

N f tp
1 64 1 64 65

1 8 64
2 8=641/2 18

1 4 16 64 3 4=641/3 15

1 64 4 2.8=641/4 15.3
2.8 8 22.6

Transistor Review 8/12/03

 29

Homework #1
ƒ Using the Level-3 CMOS inverter model
given above, determine the tpHL and tpLH
for 6 to 10 different supply voltage
values from 2.5 to 1.1 V.
ƒ Do the simulations again using
Ln=Lp=0.25 µm, Wn=2 µm, and Wp=4 µm.

ƒ You will need to modify the VIN values

for the pulse and dc analysis as VDD is
changed.
Transistor Review 8/12/03
 30

Homework #2
ƒ Determine the sizes (f) of the inverters in
the circuit below such that the delay time
between input and output is minimized. (Hint:
First find the ratios between the devices
that minimize the delay. You should find
that: 4C g , 2 4C g ,3 C L
= =
C g ,1 C g , 2 C g ,3

ƒ Determine the sizes of the inverters if the

extra fan-out at each stage is not taken into
account.

Transistor Review 8/12/03

 31

Homework #2 - Circuit

Input
Output

CL = 64Cg,1
1 2 3

Transistor Review 8/12/03