How To Communicate With PC Using RS232 Protocol: Embedded Systems
How To Communicate With PC Using RS232 Protocol: Embedded Systems
Protocol
There are two types of communication possible between two devices depending upon the number of wires required.
1. Parallel communication: In this, more than one wire is connected between two communicating node. Each bit
is sent separately on dedicated wire. In this approach, numbers of wires required=width of data bus. This is
preferred for short way communication. Over a long distance, this increases cost of wires and maintenance.
2. Serial Communication: In this, data is combined into a packet and sent bit by bit on a single wire between two
communicating devices. This requires less costly implementation and maintenance. However, synchronization
between communicating devices is necessary. Sometimes separate wires are required for two-way communication.
This approach is widely used for long distance, high speed and reliable communication.
Serial communication using UART (Universal Asynchronous Receiver/Transmitter) is widely used in embedded
systems. Almost all controller has inbuilt UART available for easy communication. IBM PC also comes with serial COM
PORTS so that we can communicate with them using controllers. Using USB to serial bridge, we can create virtual
COM PORTS and communicate with controllers using the same.
Baud rate is the measurement of speed of data transfer for serial communications. Various baud rate supported by
UART for given maximum distance is as follows.
Out of these 9 pins, only 3 (RxD, TxD and GND) pins are necessary for serial communication between PC and
controller. Connection is as shown.
Connection
between DB9 Connectors
Microcontroller works on TTL or CMOS voltage logic levels. But PC operates on RS232 voltage logic level which is
different from CMOS or TTL.
LPC 2148 has two UARTs named as UART0 and UART1. UART0 is used for programming LPC 2148.
UART oins of LPC 2148
Important registers for UART0 with functions are listed here.
1. U0RBR- Receiver Buffer- Received data from UART0 is first stored in this register.
2. U0THR-Transmit Hold Register- Data to be transmitted on UART0 must be given to this register.
3. U0LCR- Line Control Register- It has bits to enable DLL (BIT 7), Set break (BIT 6), Stick Parity select (BIT 5), Even
Parity select (BIT 4), Parity Enable (BIT 3), Number of stop bits (BIT 2) and Word length (BIT 1 and BIT 0)
4. U0LSR- Line Status Register- It reflects the status of UART0. 8 bits of this register from MSB to LSB are RX FIFO
Error, TEMT, THRE,BI,FE,PE,OE and DR.
Baud rate for UART can be calculated by formula,
Bau
drate calculations for LPC 2148
Where, PCLK= Peripheral Clock Frequency
U0DLM, U0DLL are standard UART0 baud rate generator divider registers
MULVAL and DIVADDVAL are fraction generator values. They must meet following conditions.
· Bit 5:4 for parity select (required only if bit 3 is set to logic 1)
o 00: Odd parity. Number of 1s in the transmitted character and theattached parity bit will be odd
o 01: Even Parity. Number of 1s in the transmitted character and theattached parity bit will be even
o 1: Enable breaks transmission. Output pin UART0 TXD is forcedto logic 0 when U0LCR [6] is active high
1. UOLSR
The U0LSR (UART0 LINE STATUS REGISTER) is a read-only register that provides status information on the UART0
TX andRX blocks.It is an 8 bit register. Function of each pin is as follows.
· Bit 0- Receiver Data Ready (RDR)
o U0LSR0 is set when the U0RBR holds an unread character and is clearedwhen the UART0 RBR FIFO is empty.
o The overrun error condition is set as soon as it occurs. An U0LSR read clearsU0LSR1. U0LSR1 is set when UART0
RSR has a new character assembledand the UART0 RBR FIFO is full. In this case, the UART0 RBR FIFO will notbe
overwritten and the character in the UART0 RSR will be lost.
o When the parity bit of a received character is in the wrong state, a parity erroroccurs. An U0LSR read clears
U0LSR[2]. Time of parity error detection isdependent on U0FCR[0].
o When the stop bit of a received character is at logic 0, a framing error occurs.An U0LSR read clears U0LSR[3].
The time of the framing error detection isdependent on U0FCR0. Upon detection of a framing error, the Rx will
attemptto resynchronize to the data and assume that the bad stop bit is actually anearly start bit. However, it cannot
be assumed that the next received byte willbe correct even if there is no Framing Error.
o When RXD0 is held in the spacing state (all 0’s) for one full charactertransmission (start, data, parity, stop), a
break interrupt occurs. Once thebreak condition has been detected, the receiver goes idle until RXD0 goes tomarking
state (all 1’s). An U0LSR read clears this status bit. The time of breakdetection is dependent on U0FCR[0].
o TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared wheneither the U0TSR or the U0THR
contain valid data.
o U0LSR[7] is set when a character with a Rx error such as framing error, parityerror or break interrupt, is loaded
into the U0RBR. This bit is cleared when theU0LSR register is read and there are no subsequent errors in the
UART0FIFO.
circuit diagram
code
#include "serial.h"
int main(void)
int j=0;
Code2