EMT 235/3

DIGITAL ELECTRONIC PRINCIPLES II

DR. MOHAMMAD NUZAIHAN BIN MD NOR

INSTITUTE OF NANO ELECTRONIC

ENGINEERING (INEE)

012 – 4296433

[email protected]

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 EMT 235/3

DIGITAL ELECTRONIC
PRINCIPLES II

CHAPTER 2:

COUNTERS

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Chapter Overview
—  Asynchronous Counter Operation
—  Synchronous Counter Operation
—  Design of Synchronous Counters
—  Up / Down Synchronous Counters
—  Cascaded Counters
—  Counter Decoding
—  Shift Register Counters
—  Counter Applications

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 Introduction
•  A Counter – a group of flip-flops (FF) connected together to
perform counting operations.
•  The number of flip-flops used and the way in which they are
connected determine the number of states (modulus).
•  Two broad categories according to the way they are
clocked:
•  Asynchronous counter – The first FF is clocked by the
external clock pulse and then each FF is clocked by output
of the preceding FF.
•  Synchronous counter – The clock input connected to all
the FF so that they are clocked simultaneously.

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Asynchronous Counter
•  Do not have fixed time relationship with each other.
•  Triggering, do not occur at the same time.
•  Do not have a common clock pulse.

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 Asynchronous Counter (cont..)
Example 1: 2-bit asynchronous binary counter.

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 Asynchronous Counter (cont..)
Solution 1: 2-bit asynchronous binary counter.

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 Asynchronous Counter (cont..)
Example 2: Three-bit Asynchronous binary counter and its timing
diagram for one cycle.

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 Asynchronous Counter (cont..)
Solution 2: Three-bit Asynchronous binary counter and its timing
diagram for one cycle.

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 Asynchronous Counter (cont..)
Quiz 1

1. With the aid of the circuit and timing diagram, design a four-bit
asynchronous counter.

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 Modulus of a counter
—  modulus of a counter – number of unique states through
which the counter will sequence

—  maximum modulus – the maximum possible of states of

a counter is 2n, where n is the number of flip-flops in the
counter

—  truncated sequence – the number of states with a

sequence less than the maximum of 2n
 Asynchronous Decade Counter
-  Decade counter – a counter with ten states in their sequence (MOD10).
A common modulus for counters
-  binary coded decimal (BCD) decade counter – a decade counter with a
count sequence of zero (0000) through (1001). The ten-state sequence
produce the BDC code

Example 3: Asynchronous decade counter.

HIGH

Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3

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Asynchronous Decade Counter (cont..)
Solution 3: Timing diagram for asynchronous decade counter

- The counter is in the 1010 state for a short time before it is reset
to 0000, thus producing the glitch on Q1 and the resulting glitch on
the CLR line that resets the counter.

1 2 3 4 5 6 7 8 9 10
CLK
Q0

Q1 Glitch
Glitch

Q2

Q3

CLR
Glitch
Glitch
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 Asynchronous Counter (cont..)
Quiz 1

2. Show how an asynchronous counter can be implemented having a

modulus of 14 (MOD 14) with binary sequence 0000 through 1101.

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Answer
An asynchronous counter having a modulus of 14 with a
straight binary sequence from 0000 through 1101.
 Asynchronous Counter (cont..)
74LS93 asynchronous binary counter
—  consists of a single flip-flop and a 3-bit asynchronous counter.
—  can be used as a divide-by-2 device if only the single flip-flop is used, or it
can be used as a modulus-8 counter if only the 3-bit counter portion is
used.
—  RO(1) and RO(2) - gated reset inputs. When both of these inputs are HIGH,
the counter is reset to the 0000 state /CLR.

divide-by-2 device
modulus-8 counter

Logic diagram
Asynchronous Counter (cont..)
74LS93 asynchronous binary counter

Question: How do you connect the 74LS93 as :

1.  Modulus-16 counter ? (MOD 16)

2.  MOD 10

3.  MOD 12
 Asynchronous Counter (cont..)
—  The 74LS93 can be used as a 4-bit modulus-16 counter (counts 0 through 15)
by connecting the Q0 output to the CLK B input as shown in (a).
—  It can also be configured as a decade counter (counts 0 through 9) with
asynchronous recycling by using the gated reset inputs for partial decoding of
count ten (1010), as shown in (b)
—  Immediately after the counter goes to count 10 (1010), it is reset to 0000.
—  The recycling, however, results in a glitch on Q1 because the counter must go
into the 1010 state for several nanoseconds before recycling.

Q3 = MSB
Q0 = LSB

(a) (b)
Propagation delay
—  Asynchronous counters are known as ripple counters because the effect
of the input clock pulse does not affect all the outputs of the flip-flops
simultaneously but “ripples” through the counter due to propagation
delay.

Q1 is delayed by 1 delay Q2 is delayed by 2 delays Q3 is delayed by 3 delay

Propagation delay (cont …)
—  The cumulative delay of an asynchronous counter is a major
disadvantage especially in high speed applications because it
limits the rate at which the counter can be clocked and
creates decoding problems.

—  The maximum cumulative delay in a counter must be less

than the period of the clock waveform
 Synchronous Counter
In a synchronous counter all flip-flops are clocked together
with a common clock pulse. Synchronous counters overcome
the disadvantage of accumulated propagation delays, but
generally they require more circuitry to control states changes.

HIGH Q0
This 3-bit binary Q0Q1
synchronous counter
has the same count Q0 Q1 Q2
J0 J1 J2
sequence as the 3-bit
asynchronous counter C C C
shown previously. K0 K1 K2
CLK

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 Synchronous Counter (cont..)
Example 1
2-bit Synchronous binary counter.

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 Synchronous Counter (cont..)
Solution 1
2-bit Synchronous binary counter.

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Synchronous Counter (cont..)
Table for 2-bit Synchronous binary counter.

Clock Q1 Q2
Pulse
0 (Initially) 0 0
1 0 1
2 1 0
3 1 1
4 (recycle) 0 0

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 Synchronous Counter (cont..)
Example 2
3-bit Synchronous binary counter.

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 Synchronous Counter (cont..)
Solution 2
3-bit Synchronous binary counter.

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 BCD Decade Counter
With some additional logic, a binary counter can be converted
to a BCD synchronous decade counter. After reaching the
count 1001, the counter recycles to 0000.

This gate detects 1001, and causes FF3 to toggle on the next
clock pulse. FF0 toggles on every clock pulse. Thus, the
count starts over at 0000.
Q3
HIGH Q0
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

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BCD Decade Counter
Output
Waveforms for the decade counter:

1 2 3 4 5 6 7 8 9 10
CLK
Q0 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0

Q3 0 0 0 0 0 0 0 0 1 1 0

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BCD Decade Counter
The binary state sequence for BCD Decade counter

CLOCK Q3 Q2 Q1 Q0
PULSE
Initially 0 0 0 0

1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycles) 0 0 0 0

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 Design of Synchronous Counters
—  The followings are the general steps used to design a
synchronous counter

1)  obtain the state diagram for the counter

2)  obtain the state table
3)  choose the type of flip-flops to be used
4)  from the state table, obtain the required input for each
flip-flop to produce the next state for the given
present state based on the flip-flop excitation table
5)  obtain the simplified flip-flop input equations and/or
output equations from the Karnaugh maps
6)  implement the counter
Design of Synchronous Counters
Construct the state diagram

Construct the next-state

table

Decide the type of flip-flop to

be used

Obtain the required input for

each flip-flop to produce the
next state for the given
present state

Karnaugh map
implementation to obtain the
flip-flops input equations

Counter implementation
Design of Synchronous Counters (cont..)
Step 1 : State diagram for a 3-bit Gray code counter.
> State Diagram show the progression of state through which the
counter advances when it is clocked.

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Design of Synchronous Counters (cont..)

Step 2 : Next-state table for a 3-bit Gray code counter.

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0

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Design of Synchronous Counters (cont..)

Step 3 : Transition Table for a J-K flip-flop

Output Transitions Flip-flop Inputs

QN QN+1 J K
0 ! 0 0 X
0 ! 1 1 X
1 ! 0 X 1
1 ! 1 X 0

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Flip-Flop Excitation Tables

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Design of Synchronous Counters (cont..)
Step 4 : Draw K-Map for present-state J and K inputs.

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Design of Synchronous Counters (cont..)

Step 5 : Logic Expression for Flip Flop input

From K-MAP,
J0 = Q2’Q1’ + Q2Q1 K0 = Q2’Q1 + Q2Q1’
J1 = Q2’Q0 ,K1 = Q2Q0
J2 = Q1Q0’ ,K2 = Q1’Q0’

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Design of Synchronous Counters (cont..)

Step 6 : Design Three-bit Gray code counter

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Up/Down Synchronous Counters
A basic 3-bit up/down synchronous counter

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Up/Down Synchronous Counters (cont..)
Timing Diagram

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Up/Down Synchronous Counters (cont..)

How to design Up/Down Counter?

—  Use the same technique as designing a normal 1-way
counter.
—  But, in the next state table, you will have to included
another variable to indicate the direction that the
counter is operating
◦  Eg: Y variable (Y = 1 (up), Y = 0 (down))

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Up/Down Synchronous Counters (cont..)

Example:
Design a counter with the irregular binary count sequence as
shown in the state diagram. Use J-K flip-flops

To Solve, please remind step from Chapter 2:

—  Step 1 : specify state diagram given.

—  Step 2 : draw next-state table
—  Step 3 : make transition table
—  Step 4 : plotted K-MAP
—  Step 5 : simply in logic expression
—  Step 6 : implement the combinational logic

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Up/Down Synchronous Counters (cont..)

SOLUTION

—  Step 1 : Do State diagram for a 3-bit UP/DOWN Gray

code counter.
—  Step 2 : Do Next-state table for a 3-bit UP/DOWN Gray
code counter.
—  Step 3 : Do Transition Table for a J-K flip-flop

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Up/Down Synchronous Counters (cont..)

Step 4 : Draw K-Map for present-state J and K inputs.

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Step 6 :
Design
Three-bit
UP/DOWN
Gray code
counter

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 Cascade Counters
Example: Two cascaded counters (all J and K inputs are HIGH).

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 Cascade Counters (cont..)
Cascade Counters :
—  Counter can be connect in cascade to achieve higher
modulus operation.
—  Cascading ~ is the last stage output of one-counter
drive the output of next counter.
—  Based on 2 cascaded counter given.
- Asynchronous counter have positive edge-triggered
- all both JK input are high. So, output always toggle
when clock triggered.
- initial condition are LOW.
—  The final output modulus-8 counter (Q4) occurs once for
every 32 input clock pulse.
—  So, it can be classified as divide-by-32 counter.

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 Cascade Counters (cont..)
Example : A modulus-100 counter using two cascaded decade counters.

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Cascade Counters (cont..)
Modulus-100 :
—  Operate as Synchronous counter.
—  So, it use count enable (CTEN) and terminal count (TC)
function to achieve higher-modulus operation.
—  CTEN = G while TC = analog to ripple output (RCO).
—  This modulus-100 counter operation is :-
- TC output counter1 connect to CTEN input counter2.
- counter2 start from low on CTEN1 input until counter1 reach
last or TC=high.
- when TC=high, it will enable counter2. in this case, when 1st
clock pulse after counter1 reach TC(CLK10) counter2 goes
from initial state to 2nd state.
- it will continosly. Counter2 will complete one cycle after 100
clock pulses.
- overall modulus of 2 cascaded counter;
10 x 10 = 100

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 Cascade Counters (cont..)
Example : Three cascaded decade counters forming a divide-by-1000
frequency divider with intermediate divide- by-10 and divide-by-100
outputs.

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 Cascade Counters (cont..)
Solution : Three cascaded decade counters forming a divide-
by-1000 frequency divider with intermediate divide- by-10
and divide-by-100 outputs.

—  Shown cascaded counter called Count DOWN chain.

—  Example; Given basic clock frequency 1MHz to obtain
100kHz, 10kHz and 1kHz by using cascaded counter.

—  Solution: series of cascade decade counter can be formed.

—  If 1MHz signal divide by 10, so output = 100kHz
—  If 100kHz divide by 10, so output = 10kHz
—  If 10kHz divide by 10, output = 1kHz
—  So, we can used 3 cascade decade counter to produce 1kHz.
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 Cascade Counters (cont..)
Example: Determine the overall modulus of the two
cascaded counter for (a) and (b)

Solution :
For (a) the overall modulus for the 3 counter configuration
is 8 x 12 x 16 = 1536

For (b) the overall modulus for the 4 counter configuration

is 10 x 4 x 7 x 5 = 1400

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 Cascade Counters (cont..)
Example : A divide-by-40,000 counter using 74HC161 4-bit binary
counters. Note that each of the parallel data inputs is shown in binary
order (the right-most bit D0 is the LSB in each counter).

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Solution : Divide-by-40,000 couter using Logic ICs 74LS161.

—  Cascade counter with truncated sequence. How to achieve

overall modulus (divide-by-factor).
—  If counter (16-bit total) were cascade in full-modulus, so it will
be 2(16) = 65536.
—  Application is required divide-by-40,000 counter (or
modulus-40000).
- 65535 – 40000 = 25536.
- 25535 must select from moduluss sequence.
- 25535 = 63C0 H (in hexadecimal).
- so, it count from 25536 up to 65536 on each full cycle.
—  RCO output of right counter is inverted and apply to LOAD
input of each 4-bit counter.
—  So, 65535 = 1111 1111 1111 1111 B

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 Counter Decoding
* To determine when the counter is in a certain states in its
sequence by using decoders or logic gates.

Example : Decoding of state 6 (110).

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Counter Decoding (cont..)
Solution : Counter Decoding [Decoding of State 6 (110)]

—  Decoding of counter involve by using decoder AND logic

Gates to determine when the counter is in certain state.
—  Based on figure, when Q2=1, Q1=1 and Q0=0, a High
appears on output decoding gate indicate counter is at
State6.
—  It call active-HIGH decoding.
—  If replace AND-Gates with NAND-Gates, it will provide active-
LOW decoding.

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 Counter Decoding (cont..)
Example : Implement the decoding of binary state2 and binary
state7 of 3-bit synchronous counter. Show entire counter timing
diagram and output waveform of decoding gates.

Solution :
—  Binary state2 = Q2’ Q1 Q0’ = (010).
—  Binary state7 = Q2 Q1 Q0 = (111).
—  A 3-bit counter with active-HIGH decoding of count2 and
count7.

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Solution Design : A
3-bit counter with
active-HIGH
decoding of count 2
and count 7.

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Shift Register Counters
—  shift register counter – shift register with serial output
connected back to the serial input to produce special
sequences.

—  Classified as counters because they exhibit a specified

sequences of states

—  Common types of shift register counters:

§  Johnson counter
§  Ring counter

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 Shift Register Counters (cont..)
—  In a Johnson counter,
§  the complement output of the last D flip-flop is connected
back to the D input of the first flip-flop (it can be
implemented with other types of flip-flops as well).
§  the Q output of each flip-flop is connected to the D input
of the next flip-flop (assuming that D flip-flops are used).

4-bit Johnson counter using D flip-flop

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Shift Register Counters (cont..)

4-bit Johnson counterusing J-K flip-flop

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 Shift Register Counters (cont..)
—  As an example, if the counter starts at 0, this feedback
arrangement produces a characteristic sequence of eight
different states as shown in the given table for a 4-bit device.

4 bit Johnson sequence

•  As shown in the given table, if the counter starts at 0, it
will “fill up” with 1s from left to right, and then it will “fill
up” with 0s again.
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Shift Register Counters (cont..)

4 bit timing sequence

•  The implementation of a Johnson counter is the same

regardless of the number of stages.

•  In general, a Johnson counter will produce a modulus of

2n, where n is the number of stages in the counter.
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Shift Register Counters (cont..)

5-bit Johnson counter using D flip-flop

5-bit timing sequence

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Shift Register Counters (cont..)

5-bit Johnson sequence

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 Shift Register Counters (cont..)
•  In a ring counter, the interstage connections are the same
as the Johnson counter, except that Q rather than Q is
fed back from the last stage.

A TEN bit ring counter

•  For every clock pulse, the stored bits will move to the
respective next stages.
•  The bits are retained in the counter and are simply shifted
“around the ring”. 66
Shift Register Counters (cont..)
—  An example of a sequence produced by the 10 bit ring counter
when the first flip-flop is initially preset to 1 and the rest of
the flip-flops are cleared.

Sequence of a TEN bit ring counter

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Counter Application

Counter Application :
A.  Digital Clock.
B.  Automobile Parking Control.
C.  Parallel to Serial Data Conversion
(MULTIPLEXING).

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Counter Application (cont..)
(A) Digital Clock

—  Logic diagram display second, minutes and hours.

—  60Hz sinusoidal AC voltage connect to 60Hz pulse
waveform and divide to 1Hz by using divide-by-60
(include divide-by-10 and divide-by-6).
—  Both second and minutes produce divide-by-60
counter and it will count from 0 to 59.
—  This digital clock use synchronous decade counter
in implementation.

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Simplified logic diagram for a 12-hour digital clock.

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Counter Application (cont..)
Logic diagram of typical divide-by-60 counter using 74LS160A
synchronous decade counters. Note that the outputs are in
binary order (the right-most bit is the LSB).

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Counter Application (cont..)
Digital Clock = hours definition
—  Hours counter implement with decade counter and
flip-flops.
—  Initially both decade counter flip-flops = Reset.
—  Decode-12 and decode-9 output = High, so decade
counter through all state from 0 to 9 and recycle
from 9 to 0.
—  Flip-flops goes SET state (J=1, K=0) so it will
illuminate (nyala) segment 1 on 10-hours display.
—  In state12, Q2 output decade counter is High, so
flip-flops still SET and decode-12 gates output =
LOW.
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Logic diagram for hours counter and decoders. Note that on the
counter inputs and outputs, the right-most bit is the LSB.

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 Counter Application (cont..)
(B) Automobile Parking Control

—  Use up/down counter to solve problem.

—  Monitor available space in the one-100 space
parking garage and provide full condition by display
sign and lower gate bar at entrance.
—  The system consist :-
- opto-electronic sensor at entrance and exit garage.
- up/down counter.
- interface circuit use counter output to turn full-sign
on/off and lower/raise gate bar at entrance.

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Functional block diagram for parking garage control.

Logic diagram for modulus-100 up/down counter for

automobile parking control.

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Counter Application (cont..)
Automobile Parking Control

—  up/down use 2-cascade IC.

—  Counter initial preset to 0 by using parallel data input.
—  Each car enter garage break a light beam and activate sensor.
Positive-pulse set SR latches on leading edge.
—  Low on Q’ output latches put counter UP mode.
—  Sensor pulse goes through NOR-Gates and clock the counter on
LOW-to-HIGH transition.
—  When cars enter garage, counter increase by 1.
—  When count last stage (100 unit) the MAX/MIN = High and it activate
light Full-Sign and low gate bar.
—  When car exit, sensor produce (positive pulse) which Reset SR
latches and put counter DOWN mode. So, it will decrease.
—  If garage full and car leave, MAX/MIN = Low, so it will turning off
Full-Sign and raising the bar gate.

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Counter Application (cont..)
(C) Parallel to Serial Data Conversion
(MULTIPLEXING)

—  Parallel data bit on MUX input convert to serial data bit

on single transmission line.
—  Parallel data = a group of bit appear on parallel line in
time sequence.
—  Serial data = a group of bit appear on single line in time
sequence.
—  Counter goes binary sequence from 0 to 7.
- each bit start D0.
- select and pass through MUX output line.
- after 8 clock pulses, data byte has been convert to
serial format and sent out transmission lines.

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Counter Application (cont..)
Parallel-to-serial data conversion logic.

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Example : Parallel-to-
serial conversion timing for
the previous circuit

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