EC1208-DIGITAL LABORATORY

II YEAR/III SEM- CSE

M.A.M SCHOOL OF ENGINEERING

SIRUGANUR, TRICHY
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING

Syllabus
s.no Name of the experiment Page no.
1. Verification of Boolean Theorems using Digital Logic Gates 4
DIGITAL LAB 2. Design and Implementation of Combinational Circuits 10
using Basic Gates for Arbitrary Functions, Code
CS2207 Converters, Etc
3. Design and Implementation of 4-Bit Binary Adder / 17
LAB MANUAL Subtractor using Basic Gates and MSI Devices
4. Design and Implementation of Parity Generator / Checker 24
using Basic Gates and MSI Devices.
5. Design and Implementation of Magnitude Comparator. 21
6. Design and Implementation of Application using 26
Multiplexers/Demultiplexers.
7. Design and Implementation of Shift Registers. 33
8. Design and Implementation of Synchronous and 31
Asynchronous Counters.
9. Simulation of Combinational Circuits using Hardware 35
Description Language (VHDL / Verilog HDL Software
Required).
10. Simulation of Sequential Circuits using HDL (VHDL / 37
Verilog HDL Software Required).

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EXP NO: 1 STUDY OF LOGIC GATES OR GATE:

The OR gate performs a logical addition commonly known as OR
AIM: function. The output is high when any one of the inputs is high. The output
To study about logic gates and verify their truth tables. is low level when both the inputs are low.
NOT GATE:
APPARATUS REQUIRED:
The NOT gate is called an inverter. The output is high when
SL No. COMPONENT SPECIFICATION QTY
the input is low. The output is low when the input is high.
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1 NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1 when both inputs are low and any one of the input is low .The output is low
5. NOR GATE IC 7402 1 level when both inputs are high.
6. X-OR GATE IC 7486 1 NOR GATE:
7. NAND GATE 3 I/P IC 7410 1 The NOR gate is a contraction of OR-NOT. The output is high
8. IC TRAINER KIT - 1 when both inputs are low. The output is low when one or both inputs are
9. PATCH CORD - 14
high.

THEORY: X-OR GATE:

The output is high when any one of the inputs is high. The output
Circuit that takes the logical decision and the process are called
is low when both the inputs are low and both the inputs are high.
logic gates. Each gate has one or more input and only one output.OR, AND
PROCEDURE:
and NOT are basic gates. NAND, NOR and X-OR are known as universal (i). Connections are given as per circuit diagram.
gates. Basic gates form these gates.
(ii). Logical inputs are given as per circuit diagram.
AND GATE: (iii). Observe the output and verify the truth table.
The AND gate performs a logical multiplication commonly known
as AND function. The output is high when both the inputs are high. The
output is low level when any one of the inputs is low.

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AND GATE:
SYMBOL: PIN DIAGRAM: NOT GATE:
SYMBOL: PIN DIAGRAM:

OR GATE: X-OR GATE :

SYMBOL : PIN DIAGRAM :

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2-INPUT NAND GATE: NOR GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

RESULT:
Thus the logic gates were verified.

EXP NO: 2 VERIFICATION OF BOOLEAN THEOREMS

USING LOGIC GATES

AIM:
To verification of Boolean theorems using logic gates.

THEORY:
BASIC BOOLEAN LAWS
1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

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2. Associative Law AB+A'C+BC = AB+A'C

The binary operator OR, AND is said to be associative if, Proof: AB+A'C+BC = AB+A'C+BC (A+A')
1. A+(B+C) = (A+B)+C = AB+A'C+ABC+A'BC
2. A.(B.C) = (A.B).C = AB(1+C)+A'C(1+B)
= AB+A'C. (using OR law,
3. Distributive Law 1+C=1 and 1+B=1)
The binary operator OR, AND is said to be distributive if, Design
1. A+(B.C) = (A+B).(A+C) 1. Absorption Law
2. A.(B+C) = (A.B)+(A.C) A+AB = A

4. Absorption Law

1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. A.A = A 2. Involution (or) Double complement Law

7. Complementary Law A=A

1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the
individual complements.
A+B = A.B 3. Idempotent Law
2. The complement of the product is equal to the sum of the individual 1. A+A = A
complements.
A.B = A+B

9. Consensus Theorem
Consensus theorem is used to simplify the Boolean expression by
eliminating the redundant terms.

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2. A.A = A PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

4. Demorgan’s Law
RESULT:
A+B = A.B
Thus the above stated Boolean laws are verified.

EXP NO: 3 DESIGN OF ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and
5. Distributive Law full subtractor circuits and verify the truth table using logic gates.
A+(B.C) = (A+B).(A+C) APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:
HALF ADDER:
APPARATUS REQUIRED:
Digital trainer kit, IC7408 (AND gate), IC7432 (OR gate), IC7486 A half adder has two inputs for the two bits to be added and two
(Ex-OR gate), and connecting wires.
outputs one from the sum ‘ S’ and other from the carry ‘ c’ into the higher

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adder position. Above circuit is called as a carry signal from the addition of half subtractor and the second term is the inverted difference output of first
X-OR.
the less significant bits sum from the X-OR Gate the carry out from the
LOGIC DIAGRAM:
AND gate. HALF ADDER

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic

sum of input; it consists of three inputs and two outputs. A full adder is
useful to add three bits at a time but a half adder cannot do so. In full adder
sum output will be taken from X-OR Gate, carry output will be taken from
OR Gate.

HALF SUBTRACTOR:
TRUTH TABLE:
The half subtractor is constructed using X-OR and AND Gate. The
A B CARRY SUM
half subtractor has two input and two outputs. The outputs are difference
and borrow. The difference can be applied using X-OR Gate, borrow output 0 0 0 0
0 1 0 1
can be implemented using an AND Gate and an inverter. 1 0 0 1
1 1 1 0
FULL SUBTRACTOR:
K-Map for SUM: K-Map for CARRY:
The full subtractor is a combination of X-OR, AND, OR, NOT
Gates. In a full subtractor the logic circuit should have three inputs and two
outputs. The two half subtractor put together gives a full subtractor .The
first half subtractor will be C and A B. The output will be difference output
of full subtractor. The expression AB assembles the borrow output of the

SUM = A’B + AB’ CARRY = AB

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LOGIC DIAGRAM: K-Map for SUM:

FULL ADDER
FULL ADDER USING TWO HALF ADDER

SUM = A’B’C + A’BC’ + ABC’ + ABC

TRUTH TABLE: K-Map for CARRY:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
CARRY = AB + BC + AC
1 1 1 1 1

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K-Map for BORROW:

LOGIC DIAGRAM:
HALF SUBTRACTOR

BORROW = A’B

LOGIC DIAGRAM:
FULL SUBTRACTOR:

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

TRUTH TABLE:
K-Map for DIFFERENCE: A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
DIFFERENCE = A’B + AB’ 1 1 1 1 1

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K-Map for Difference: RESULT:

Thus the half adder, full adder, half subtractor & full subtractor
were verified.

EXP NO: 4

DESIGN & IMPLEMENTATION OF CODE CONVERTOR

AIM:
To design and implement 4-bit
Difference = A’B’C + A’BC’ + AB’C’ + ABC (i) Binary to gray code converter
(ii) Gray to binary code converter
K-Map for Borrow: (iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
Borrow = A’B + BC + A’C 6. PATCH CORDS - 35

PROCEEDURE: THEORY:
(i) Connections are given as per circuit diagram. The availability of large variety of codes for the same discrete
(ii) Logical inputs are given as per circuit diagram. elements of information results in the use of different codes by different
systems. A conversion circuit must be inserted between the two systems if
(iii) Observe the output and verify the truth table.
each uses different codes for same information. Thus, code converter is a

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circuit that makes the two systems compatible even though each uses LOGIC DIAGRAM:
different binary code. BINARY TO GRAY CODE CONVERTOR
The bit combination assigned to binary code to gray code. Since
each code uses four bits to represent a decimal digit. There are four inputs
and four outputs. Gray code is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output
variables are designated as C3, C2, C1, Co. from the truth table,
combinational circuit is designed. The Boolean functions are obtained from
K-Map for each output variable.
A code converter is a circuit that makes the two systems
compatible even though each uses a different binary code. To convert from
binary code to Excess-3 code, the input lines must supply the bit
combination of elements as specified by code and the output lines generate
K-Map for G3:
the corresponding bit combination of code. Each one of the four maps
represents one of the four outputs of the circuit as a function of the four
input variables.
A two-level logic diagram may be obtained directly from the
Boolean expressions derived by the maps. These are various other
possibilities for a logic diagram that implements this circuit. Now the OR
gate whose output is C+D has been used to implement partially each of
three outputs.

G3 = B3

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K-Map for G2: K-Map for G0:

TRUTH TABLE:
Binary input Gray code output
B3 B2 B1 B0 G3 G2 G1 G0
K-Map for G1:
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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LOGIC DIAGRAM: K-Map for B2:

GRAY CODE TO BINARY CONVERTOR

K-Map for B1:

K-Map for B3:

B3 = G3

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K-Map for B0: LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE:
Gray CodeBinary Code
G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0 K-Map for E3:

0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
E3 = B3 + B2 (B0 + B1)

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K-Map for E2: K-Map for E0:

TRUTH TABLE:
BCD input Excess – 3 output
B3 B2 B1 B0 G3 G2 G1 G0
K-Map for E1:
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

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LOGIC DIAGRAM: K-Map for B:

EXCESS-3 TO BCD CONVERTOR

K-Map for C:

K-Map for A:

A = X1 X2 + X3 X4 X1

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K-Map for D: PROCEDURE:

(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:
Thus the code converters were designed and verified using the
corresponding truth table.

EXP NO: 5 DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
TRUTH TABLE:
Excess – 3 Input BCD Output 2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
B3 B2 B1 B0 G3 G2 G1 G0 3. IC TRAINER KIT - 1
0 0 1 1 0 0 0 0 4. PATCH CORDS - 40
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0 THEORY:
0 1 1 0 0 0 1 1
4 BIT BINARY ADDER:
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1 A binary adder is a digital circuit that produces the arithmetic sum
1 0 0 1 0 1 1 0 of two binary numbers. It can be constructed with full adders connected in
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0 cascade, with the output carry from each full adder connected to the input
1 1 0 0 1 0 0 1 carry of next full adder in chain. The augends bits of ‘A’ and the addend
bits of ‘B’ are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits. The carries are connected in

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chain through the full adder. The input carry to the adder is C0 and it ripples PIN DIAGRAM FOR IC 7483:
through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters,
placed between each data input ‘B’ and the corresponding input of full
adder. The input carry C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one
circuit with one common binary adder. The mode input M controls the
operation. When M=0, the circuit is adder circuit. When M=1, it becomes
subtractor. LOGIC DIAGRAM:
4 BIT BCD ADDER: 4-BIT BINARY ADDER
Consider the arithmetic addition of two decimal digits in BCD,
together with an input carry from a previous stage. Since each input digit
does not exceed 9, the output sum cannot be greater than 19, the 1 in the
sum being an input carry. The output of two decimal digits must be
represented in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in
BCD. The 2 decimal digits, together with the input carry, are first added in
the top 4 bit adder to produce the binary sum.

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LOGIC DIAGRAM: LOGIC DIAGRAM:

4-BIT BINARY SUBTRACTOR 4-BIT BINARY ADDER/SUBTRACTOR

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LOGIC DIAGRAM:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

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K MAP PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:
Thus the combinational circuits-
(i) Half Adder (2 bits)
(ii) Full Adder (3 bits) were designed and implemented using the
logic gates.

EXP NO: 6 DESIGN AND IMPLEMENTATION OF

MAGNITUDE COMPARATOR

Y = S4 (S3 + S2) AIM:

To design and implement
TRUTH TABLE: (i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.
BCD SUM CARRY APPARATUS REQUIRED:
S4 S3 S2 S1 C
0 0 0 0 0 Sl.No. COMPONENT SPECIFICATION QTY.
0 0 0 1 0 1. AND GATE IC 7408 2
0 0 1 0 0 2. X-OR GATE IC 7486 1
0 0 1 1 0 3. OR GATE IC 7432 1
0 1 0 0 0
4. NOT GATE IC 7404 1
0 1 0 1 0
0 1 1 0 0 5. 4-BIT MAGNITUDE IC 7485 2
0 1 1 1 0 COMPARATOR
1 0 0 0 0 6. IC TRAINER KIT - 1
1 0 0 1 0 7. PATCH CORDS - required
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1 THEORY:
1 1 0 1 1 The comparison of two numbers is an operator that determine one
1 1 1 0 1 number is greater than, less than (or) equal to the other number. A
1 1 1 1 1

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magnitude comparator is a combinational circuit that compares two LOGIC DIAGRAM:

numbers A and B and determine their relative magnitude. The outcome of 2 BIT MAGNITUDE COMPARATOR
the comparator is specified by three binary variables that indicate whether
A>B, A=B (or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a
combinational circuit designated by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude
of pairs of significant digits starting from most significant position. A is 0
and that of B is 0.
We have A<B, the sequential comparison can be expanded as

A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of
two BCD digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
   
x3 x2 x1 x0

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K MAP

TRUTH TABLE
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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PIN DIAGRAM FOR IC 7485: TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0 1 0
0000 0000
0001 0000 1 0 0
0001 0000
0000 0001 0 0 1
0000 0001
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the 2-bit and 8-bit magnitude comparator was designed and
verified using the logic gates.
LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR
EXP NO: 7 PARITY CHECKER /GENERATOR
AIM:
To design and verify the truth table of a three bit Odd Parity
generator and checker.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit - 1
2. EX-OR gate IC 7486
3. NOT gate IC 7404
4. Connecting wires required

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THEORY: P( A, B, C) = Σ (0, 3, 5, 6)
A parity bit is used for the purpose of detecting errors during Also written as,
transmission of binary information. A parity bit is an extra bit included P = A’B’C’ + A’BC + AB’C + ABC’ = (A B C) ‘
with a binary message to make the number of 1’s either odd or even. The CIRCUIT DIAGRAM:
message including the parity bit is transmitted and then checked at the ODD PARITY GENERATOR
receiving end for errors.
An error is detected if the checked parity does not correspond with
the one transmitted. The circuit that generates the parity bit in the
transmitter is called a parity generator and the circuit that checks the parity
in the receiver is called a parity checker.In even parity the added parity bit
will make the total number of 1’s an even amount and in odd parity the
added parity bit will make the total number of 1’s an odd amount. In a three
bit odd parity generator the three bits in the message together with the parity
bit are transmitted to their destination, where they are applied to the parity
checker circuit. The parity checker circuit checks for possible errors in the
transmission.
ODD PARITY CHECKER
TRUTH TABLE:
Since the information was transmitted with odd parity the four bits
INPUT OUTPUT
received must have an odd number of 1’s. An error occurs during the ( four bit (Parity
transmission if the four bits received have an even number of 1’s, indicating S.No message error
that one bit has changed during transmission. The output of the parity Received ) check)
checker is denoted by PEC (parity error check) and it will be equal to 1 if an A B C P X
error occurs, i.e., if the four bits received has an even number of 1’s. 1. 0 0 0 0 1
2. 0 0 0 1 0
ODD PARITY GENERATOR
3. 0 0 1 0 0
TRUTH TABLE:
4. 0 0 1 1 1
5. 0 1 0 0 0
6. 0 1 0 1 1
INPUT OUTPUT 7. 0 1 1 0 1
( Three bit ( Odd Parity 8. 0 1 1 1 0
S.No
message) bit) 9. 1 0 0 0 0
10. 1 0 0 1 1
A B C P 11. 1 0 1 0 1
1. 0 0 0 1 From the truth table the 12. 1 0 1 1 0
2. 0 0 1 0 expression for the 13. 1 1 0 0 1
3. 0 1 0 0 output parity bit is,
4. 0 1 1 1
5. 1 0 0 0
6. 1 0 1 1
7. 1 1 0 1
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14. 1 1 0 1 0 EXP NO: 8 DESIGN AND IMPLEMENTATION OF

15. 1 1 1 0 0 MULTIPLEXER AND DEMULTIPLEXER
16. 1 1 1 1 1 AIM:
To design and implement multiplexer and demultiplexer using
From the truth table the expression for the output parity checker bit is,
logic gates and study of IC 74150 and IC 74154.
X (A, B, C, P) = Σ (0, 3, 5, 6, 9, 10, 12, 15) APPARATUS REQUIRED:
The above expression is reduced as,
Sl.No. COMPONENT SPECIFICATION QTY.
X = (A B C P) 1. 3 I/P AND GATE IC 7411 2
CIRCUIT DIAGRAM: 2. OR GATE IC 7432 1
ODD PARITY CHECKER
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - required

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information
units over a smaller number of channels or lines. A digital multiplexer is a
combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The selection of a particular
input line is controlled by a set of selection lines. Normally there are 2n
PROCEDURE: input line and n selection lines whose bit combination determine which
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V input is selected.
supply. DEMULTIPLEXER:
3. Apply the inputs and verify the truth table for the Parity generator
and checker. The function of Demultiplexer is in contrast to multiplexer
RESULT: function. It takes information from one line and distributes it to a given
The design of the three bit odd Parity generator and checker circuits was
done and their truth tables were verified.

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number of output lines. For this reason, the demultiplexer is also known as a CIRCUIT DIAGRAM FOR MULTIPLEXER:
data distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of
the AND gates. The data select lines enable only one gate at a time and the
data on the data input line will pass through the selected gate to the
associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

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LOGIC DIAGRAM FOR DEMULTIPLEXER 1 0 0 0 0 0 0

1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0

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PROCEDURE: flops are not activated at same time which results in asynchronous
(i) Connections are given as per circuit diagram. operation.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table. PIN DIAGRAM FOR IC 7476:
RESULT:
Thus the multiplexer and demultiplexer was studied and verified.

EXPT NO: 9 CONSTRUCTION AND VERIFICATION OF 4 BIT

RIPPLE COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER
AIM:
To design and verify 4 bit ripple counter mod 10/ mod 12 ripple
counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. NAND GATE IC 7400 1 LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
3. IC TRAINER KIT - 1
4. PATCH CORDS - required
THEORY:
A counter is a register capable of counting number of clock pulse
arriving at its clock input. Counter represents the number of clock pulses
arrived. A specified sequence of states appears as counter output. This is the
main difference between a register and a counter. There are two types of
counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q
output of previous stage. A soon the clock of second stage is triggered by
output of first stage. Because of inherent propagation delay time all flip

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TRUTH TABLE: LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
TRUTH TABLE:
8 0 0 0 1
CLK QA QB QC QD
9 1 0 0 1
0 0 0 0 0
10 0 1 0 1
1 1 0 0 0
11 1 1 0 1
2 0 1 0 0
12 0 0 1 1
3 1 1 0 0
13 1 0 1 1
4 0 0 1 0
14 0 1 1 1
5 1 0 1 0
15 1 1 1 1
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

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LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER: PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT:
Thus the 4-bit counter, Mod-10 and Mod-12 ripple counters was
designed and implemented.

EXP NO: 10 DESIGN AND IMPLEMENTATION OF 3 BIT

SYNCHRONOUS UP/DOWN COUNTER
AIM:
TRUTH TABLE: To design and implement 3 bit synchronous up/down counter.
CLK QA QB QC QD APPARATUS REQUIRED:
0 0 0 0 0 Sl.No. COMPONENT SPECIFICATION QTY.
1 1 0 0 0 1. JK FLIP FLOP IC 7476 2
2 0 1 0 0 2. 3 I/P AND GATE IC 7411 1
3 1 1 0 0 3. OR GATE IC 7432 1

4 0 0 1 0 4. XOR GATE IC 7486 1

5. NOT GATE IC 7404 1
5 1 0 1 0
6. IC TRAINER KIT - 1
6 0 1 1 0
7. PATCH CORDS - 35
7 1 1 1 0
8 0 0 0 1 THEORY:
9 1 0 0 1 A counter is a register capable of counting number of clock pulse

10 0 1 0 1 arriving at its clock input. Counter represents the number of clock pulses

11 1 1 0 1 arrived. An up/down counter is one that is capable of progressing in

12 0 0 0 0 increasing order or decreasing order through a certain sequence. An

up/down counter is also called bidirectional counter. Usually up/down

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operation of the counter is controlled by up/down signal. When this signal is CHARACTERISTICS TABLE:
high counter goes through up sequence and when up/down signal is low Q Qt+1 J K
counter follows reverse sequence. 0 0 0 X
K MAP 0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:

STATE DIAGRAM:

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TRUTH TABLE: EXP NO: 11 DESIGN AND IMPLEMENTATION OF SHIFT

Input Present Next State A B C REGISTER
Up/Down State Q A+1 Q B+1 QC+1 JA KA JB KB JC KC AIM:
Q A Q B QC To design and implement
0 0 0 0 1 1 1 1 X 1 X 1 X (i) Serial in serial out
0 1 1 1 1 1 0 X 0 X 0 X 1 (ii) Serial in parallel out
0 1 1 0 1 0 1 X 0 X 1 1 X (iii) Parallel in serial out
0 1 0 1 1 0 0 X 0 0 X X 1 (iv) Parallel in parallel out
0 1 0 0 0 1 1 X 1 1 X 1 X APPARATUS REQUIRED:
0 0 1 1 0 1 0 0 X X 0 X 1 Sl.No. COMPONENT SPECIFICATION QTY.
0 0 1 0 0 0 1 0 X X 1 1 X 1. D FLIP FLOP IC 7474 2
0 0 0 1 0 0 0 0 X 0 X X 1 2. OR GATE IC 7432 1
1 0 0 0 0 0 1 0 X 0 X 1 X
3. IC TRAINER KIT - 1
1 0 0 1 0 1 0 0 X 1 X X 1
4. PATCH CORDS - 35
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
THEORY:
1 1 0 0 1 0 1 X 0 0 X 1 X
A register is capable of shifting its binary information in one or
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X both directions is known as shift register. The logical configuration of shift
1 1 1 1 0 0 0 X 1 X 1 X 1 register consist of a D-Flip flop cascaded with output of one flip flop
connected to input of next flip flop. All flip flops receive common clock
PROCEDURE: pulses which causes the shift in the output of the flip flop. The simplest
(i) Connections are given as per circuit diagram.
possible shift register is one that uses only flip flop. The output of a given
(ii) Logical inputs are given as per circuit diagram. flip flop is connected to the input of next flip flop of the register. Each clock

(iii) Observe the output and verify the truth table. pulse shifts the content of register one bit position to right.

RESULT: Thus the 3-bit synchronous up/down counters was

implemented successfully.

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PIN DIAGRAM: 6 X 0
7 X 1

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
TRUTH TABLE: 1 1 1 0 0 0
CLK Serial in Serial out 2 0 0 1 0 0
1 1 0 3 0 0 0 1 1
2 0 0 4 1 1 0 0 1
3 0 0
4 1 1
5 X 0

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LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT: TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
TRUTH TABLE:
RESULT:
CLK Q3 Q2 Q1 Q0 O/P Thus the implementation of shift registers using flip flops was
0 1 0 0 1 1 completed successfully.
1 0 0 0 0 0
EXP NO: 12 SIMULATION OF COMBINATIONAL CIRCUITS
2 0 0 0 0 0 USING HDL
3 0 0 0 0 1 AIM:
LOGIC DIAGRAM: To write a verilog code for half adder, full adder and multiplexer.
PARALLEL IN PARALLEL OUT:
TOOLS REQUIRED:
Xilinx 9.2
PROGRAM:
HALF ADDER
A S=A⊕B
B

Cout=AB

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SIMULATED OUTPUT:

SIMULATED OUTPUT:

FULL ADDER:
MULTIPLEXER:

S0

S1
S0

S1
I0
7411

'S +

'S Y'+
Y= I0 S0
I1

1
I1 S0
I2
I3

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RESULT:
Thus the verilog code for half adder, full adder and multiplexer
were simulated and verified.

EXP NO: 13 SIMULATION OF SEQUENTIAL CIRCUITS

USING HDL
AIM:
To write a verilog code for RS, D, JK flip flop and up counter

TOOLS REQUIRED:

Xilinx 9.2

PROGRAM:
RS FLIP FLOP:

R
Q

7408
7402

SIMULATED OUTPUT: CP

Q'
1
S

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SIMULATED OUTPUT:

SIMULATED OUTPUT:

JK FLIP FLOP:

D FLIP FLOP: K
Q
D 7411
Q 7402
CP
7408
7402

Q'
J

1 1 Q'

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UP COUNTER:

SIMULATED OUTPUT:

SIMULATED OUTPUT:

RESULT:
Thus the verilog code for RS, D, JK flip flop and up counter
were simulated and verified.

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EX NO: 14 IMPLEMENTATION OF BOOLEAN FUNCTIONS From the K-Map,

F = B’ C’ + D’ B’ + A’ C’ D
AIM: Since we are using only two input logic gates the above expression can be
To design the logic circuit and verify the truth table of the given re-written as,
Boolean expression, F = C’ (B’ + A’ D) + D’ B’
F (A, B, C, D) = Σ (0, 1, 2, 5, 8, 9, 10) Now the logic circuit for the above equation can be drawn.

[Design can be changed by changing the Boolean expression] CIRCUIT DIAGRAM:

APPARATUS REQUIRED:

S.NO COMPONENT SPECIFICATION QTY.

1. IC TRAINER KIT 1
2. AND GATE IC 7408 3
3. OR GATE IC 7432 2
4. NOT GATE IC 7404 4
5. EX-OR GATE IC 7486
6. PATCH CORDS - REQUIRED

DESIGN:
Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)
The output function F has four input variables hence a four variable
Karnaugh Map is used to obtain a simplified expression for the output as
shown,

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TRUTH TABLE:

INPUT OUTPUT
S.No
A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0

PROCEDURE:
1. Connections are given as per the circuit diagram
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V
supply.
3. Apply the inputs and verify the truth table for the given Boolean
expression.
RESULT:
The truth table of the given Boolean expression was verified.

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