0% found this document useful (0 votes)

992 views

Arm STM32WB55 PDF

Uploaded by

tung

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

992 views

Arm STM32WB55 PDF

Uploaded by

tung

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 178

STM32WB55xx

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4

with FPU, Bluetooth® 5 and 802.15.4 radio solution
Datasheet - production data

Features
.
• Includes ST state-of-the-art patented
technology
• Radio
UFQFPN48 VFQFPN68
– 2.4 GHz
7 x 7 mm solder pad 8 x 8 mm solder pad
– RF transceiver supporting Bluetooth® 5
specification, IEEE 802.15.4-2011 PHY FBGA

and MAC, supporting Thread and

ZigBee® 3.0
– RX Sensitivity: -96 dBm (Bluetooth® Low WLCSP100 BGA129
Energy at 1 Mbps), -100 dBm (802.15.4) 0.4 mm pitch 0.5 mm pitch
– Programmable output power up to +6 dBm from Flash memory, frequency up to 64 MHz,
with 1 dB steps MPU, 80 DMIPS and DSP instructions
– Integrated balun to reduce BOM
• Performance benchmark
– Support for 2 Mbps
– 1.25 DMIPS/MHz (Drystone 2.1)
– Dedicated Arm® 32-bit Cortex® M0 + CPU
– 219.48 Coremark® (3.43 Coremark/MHz
for real-time Radio layer
@64 MHz)
– Accurate RSSI to enable power control
• Energy benckmark
– Suitable for systems requiring compliance
with radio frequency regulations ETSI EN – 303 ULPMark™ CP score
300 328, EN 300 440, FCC CFR47 Part 15 • Supply and reset management
and ARIB STD-T66 – High efficiency embedded SMPS
– Support for external PA step-down converter with intelligent bypass
– Available integrated passive device (IPD) mode
companion chip for optimized matching – Ultra-safe, low-power BOR (brownout
solution MLPF-WB55-01E3 reset) with five selectable thresholds
• Ultra-low-power platform – Ultra-low-power POR/PDR
– 1.71 V to 3.6 V power supply – Programmable voltage detector (PVD)
– – 40 °C to 85 / 105 °C temperature ranges – VBAT mode with RTC and backup registers
– 13 nA shutdown mode • Clock sources
– 600 nA Standby mode + RTC + 32 KB – 32 MHz crystal oscillator with integrated
RAM trimming capacitors (Radio and CPU clock)
– 2.1 µA Stop mode + RTC + 256 KB RAM – 32 kHz crystal oscillator for RTC (LSE)
– Active-mode MCU: < 53 µA / MHz when RF – Internal low-power 32 kHz (±5%) RC (LSI1)
and SMPS On – Internal low-power 32 kHz (stability
– Radio: Rx 4.5 mA / Tx at 0 dBm 5.2 mA ±500 ppm) RC (LSI2)
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, – Internal multispeed 100 kHz to 48 MHz
adaptive real-time accelerator (ART oscillator, auto-trimmed by LSE (better than
Accelerator™) allowing 0-wait-state execution ±0.25% accuracy)

October 2019 DS11929 Rev 5 1/178

This is information on a product in full production. www.st.com
STM32WB55xx

– High speed internal 16 MHz factory – Touch sensing controller, up to 18 sensors

trimmed RC (±1%) – LCD 8x40 with step-up converter
– 2x PLL for system clock, USB, SAI and – 1x 16-bit, four channels advanced timer
ADC – 2x 16-bits, two channels timer
• Memories – 1x 32-bits, four channels timer
– Up to 1 MB Flash memory with sector – 2x 16-bits ultra-low-power timer
protection (PCROP) against R/W – 1x independent Systick
operations, enabling authentic Bluetooth®
– 1x independent watchdog
Low Energy and 802.15.4 SW stack
– 1x window watchdog
– Up to 256 KB SRAM, including 64 KB with
hardware parity check • Security and ID
– 20x32-bit backup register – Secure firmware installation (SFI) for
– Boot loader supporting, USART, SPI, I2C Bluetooth® Low Energy and 802.15.4 SW
and USB interfaces stack
– OTA (Over the air) Bluetooth® Low Energy – 3x hardware encryption AES maximum
and 802.15.4 update 256-bit for the application, the Bluetooth®
Low Energy and IEEE802.15.4
– Quad SPI memory interface with XIP
– Customer key storage / key manager
• Rich analog peripherals (down to 1.62 V) services
– 12-bit ADC 4.26 Msps, up to 16-bit with – HW public key authority (PKA)
hardware oversampling, 200 µA/Msps
– Cryptographic algorithms: RSA,
– 2x ultra-low-power comparator Diffie-Helman, ECC over GF(p)
– Accurate 2.5 V or 2.048 V reference – True random number generator (RNG)
voltage buffered output
– Sector protection against R/W operation
• System peripherals (PCROP)
– Inter processor communication controller – CRC calculation unit
(IPCC) for communication with Bluetooth® – Die information: 96-bit unique ID
Low Energy and 802.15.4
– IEEE 64-bit unique ID. Possibility to derive
– HW semaphores for resources sharing 802.15.4 64-bit and Bluetooth® Low Energy
between CPUs 48-bit EUI
– 2x DMA controllers (7x channels each)
• Up to 72 fast I/Os, 70 of them 5 V-tolerant
supporting ADC, SPI, I2C, USART, QSPI,
SAI, AES, Timers • Development support
– 1x USART (ISO 7816, IrDA, SPI Master, – Serial wire debug (SWD), JTAG for the
Modbus and Smartcard mode) Application processor
– 1x LPUART (low power) – Application cross trigger with input and
– 2x SPI 32 Mbit/s output
– 2x I2C (SMBus/PMBus) – Embedded Trace Macrocell™ for
application
– 1x SAI (dual channel high quality audio)
– 1x USB 2.0 FS device, crystal-less, BCD • All packages are ECOPACK2 compliant
and LPM

Table 1. Device summary

Reference Part numbers

STM32WB55CC, STM32WB55RC, STM32WB55VC

STM32WB55xx STM32WB55CE, STM32WB55RE, STM32WB55VE
STM32WB55CG, STM32WB55RG, STM32WB55VG

2/178 DS11929 Rev 5

STM32WB55xx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 17
3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.2 BLE general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.3 802.15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.4 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.5 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.1 Power supply distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7.3 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.4 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.5 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7.6 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DS11929 Rev 5 3/178

6
Contents STM32WB55xx

3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41

3.13.2 Extended Interrupts and Events Controller (EXTI) . . . . . . . . . . . . . . . . 42
3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.15 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.17 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.19 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.20.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 47
3.20.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 48
3.20.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.20.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 49
3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 51
3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 51
3.25 Serial peripheral interface (SPI1, SPI2) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.26 Serial audio interfaces (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.27 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.28 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.28.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.28.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4/178 DS11929 Rev 5

STM32WB55xx Contents

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.4 RF 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.5 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 88
6.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . 88
6.3.7 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.9 Wakeup time from Low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.19 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.20 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 131
6.3.21 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.22 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.25 SMPS step-down converter characteristics . . . . . . . . . . . . . . . . . . . . . 147
6.3.26 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.28 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

DS11929 Rev 5 5/178

6
Contents STM32WB55xx

6.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 149

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

7.1 UFBGA129 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.2 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.3 VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 170

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

6/178 DS11929 Rev 5

STM32WB55xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32WB55xx devices features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 18
Table 4. RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 5. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Power supply typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. STM32WB55xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. STM32WB55xx CPU1 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 12. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 13. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 16. STM32WB55xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 17. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 21. Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 23. RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 24. RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 25. RF transmitter BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 26. RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 27. RF receiver BLE characteristics (2 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 28. RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 29. RF transmitter 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 30. RF receiver 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 31. RF 802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 32. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 33. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 34. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 35. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . . 92
Table 36. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 37. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V . . . . . . . . . . . . . 94
Table 38. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 39. Current consumption in Sleep and Low-power sleep modes, Flash memory ON . . . . . . . 96
Table 40. Current consumption in Low-power sleep modes, Flash memory in Power down . . . . . . . 96
Table 41. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 42. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 43. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 44. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

DS11929 Rev 5 7/178

9
List of tables STM32WB55xx

Table 45. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 46. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 47. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 48. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 49. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 50. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 51. Wakeup time using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 52. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 53. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 54. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 55. Low-speed external user clock characteristics – Bypass mode . . . . . . . . . . . . . . . . . . . . 113
Table 56. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 57. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 58. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 59. LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 60. LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 61. PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 62. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 63. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 64. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 65. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 66. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 67. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 68. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 69. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 70. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 71. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 72. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 73. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 74. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 75. ADC sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 76. ADC accuracy - Limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 77. ADC accuracy - Limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 78. ADC accuracy - Limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 79. ADC accuracy - Limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 80. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 81. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 82. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 83. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 84. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 85. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 86. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 87. IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 88. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 89. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 90. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 91. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 92. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 93. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 94. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 95. UFBGA129 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 96. UFBGA129 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

8/178 DS11929 Rev 5

STM32WB55xx List of tables

Table 97. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 98. WLCSP100 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 99. VFQFPN68 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 100. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 101. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

DS11929 Rev 5 9/178

9
List of figures STM32WB55xx

List of figures

Figure 1. STM32WB55xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. STM32WB55xx RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. STM32WB55xx external components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. Power distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 8. STM32WB55Cx UFQFPN48 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 9. STM32WB55Rx VFQFPN68 pinout(1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 10. STM32WB55Vx WLCSP100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 11. STM32WB55Vx BGA129 ballout(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 14. Power supply scheme (all packages except BGA129) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 15. Power supply scheme (BGA129 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 16. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 17. Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 18. Typical energy detection (T = 27°C, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 19. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 21. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 22. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 23. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 24. HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 25. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 27. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 30. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 31. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 32. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 33. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 34. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 35. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 36. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 37. UFBGA129 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 38. WLCSP - 100 balls, 4.390 x 4.371 mm, 0.4 mm pitch, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 39. WLCSP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 40. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 41. VFQFPN68 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 42. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 43. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 44. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

10/178 DS11929 Rev 5

STM32WB55xx Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32WB55xx microcontrollers, based on Arm® cores(a).
This document must be read in conjunction with the STM32WB55xx reference manual
(RM0434).
For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the
Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference
Manual, both available on the www.arm.com website.
For information on 802.15.4 refer to the IEEE website (www.ieee.org).
For information on Bluetooth® refer to www.bluetooth.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11929 Rev 5 11/178

54
Description STM32WB55xx

2 Description

The STM32WB55xx multiprotocol wireless and ultra-low-power devices embed a powerful

and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.0
and with IEEE 802.15.4-2011. They contain a dedicated Arm® Cortex® -M0+ for performing
all the real-time low layer operation.
The STM32WB55xx devices are designed to be extremely low-power and are based on the
high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to
64 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision that
supports all Arm® single-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) that
enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional
channels. The HSEM provides hardware semaphores used to share common resources
between the two processors.
The STM32WB55xx devices embed high-speed memories (Flash memory up to 1 Mbyte,
up to 256 Kbyte of SRAM), a Quad-SPI Flash memory interface (available on all packages)
and an extensive range of enhanced I/Os and peripherals.
Direct data transfer between memory and peripherals and from memory to memory is
supported by fourteen DMA channels with a full flexible channel mapping by the DMAMUX
peripheral.
The STM32WB55xx devices embed several mechanisms for embedded Flash memory and
SRAM: readout protection, write protection and proprietary code readout protection.
Portions of the memory can be secured for Cortex® -M0+ exclusive access.
The two AES encryption engines, PKA and RNG enable lower layer MAC and upper layer
cryptography. A customer key storage feature may be used to keep the keys hidden.
The devices offer one fast 12-bit ADC and two ultra-low-power comparators associated with
a high accuracy reference voltage generator.
The STM32WB55xx devices embed a low-power RTC, one advanced 16-bit timer, one
general-purpose 32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power
timers.
In addition, up to 18 capacitive sensing channels are available. The devices also embed an
integrated LCD driver up to 8x40 or 4x44, with internal step-up converter.
They also feature standard and advanced communication interfaces, namely one USART
(ISO 7816, IrDA, Modbus and Smartcard mode), one Low Power UART (LPUART), two I2C
(SMBus/PMBus), two SPI (up to 32 MHz), one serial audio interface (SAI) with two channels
and three PDMs, one USB 2.0 FS device with embedded crystal-less oscillator, supporting
BCD and LPM, and one Quad-SPI with execute-in-place (XIP) capability.
The STM32WB55xx operate in the -40 to +105 °C (+125 °C junction) temperature range
from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes enables
the design of low-power applications.
The STM32WB55xx include independent power supplies for analog input for ADC.
The STM32WB55xx integrate a high efficiency SMPS step-down converter with automatic
bypass mode capability when the VDD falls below VBORx (x=1, 2, 3, 4) voltage level (default

12/178 DS11929 Rev 5

STM32WB55xx Description

is 2.0 V). It includes independent power supplies for analog input for ADC and comparators,
as well as a 3.3 V dedicated supply input for USB.
A VBAT dedicated supply allows the devices to back up the LSE 32.768KHz oscillator, the
RTC and the backup registers, thus enabling the STM32WB55xx to supply these functions
even if the main VDD is not present through a CR2032-like battery, a Supercap or a small
rechargeable battery.
The STM32WB55xx offers three packages, from 48 to 100 pins.

Table 2. STM32WB55xx devices features and peripheral counts

Feature STM32WB55Cx STM32WB55Rx STM32WB55Vx

Flash memory density 256 KB 512 KB 1 MB 256 KB 512 KB 1 MB 256 KB 512 KB 1 MB

SRAM density 128 KB 256 KB 256 KB 128 KB 256 KB 256 KB 128 KB 256 KB 256 KB
SRAM1 64 KB 192 KB 64 KB 192 KB 64 KB 192 KB
SRAM2 64 KB
BLE V5.0 (2 Mbps)
802.15.4 Yes
Advanced 1 (16 bits)
General purpose 2 (16 bits) + 1 (32 bits)
Timers
Low power 2 (16 bits)
SysTick 1
SPI 1 2
I2C 2
USART(1) 1
Comm
LPUART 1
interface
SAI 2 channels
USB FS Yes
QSPI 1
RTC 1
Tamper pin 1 3
Wakeup pin 2 5
LCD, COMxSEG Yes, 4x13 Yes, 4x28 Yes, 8x40 or 4x44
GPIOs 30 49 72
Capacitive sensing No 6 18
12-bit ADC 13 channels 19 channels
Number of channels (incl. 3 internal) (incl. 3 internal)
Internal Vref No Yes
Analog comparator 2
Max CPU frequency 64 MHz

DS11929 Rev 5 13/178

54
Description STM32WB55xx

Table 2. STM32WB55xx devices features and peripheral counts (continued)

Feature STM32WB55Cx STM32WB55Rx STM32WB55Vx

Ambient operating temperature:-40 to +105 °C

Operating temperature
Junction temperature: -40 to 125 °C
Operating voltage 1.71 to 3.6 V
WLCSP100
UFQFPN48 VFQFPN68 0.4 mm pitch
Package 7 mm x 7 mm 8 mm x 8 mm
BGA129
0.5 mm pitch, solder pad 0.4 mm pitch, solder pad
0.5 mm pitch
1. USART peripheral can be used as SPI.

14/178 DS11929 Rev 5

STM32WB55xx Description

Figure 1. STM32WB55xx block diagram

APB asynchronous

asynchronous
RCC2

AHB
CTI
NVIC BLE IP 802.15.4

AHB Lite
LSI2
32 kHz
Cortex-M0+ BLE / 802.15.4 HSE2
RF IP 32 MHz

32 kB SRAM2a WKUP
Backup Memory BLE
LSE
32 kB SRAM2b RTC2 32 kHz
Shared Memory
1 MB Flash

Memory LSI1
JTAG/SWD

ARBITER
I-WDG 32 kHz

+ ART
PKA + RAM
TAMP
HSEM

AHB Lite (Shared)

RNG
ETM NVIC PLL1 HSI 1%
IPCC & 16 MHz
Cortex-M4 PLL2 MSI up to
(DSP) RCC + CSS 48 MHz
CTI

FPU MPU Power Supply POR/

PWR PDR/BOR/PVD/AVD
QSPI - XIP
EXTI CRS RC48
DMA1 7 channels AES2 USB FS + RAM
AHB Lite

MS41407V5

DS11929 Rev 5 15/178

54
Functional overview STM32WB55xx

3 Functional overview

3.1 Architecture
The STM32WB55xx multiprotocol wireless devices embed a BLE and an 802.15.4
RF subsystem that interfaces with a generic microcontroller subsystem using an Arm®
Cortex®-M4 CPU (called CPU1) on which the host application resides.
The RF subsystem is composed of a RF Analog Front end, BLE and 802.15.4 digital MAC
blocks as well as of a dedicated Arm® Cortex®-M0+ microcontroller (called CPU2) plus
some proprietary peripherals. The RF subsystem performs all of the BLE and 802.15.4 low
layer stack, reducing the interaction with the CPU1 to high level exchanges.
Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU
(CPU1):
• Flash memories
• SRAM1, SRAM2a and SRAM2b (SRAM2a can be retained in Standby mode)
• Security peripherals (RNG, AES1, PKA)
• Clock RCC
• Power control (PWR)
The communication and the sharing of peripherals between the RF subsystem and the
Cortex®-M4 CPU is performed through a dedicated Inter Processor Communication
Controller (IPCC) and semaphore mechanism (HSEM).

3.2 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is a processor for embedded systems. It has
been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional
code-efficiency, delivering the high-performance expected from an Arm® core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32WB55xx are compatible with all Arm® tools and
software.
Figure 1 shows the general block diagram of the STM32WB55xx devices.

16/178 DS11929 Rev 5

STM32WB55xx Functional overview

3.3 Memories

3.3.1 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, that normally require the processor
to wait for the Flash memory at higher frequencies.
To release the processor near 80 DMIPS performance at 64 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 64 MHz.

3.3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.3.3 Embedded Flash memory

STM32WB55xx devices feature up to 1 Mbyte of embedded Flash memory available for
storing programs and data, as well as some customer keys.
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in SRAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+
JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG
fuse). This selection is irreversible.

DS11929 Rev 5 17/178

54
Functional overview STM32WB55xx

Table 3. Access status vs. readout protection level and execution modes
Debug, boot from SRAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase

Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A

System 1 Yes No No Yes No No

memory 2 Yes No No N/A N/A N/A

Option 1 Yes Yes Yes Yes Yes Yes

bytes 2 Yes No (1)
No (1)
N/A N/A N/A
(2)
Backup 1 Yes Yes N/A No No N/A(2)
registers 2 Yes Yes N/A N/A N/A N/A
(2)
SRAM2a 1 Yes Yes Yes No No No(2)
SRAM2b 2 Yes Yes Yes N/A N/A N/A
1. The option byte can be modified by the RF subsystem.
2. Erased when RDP changes from Level 1 to Level 0.

• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4 Kbyte granularity.
• Proprietary code readout protection (PCROP): two parts of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2 KByte granularity. An additional option bit
(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP
protection is changed from Level 1 to Level 0.
A section of the Flash memory is secured for the RF subsystem CPU2, and cannot be
accessed by the host CPU1.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• the address of the ECC fail can be read in the ECC register
The embedded Flash memory is shared between CPU1 and CPU2 on a time sharing basis.
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

18/178 DS11929 Rev 5

STM32WB55xx Functional overview

3.3.4 Embedded SRAM

STM32WB55xx devices feature up to 256 KB of embedded SRAM, split in three blocks:
• SRAM1: up to 192 KB mapped at address 0x2000 0000
• SRAM2a: 32 KB located at address 0x2003 0000 (contiguous to SRAM1) also mirrored
at 0x1000 0000, with hardware parity check (this SRAM can be retained in Standby
mode)
• SRAM2b: 32 KB located at address 0x2003 8000 (contiguous with SRAM2a) and
mirrored at 0x1000 8000 with hardware parity check
SRAM2a and SRAM2b can be write-protected, with 1 KB granularity, A section of the
SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the
host CPU1.
The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock
speeds.

3.4 Security and safety

The STM32WB55xx contains many security blocks both for the BLE or IEEE 802.14.5 and
the Host application.
It includes:
• Customer storage of the BLE and 802.14.5 Keys
• Secure Flash memory partition for RF subsystem only access
• Secure SRAM partition, that can be accessed only by the RF subsystem
• True Random Number Generator (RNG)
• Advance Encryption Standard hadware accelerators (AES-128bit and AES-256bit,
supporting chaining modes ECB, CBC, CTR, GCM, GMAC, CCM)
• Private Key Acceleration (PKA) including:
– Modular arithmetic including exponentiation with maximum modulo size of 3136
bits
– Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA
verification with maximum modulo size of 521 bits
• Cyclic redundancy check calculation unit (CRC)
A specific mechanism is in place to ensure that all the code executed by the RF subsystem
CPU2 can be secure, whatever the Host application. For the AES1 a customer key can be
managed by the CPU2 and used by the CPU1 to encrypt/decrypt data.

3.5 Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM

DS11929 Rev 5 19/178

54
Functional overview STM32WB55xx

The STM32WB55xx always boot on CPU1 core. The embedded bootloader code makes it
possible to boot from various peripherals:
• USB
• UART
• I2C
• SPI
Secure Firmware update (especially BLE and 802.15.4) from system boot and over the air is
provided.

3.6 RF subsystem
The STM32WB55xx embed an ultra-low power multi-standard radio Bluetooth® Low Energy
(BLE) and 802.15.4 network processor, compliant with Bluetooth® specification v5.0 and
IEEE® 802.15.4-2011. The BLE features 1 Mbps and 2 Mbps transfer rates, supports
multiple roles simultaneously acting at the same time as Bluetooth® Low Energy sensor and
hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement protocol, thus
ensuring a secure connection.
The Bluetooth® Low Energy stack and 802.15.4 Low Level layer run on an embedded Arm®
Cortex®-M0+ core (CPU2). The stack is stored on the embedded Flash memory, which is
also shared with the Arm® Cortex®-M4 (CPU1) application, making it possible in-field stack
update.

3.6.1 RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF
architecture in Rx mode.
Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna
(single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the
internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band
interferer rejection.
In Transmit mode, the maximum output power is user selectable through the programmable
LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean
power ramp-up.
In receive mode the circuit can be used in standard high performance or in reduced power
consumption (user programmable). The Automatic Gain Control (AGC) is able to reduce the
chain gain at both RF and IF locations, for optimized interferers rejection. Thanks to the use
of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent
linearity can be achieved.
The bill of material is reduced thanks to the high degree of integration. The radio frequency
source is synthesized form an external 32 MHz crystal that does not need any external
trimming capacitor network thanks to a dual network of user programmable integrated
capacitors.

20/178 DS11929 Rev 5

STM32WB55xx Functional overview

Figure 2. STM32WB55xx RF front-end block diagram

control
AGC
Timer and Power
AGC
control

EXT_
RF control
PA_TX

ADC
G
Interrupt BLE BP
Wakeup modulator LNA
filter
BLE

ADC
AHB controller
BLE G
APB demodulator
RF1
802.15.4
APB modulator
802.15.4
MAC
Modulator

Interrupt 802.15.4
demodulator PLL
Wakeup

PA
See
notes

generator
PA ramp
Adjust Adjust

HSE Trimmed
bias

SMPS Max PA
LDO LDO LDO
level

VDDSMPS VSSSMPS VLXSMPS VFBSMPS VDDRF

OSC_IN OSC_OUT

32 MHz
Notes:
- UFQFPN48 and VFQFPN68: VSS through exposed pad, and VSSRF pin must be connected to ground plane
- WLCSP100: VSSRF pins must be connected to ground plane
MS45477V5

3.6.2 BLE general description

The BLE block is a master/slave processor, compliant with Bluetooth® specification 5.0
standard (2 Mbps).
It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a
complete power-optimized stack for Bluetooth® Low Energy protocol runs, providing
master / slave role support
• GAP: central, peripheral, observer or broadcaster roles
• ATT/GATT: client and server
• SM: privacy, authentication and authorization
• L2CAP
• Link Layer: AES-128 encryption and decryption

DS11929 Rev 5 21/178

54
Functional overview STM32WB55xx

In addition, according to Bluetooth® specification v5.0, the BLE block provides:

• Multiple roles simultaneously support
• Master/slave and multiple roles simultaneously
• LE Data Packet Length Extension (making it possible to reach 800 kbps at application
level)
• LE Privacy 1.2
• LE Secure Connections
• Flexible Internet Connectivity Options
• High data rate (2 Mbps)
The device allows the applications to meet the tight peak current requirements imposed by
the use of standard coin cell batteries. When the high efficiency embedded SMPS step-
down converter is used, the RF front end consumption (Itmax) is only 8.1 mA at the highest
output power (+6 dBm).
The power efficiency of the subsystem is optimized: while running with the radio and the
applicative cores simultaneously using the SMPS, the Cortex®-M4 core consumption
reaches 53 µA / MHz in active mode.
Ultra-low-power sleep modes and very short transition time between operating modes result
in very low average current consumption during real operating conditions, resulting in longer
battery life.
The BLE block integrates a full bandpass balun, thus reducing the need for external
components.
The link between the Cortex®-M4 application processor (CPU1) running the application, and
the BLE stack running on the dedicated Cortex®-M0+ (CPU2) is performed through a
normalized API, using a dedicated Inter Processor Communication Controller.

22/178 DS11929 Rev 5

STM32WB55xx Functional overview

3.6.3 802.15.4 general description

The STM32WB55xx embed a dedicated 802.15.4 Hardware MAC
• Support for 802.15.4 release 2011
• Advanced MAC frame filtering; hardwired firewall: Programmable filters based on
source/destination addresses, frame version, security enabled, frame type
• 256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean
RSSI,LQI)
• 128-byte TX FIFO with retention
– Content not lost, retransmissions possible under CPU2 control
• Automatic frame Acknowledgment, with programmable delay
• Advanced channel access features
– Full CSMA-CA support
– Superframe timer
– Beaconing support (require LSE),
– Flexible TX control with programmable delay
• Configuration registers with retention available down to Standby mode for
software/auto-restore
• Autonomous Sniffer, Wakeup based on timer or CPU2 request
• Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on
particular events

3.6.4 RF pin description

The RF block contains dedicated pins, listed in Table 4.
:

Table 4. RF pin list

Name Type Description

RF1 RF Input/output, must be connected to the antenna through a low pass matching network
OSC_OUT
I/O 32 MHz main oscillator, also used as HSE source
OSC_IN
EXT_PA_TX External PA transmit control
VDDRF VDD Dedicated supply, must be connected to VDD
(1)
VSSRF VSS To be connected to GND
1. On packages with exposed pad, this pad must be connected to GND plane for correct RF operation.

3.6.5 Typical RF application schematic

The schematic in Figure 3 and the external components listed in Table 4 are purely
indicative. For more details refer to the “Reference design” provided in separate documents.

DS11929 Rev 5 23/178

54
Functional overview STM32WB55xx

Figure 3. STM32WB55xx external components for the RF part

OSC_IN
X1 32 MHz
OSC_OUT
VDD
VDDRF

C1
Antenna
STM32WB55xx VSSRF
(including exposed pad)

Lf1
Cf1 Cf2

RF1
Antenna
Lf2 filter

MS41408V3

Table 5. Typical external components

Component Description Value

C1 Decoupling capacitance for RF 100 nf // 100 pF

X1 32 MHz crystal(1) 32 MHz
Antenna filter Antenna filter and matching network Refer to AN5165
Antenna 2.4 GHz band antenna -
1. e.g. NDK refernce: NX2016SA 32 MHz EXS00A-CS06654.

3.7 Power supply management

3.7.1 Power supply distribution

The device integrate an SMPS step-down converter to improve low power performance
when the VDD voltage is high enough. This converter has an intelligent mode that
automatically enters in bypass mode when the VDD voltage falls below a specific BORx
(x = 1, 2, 3 or 4) voltage.
By default, at Reset the SMPS is in bypass mode.
The device can be operated without the SMPS by just wiring its output to VDD. This is the
case for applications where the voltage is low, or where the power consumption is not
critical.

24/178 DS11929 Rev 5

STM32WB55xx Functional overview

Figure 4. Power distribution

VDD VDD
VDDSMPS VDDSMPS

SMPS
SMPS
VLXSMPS SMPS mode or VLXSMPS
(not used)
BYPASS mode
L1 LPR LPR

VFBSMPS VFBSMPS
C2
RFR MR RFR MR

SMPS configuration LDO configuration

MS41409V4

Table 6. Power supply typical components

Component Description Value

C2 SMPS output capacitor(1) 4.7 µF

For 8 MHz(3) 2.2 µH
L1(2) SMPS inductance
(4)
For 4 MHz 10 µH
1. e.g. GRM155R60J475KE19.
2. An extra 10 nH inductor in series with L1 is needed to improve the receiver performance,
e.g Murata LQG15WZ10NJ02D
3. e.g. Wurth 74479774222.
4. e.g. Murata LQM21FN100M70L.

The SMPS can also be switched On or set in bypass mode at any time by the application
software, for example when very accurate ADC measurement are needed.

3.7.2 Power supply schemes

The STM32WB55xx devices have different voltage supplies (see Figure 6) and can operate
within the following voltage ranges:
• VDD = 1.71 V to 3.6 V: external power supply for I/Os (VDDIO), the internal regulator and
system functions such as RF, SMPS, reset, power management and internal clocks. It
is provided externally through VDD pins. VDDRF and VDDSMPS must be always
connected to VDD pins.
• VDDA = 1.62 V (ADC/COMPs) to 3.6 V: external analog power supply for ADC,
comparators and voltage reference buffer. The VDDA voltage level can be independent
from the VDD voltage. When not used VDDA should be connected to VDD.
• VDDUSB = 3.0 V to 3.6 V: external independent power supply for USB transceivers.
When not used VDDUSB should be connected to VDD.
• VLCD = 2.5 V to 3.6 V: the LCD controller can be powered either externally through the
VLCD pin, or internally from an internal voltage generated by the embedded step-up
converter. This converter can generate a VLCD voltage up to 3.6 V if VDD is higher than
2.0 V.

DS11929 Rev 5 25/178

54
Functional overview STM32WB55xx

During power up/ down, the following power sequence requirements must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDUSB, VLCD), must remain
below VDD + 300 mV
• When VDD is above 1 V, all power supplies are independent.

Figure 5. Power-up/down sequence

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to any power supply among VDDA, VDDUSB, VLCD.

During the power down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling
capacitors to be discharged with different time constants during the power down transient
phase.
Note: VDD, VDDRF and VDDSMPS must be wired together, so they follow the same voltage
sequence.

26/178 DS11929 Rev 5

STM32WB55xx Functional overview

Figure 6. Power supply overview

Interruptible domain (VDD12I) On domain (VDD12O)

(CPU1, CPU2,

Level shifter
peripherals, SysConfig, AIEC,
IO SRAM1, RCC, PwrCtrl,
IOs
logic SRAM2b) LPTIM, LPUSART
Power Power
switch switch

VSS
VSS VSS
VFBSMPS MR
VLXSMPS
SMPS
VDDSMPS RFR
VSSSMPS
LPR
VDDRF
RF domain
Backup domain
Radio VBKP12 SRAM2a

VSSRF Power switch

VSS
VSS
(including exposed pad)
Wakeup domain (VDDIO)
VDD HSI, HSE1,
Power switch 2xPLL, LSI1,
VSW LSI2, IWDG,
VBAT RFpc
VSS

Switch domain (VSW)

VBAT LSE, RTC,
IO
IOs backup
logic
registers
VSS
VSS
VLCD LCD
VDDA Analog domain
REF_BUF ADC
=
VREF+ VREF+ =
VREF-
VSSA

VDDUSB

VUSB USB
IOs transceiver(1)
VSS
USB domain (VUSB)
VSS

MS41410V6

1. The USB transceiver is powered by VDDUSB, and the GPIOs associated with USB are powered by VDDUSB
when USB alternate function (PA11 and PA12) is selected. When USB alternate function is not selected
the GPIOs associated with USB are powered as standard GPIOs.

DS11929 Rev 5 27/178

54
Functional overview STM32WB55xx

3.7.3 Linear voltage regulator

Three embedded linear voltage regulators supply most of the digital and RF circuitries, the
main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the SRAM2a in Standby with retention.
• The RFR is used to supply the RF analog part, its activity is automatically managed by
the RF subsystem.
All the three regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing zero
consumption.
The ultralow-power STM32WB55xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two voltage and frequency ranges:
• Range 1 with the CPU running up to 64 MHz.
• Range 2 with a maximum CPU frequency of 16 MHz (note that HSE can be active in
this mode). All peripheral clocks are also limited to 16 MHz.
The VCORE can also be supplied by the low-power regulator, the main regulator being
switched off. The system is then in Low-power run mode. In this case the CPU is running at
up to 2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode
the RF subsystem is not available).

3.7.4 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it with the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a Peripheral Voltage Monitor that compares the independent
supply voltage VDDA with a fixed threshold to ensure that the peripheral is in its functional
supply range.
Any BOR level can also be used to automatically switch the SMPS step-down converter in
bypass mode when the VDD voltage drops below a given voltage level. The mode of
operation is selectable by register bit, the BOR level is selectable by option byte.

3.7.5 Low-power modes

The ultra-low-power STM32WB55xx support eight low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.

28/178 DS11929 Rev 5

STM32WB55xx Functional overview

By default, the microcontroller is in Run mode, range 1, after a system or a power on Reset.
It is up to the user to select one of the low-power modes described below:
• Sleep
In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,
continue to operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU1 frequency is limited to 2 MHz. The peripherals with independent clock
can be clocked by HSI16. The RF subsystem is not available in this mode and must be
OFF.
• Low-power sleep
This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the
low-power run mode. The RF subsystem is not available in this mode and must be
OFF.
• Stop 0, Stop 1 and Stop 2
Stop mode achieves the lowest power consumption while retaining the content of all
the SRAM and registers. The LSE (or LSI) is still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
In these modes the RF subsystem can wait for incoming events in all Stop modes 0, 1,
and 2.
The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI
up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem or the
SMPS is used the exits must be set to HSI16 only. If used, the SMPS is restarted
automatically.
• Standby
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off.
The RTC can remain active (Standby mode with RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1, SRAM2b and register contents are lost except
for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be
retained in Standby mode, supplied by the low-power Regulator (Standby with 32 KB
SRAM2a retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,

DS11929 Rev 5 29/178

Run Range 2

Sleep

VBAT
Peripheral
- - - -

SAI1 O O O O - - - - - - - - -
ADC1 O O O O - - - - - - - - -
VREFBUF O O O O O - - - - - - - -
COMPx (x=1, 2) O O O O O O O O - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers TIMx
O O O O - - - - - - - - -
(x=1, 2, 16, 17)
Low-power Timer 1
O O O O O O O O - - - - -
(LPTIM1)
Low-power Timer 2
O O O O O O - - - - - - -
(LPTIM2)
Independent watchdog
O O O O O O O O O O - - -
(IWDG)
Window watchdog
O O O O - - - - - - - - -
(WWDG)
SysTick timer O O O O - - - - - - - - -
Touch sensing controller
O O O O - - - - - - - - -
(TSC)
True random number
O - O - - - - - - - - - - -
generator (RNG)
AES2 hardware accelerator O O O O - - - - - - - - -
CRC calculation unit O O O O - - - - - - - - -
IPCC O - O - - - - - - - - - -
HSEM O - O - - - - - - - - - -

(15) 5 (16) 5
GPIOs O O O O O O O O -
pins pins
1. Legend: Y = Yes (Enabled), O = Optional (Disabled by default, can be enabled by software), R = Data retained,
- = Not available.
2. Bluetooth® Low Energy not possible in this mode.
3. Standby with SRAM2a Retention mode only.
4. Flash memory programming only possible in Range 1 voltage, not in Range 2 and not in Low Power mode.
5. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down mode.
6. The SRAM clock can be gated on or off.
7. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register.
8. Stop 0 only. SMPS is automatically switched to Bypass or Open mode during Low power operation.

32/178 DS11929 Rev 5

STM32WB55xx Functional overview

9. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
10. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).
11. MSI maximum frequency.
12. In case RF will be used and HSE will fail.
13. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
14. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
15. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
16. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

DS11929 Rev 5 33/178

54
34/178

Functional overview
Table 8. STM32WB55xx modes overview
Mode Regulator CPU1 Flash SRAM Clocks DMA and Peripherals Wakeup source Consumption(1) Wakeup time

Range 1 All 107 µA/MHz

Run Yes ON(2)(3) ON Any N/A N/A
Range2 All except RNG and USB-FS 100 µA/MHz
Any
LPRun LPR Yes ON(2) ON except All except RF, RNG and USB-FS N/A 103 µA/MHz 15.33 µs
PLL
Range 1 All Any interrupt 41 µA/MHz
Sleep No ON(2) ON(4) Any 9 cycles
Range 2 All except RNG and USB-FS or event 46 µA/MHz
Any
Any interrupt
LPSleep LPR No ON(2) ON(4) except All except RF, RNG and USB-FS 45 µA/MHz 9 cycles
or event
PLL
Reset pin, all I/Os,
RF, BOR, PVD, PVM
DS11929 Rev 5

Range 1 RF, BOR, PVD, PVM

RTC, LCD, IWDG
RTC, LCD, IWDG
LSE, COMPx (x=1, 2)
COMPx (x=1, 2)
LSI, USART1(7)
Stop 0 No OFF ON USART1 100 µA 1.7 µs
HSE(5), LPUART1(7)
HSI16(6) LPUART1
Range 2 I2Cx (x=1, 3)(8)
I2Cx (x=1, 3)
LPTIMx (x=1, 2), SMPS
LPTIMx (x=1, 2)
All other peripherals are frozen.
USB
Reset pin, all I/Os
RF, BOR, PVD, PVM
RF, BOR, PVD, PVM
RTC, LCD, IWDG
RTC, LCD, IWDG
LSE, COMPx (x=1, 2)
COMPx (x=1, 2)
LSI, USART1(7) 9.2 µA w/o RTC
Stop 1 LPR No OFF ON USART1 4.7 µs
HSE(5), LPUART1(7) 9.6 µA w RTC
HSI16(6) LPUART1
I2Cx (x=1, 3)(8)

STM32WB55xx
I2Cx (x=1, 3)
LPTIMx (x=1, 2)
LPTIMx (x=1, 2)
All other peripherals are frozen.
USB
Table 8. STM32WB55xx modes overview (continued)

STM32WB55xx
Mode Regulator CPU1 Flash SRAM Clocks DMA and Peripherals Wakeup source Consumption(1) Wakeup time

RF, BOR, PVD, PVM Reset pin, all I/Os

RTC, LCD, IWDG RF, BOR, PVD, PVM
COMPx (x=1, 2) RTC, LCD, IWDG
LSE, 1.85 µA w/o RTC
Stop 2 LPR No OFF ON LPUART1(7) COMPx (x=1, 2) 5.71 µs
LSI 2.1 µA w RTC
I2C3(8) LPUART1
LPTIM1 I2C3
All other peripherals are frozen. LPTIM1

SRAM2a RF, BOR, RTC, IWDG 0.32 µA w/o RTC

LPR
ON(9) All other peripherals are RF, Reset pin 0.6 µA w RTC
LSE,
Standby No OFF powered off. 5 I/Os (WKUPx)(10) 51 µs
LSI 0.11 µA w/o RTC
OFF OFF I/O configuration can be floating, BOR, RTC, IWDG
pull-up or pull-down 0.39 µA w RTC

RTC
DS11929 Rev 5

All other peripherals are

5 I/Os (WKUPx)(10), 0.028 µA w/o RTC
Shutdown OFF No OFF OFF LSE powered off. -
RTC 0.315 µA w/ RTC
I/O configuration can be floating,
pull-up or pull-down(11)
1. Typical current at VDD = 1.8 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.
2. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.
3. Flash memory programming is only possible in Range 2 voltage.
4. The SRAM1 and SRAM2 clocks can be gated off independently.
5. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.
6. HSI16 (16 MHz) automatically used by some peripherals.
7. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, Address match or Received frame event.
8. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

Functional overview
9. SRAM1 and SRAM2b are OFF.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PC12, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.
35/178
Functional overview STM32WB55xx

3.7.6 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.

3.8 VBAT operation

The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)
from an external battery, an external supercapacitor, or from VDD when no external battery
nor an external supercapacitor are present. Three anti-tamper detection pins are available
in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC
alarm/events do not exit it from VBAT operation.

3.9 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU1 resources and, consequently, reducing
power supply consumption. In addition, these hardware connections allow fast and
predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 9. STM32WB55xx CPU1 peripherals interconnect matrix Low-power run

Stop 0 / Stop 1
Low-power

Stop 2
Sleep
Run

Source Destination Action

TIMx Timers synchronization or chaining Y Y Y Y - -

ADC1 Conversion triggers Y Y Y Y - -
TIMx
DMA Memory to memory transfer trigger Y Y Y Y - -
COMPx Comparator output blanking Y Y Y Y - -

TIM1 Timer input channel, trigger, break

Y Y Y Y - -
TIM2 from analog signals comparison
COMPx
Low-power timer triggered by analog
LPTIMERx Y Y Y Y Y Y(1)
signals comparison
ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -

36/178 DS11929 Rev 5

STM32WB55xx Functional overview

Table 9. STM32WB55xx CPU1 peripherals interconnect matrix (continued)

Low-power run

Stop 0 / Stop 1
Low-power

Stop 2
Sleep
Run
Source Destination Action

TIM16 Timer input channel from RTC events Y Y Y Y - -

RTC Low-power timer triggered by RTC
LPTIMERx Y Y Y Y Y Y(1)
alarms or tampers

All clocks sources TIM2 Clock source used as input channel

Y Y Y Y - -
(internal and external) TIM16, 17 for RC measurement and trimming

USB TIM2 Timer triggered by USB SOF Y Y - - - -

CSS
CPU (hard fault)
SRAM (parity error) TIM1
Timer break Y Y Y Y - -
Flash memory (ECC error) TIM16,17
COMPx
PVD

TIMx External trigger Y Y Y Y - -

(1)
GPIO LPTIMERx External trigger Y Y Y Y Y Y
ADC1 Conversion external trigger Y Y Y Y - -
1. LPTIM1 only.

DS11929 Rev 5 37/178

54
Functional overview STM32WB55xx

3.10 Clocks and startup

The STM32WB55xx devices integrate many sources of clocks:
• LSE: 32.768KHz external oscillator, for accurate RTC and calibration with other
embedded RC oscillators
• LSI1: 32 KHz on-chip low-consumption RC oscillator
• LSI2: almost 32 KHz on-chip high-stability RC oscillator, used by the RF subsystem
• HSE: high quality 32 MHz external oscillator with trimming, needed by the RF
subsystem
• HSI16: 16 MHz high accuracy on-chip RC oscillator
• MSI: 100 KHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed
using the LSE signal
• HSI48: 48 MHz on-chip RC oscillator, for USB crystal-less purpose
The clock controller (see Figure 7) distributes the clocks coming from the different
oscillators to the core and the peripherals including the RF subsystem. It also manages
clock gating for low power modes and ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
– System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of
64 MHz.
• Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2
on-chip oscillator.
• Peripheral clock sources: Several peripherals (RNG, SAI, USARTs, I2Cs, LPTimers,
ADC) have their own independent clock whatever the system clock. Two PLLs, each

38/178 DS11929 Rev 5

STM32WB55xx Functional overview

having three independent outputs allowing the highest flexibility, can generate
independent clocks for the ADC, the RNG and the SAI.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If an HSE
clock failure occurs, the master clock is automatically switched to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and an interrupt
generated.
• Clock-out capability:
– MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSIx, LSE) are available
down to Stop 1 low power state.
– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby.
Several prescalers allow the user to configure the AHB frequencies, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 64 MHz.

DS11929 Rev 5 39/178

54
Functional overview STM32WB55xx

Figure 7. Clock tree

LSI1 RCC 32 kHz to IWDG

LSI

LSI2 RCC 32 kHz

LSI
LSCO
LSE to RTC and LCD

OSC32_OUT LSE OSC to BLE wakeup

32.768 kHz en
LSE
OSC32_IN
LSI to 802.15.4 wakeup
LSE CSS en
LSI1
/32
CPU1 to CPU1, AHB1, AHB2, AHB3, and SRAM1
LSI2 HCLK1
HPRE
/32 /1,2,...,512 to CPU1 FCLK
LSE

HSE to CPU1 system timer

/8
MCO SYSCLK
/1 - 16
APB1 PCLK1 to APB1
PLLRCLK
PPRE1
HSI16 SYS clock /1,2,4,8,16 x1 or to APB1 TIMx
source control x2
MSI
PLLRCLK APB2
RC48 PCLK2 to APB2
PPRE2
HSI16
OSC_OUT HSE OSC /1,4 /1,2,4,8,16 x1 or to APB2 TIMx
SYSCLK
32 MHz HSE HSEPRE/1,2 x2
OSC_IN
CPU2 to CPU2
HSE CSS MSI HCLK2
C2HPRE
1,2,...,512 to CPU2 FCLK
HSI16 RC
16 MHz to CPU2 system timer
/8
MSI RC AHB4
100 kHz - 48 MHz HCLK4 to AHB4, Flash memory, SRAM2
SHDHPRE
HSI48 RC /1,2,...,512
48 MHz to APB3
MSI HSI16
HCLK5 to AHB5
HSI16 HSE /2
/M
to RF

PLL HSI16 to
MSI
PLLPCLK SMPS
xN /P MSI SMPSDIV /2
HSI48 to USB /1,2,3,4,6,8,12
PLLQCLK HSE
/Q
/3
PLLRCLK to RNG PCLKn
/R SMPS clock
LSI source control SYSCLK to USART1
LSE
HSI16 HSI16
PLLSAI1 to SAI1 to LPUART1
PLLSAI1PCLK LSE
xN /P
SAI1_EXTCLK
PLLSAI1QCLK PCLKn
/Q
PCLKn HSI16 to LPTIMx
PLLSAI1RCLK
/R to ADC to I2Cx
SYSCLK LSI

SYSCLK HSI16 LSE

MS45402V5

3.11 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

40/178 DS11929 Rev 5

STM32WB55xx Functional overview

3.12 Direct memory access controller (DMA)

The device embeds two DMAs. Refer to Table 10: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, a full cross matrix allows any peripheral
to be mapped on any of the available DMA channels. Each has an arbiter for handling the
priority between DMA requests.
The DMA supports:
• 14 independently configurable channels (requests)
• A full cross matrix between peripherals and all 14 channels exist. There is also a HW
trigger possibility through the DMAMUX
• Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management
• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
• Access to Flash, SRAM, APB and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.

Table 10. DMA implementation

DMA features DMA1 DMA2
Number of regular channels 7 7

A DMAMUX block makes it possible to route any peripheral source to any DMA channel.

3.13 Interrupts and events

3.13.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.

DS11929 Rev 5 41/178

54
Functional overview STM32WB55xx

The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.13.2 Extended Interrupts and Events Controller (EXTI)

The Extended Interrupts and Events Controller (EXTI) manages wakeup through
configurable and direct event inputs. It provides wake-up requests to the Power Control, and
generates interrupt requests to the CPUx NVIC and events to the CPUx event input.
Configurable events/interrupt come from peripherals able to generate a pulse and allow to
select the Event/Interrupt trigger edge and/or a SW trigger
Direct events/interrupt are coming from peripherals having their own clearing mechanism.

3.14 Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the
following features:
• 12-bit native resolution, with built-in calibration
• up to 16-bit resolution with 64 decimation ratio
• 4.26 Msps maximum conversion rate with full resolution
– Down to 39 ns sampling time
– Increased conversion rate for lower resolution (up to 7.11 Msps for 6-bit
resolution)
• Up to 16 external channels and three internal channels: internal reference voltages,
temperature sensor
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: two groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– The ADC supports multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into three data register or in SRAM with DMA controller support

42/178 DS11929 Rev 5

STM32WB55xx Functional overview

– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channel, which is
used to convert the sensor output voltage into a digital value.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored in the system memory area, accessible in read-only mode.

Table 11. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)

3.14.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.

Table 12. Internal voltage reference calibration values

Calibration value name Description Memory address

Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.6 V (± 10 mV)

DS11929 Rev 5 43/178

54
Functional overview STM32WB55xx

3.15 Voltage reference buffer (VREFBUF)

The STM32WB55xx devices embed an voltage reference buffer which can be used as
voltage reference for ADC and also as voltage reference for external components through
the VREF+ pin. The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off. The VREF+ pin is double-bonded with VDDA on UFQFPN48
package, hence the internal voltage reference buffer is not available on a dedicated pin, but
user can still use the VDDA value.

3.16 Comparators (COMP)

The STM32WB55xx devices embed two rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.

3.17 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric such as
glass or plastic. The capacitive variation introduced by the finger (or any conductive object)
is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library (free to use) and enables reliable touch sensing functionality in the end application.

44/178 DS11929 Rev 5

STM32WB55xx Functional overview

The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 18 capacitive sensing channels
• Up to three capacitive sensing channels can be acquired in parallel offering a very
good response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.

DS11929 Rev 5 45/178

54
Functional overview STM32WB55xx

3.18 Liquid crystal display controller (LCD)

All device embed an LCD controller with the following characteristics:
• Highly flexible frame rate control.
• Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.
• Supports Static, 1/2, 1/3 and 1/4 bias.
• Double buffered memory allows data in LCD_RAM registers to be updated at any time
by the application firmware without affecting the integrity of the data displayed.
– LCD data RAM of up to 16 x 32-bit registers which contain pixel information
(active/inactive)
• Software selectable LCD output voltage (contrast) from VLCDmin to VLCDmax.
• No need for external analog components:
– A step-up converter is embedded to generate an internal VLCD voltage higher
than VDD (up to 3.6 V if VDD > 2.0 V)
– Software selection between external and internal VLCD voltage source. In case of
an external source, the internal boost circuit is disabled to reduce power
consumption
– A resistive network is embedded to generate intermediate VLCD voltages
– The structure of the resistive network is configurable by software to adapt the
power consumption to match the capacitive charge required by the LCD panel
– Integrated voltage output buffers for higher LCD driving capability.
• The contrast can be adjusted using two different methods:
– When using the internal step-up converter, the software can adjust VLCD between
VLCDmin and VLCDmax
– Programmable dead time (up to eight phase periods) between frames.
• Full support of low-power modes: the LCD controller can be displayed in Sleep,
Low-power run, Low-power sleep and Stop modes, or can be fully disabled to reduce
power consumption.
• Built in phase inversion for reduced power consumption and EMI (electromagnetic
interference).
• Start of frame interrupt to synchronize the software when updating the LCD data RAM.
• Blink capability:
– 1, 2, 3, 4, 8 or all pixels can be programmed to blink at a configurable frequency
– Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
Used LCD segment and common pins should be configured as GPIO alternate functions
and unused segment and common pins can be used for general purpose I/O or for another
peripheral alternate function.
Note: When the LCD relies on the internal step-up converter, the VLCD pin should be connected
to VSS with a capacitor. Its typical value is 1 μF.

3.19 True random number generator (RNG)

All devices embed a true RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.

46/178 DS11929 Rev 5

STM32WB55xx Functional overview

3.20 Timers and watchdogs

The STM32WB55xx include one advanced 16-bit timer, one general-purpose 32-bit timer,
two 16-bit basic timers, two low-power timers, two watchdog timers and a SysTick timer.
Table 13 compares the features of the advanced control, general purpose and basic timers.

Table 13. Timer features

DMA Capture/
Timer Counter Counter Prescaler Complementary
Timer request compare
type resolution type factor outputs
generation channels

Advanced Up, down,

TIM1 16-bits 4 3
control Up/down
General Up, down,
TIM2 32-bits 4 No
purpose Up/down
Any integer
General
TIM16 16-bits Up between 1 Yes 2 1
purpose
and 65536
General
TIM17 16-bits Up 2 1
purpose
LPTIM1
Low power 16-bits Up 1 1
LPTIM2

3.20.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.20.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.

3.20.2 General-purpose timers (TIM2, TIM16, TIM17)

There are up to three synchronizable general-purpose timers embedded in the
STM32WB55xx (see Table 13 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
• TIM2
– Full-featured general-purpose timer

DS11929 Rev 5 47/178

54
Functional overview STM32WB55xx

– Features four independent channels for input capture/output compare, PWM or

one-pulse mode output. Can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
– The counter can be frozen in debug mode.
– Independent DMA request generation, support of quadrature encoders.
• TIM16 and TIM17
– General-purpose timers with mid-range features:
– 16-bit auto-reload upcounters and 16-bit prescalers.
– 1 channel and 1 complementary channel
– All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
– The timers can work together via the Timer Link feature for synchronization or
event chaining. The timers have independent DMA request generation.
– The counters can be frozen in debug mode

3.20.3 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSIx or by an external clock. They are able
to wakeup the system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only)

3.20.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.

48/178 DS11929 Rev 5

STM32WB55xx Functional overview

3.20.5 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.20.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source

3.21 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Three anti-tamper detection pins with programmable filter
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 20 backup registers are supplied through a switch that takes power either
from the VDD supply (when present) or from the VBAT pin.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• One of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of
32 kHz)
• The high-speed external clock (HSE) divided by 32

DS11929 Rev 5 49/178

54
Functional overview STM32WB55xx

The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is
functional in all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.

3.22 Inter-integrated circuit interface (I2C)

The device embeds two I2Cs. Refer to Table 14 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 7: Clock tree.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 14. I2C implementation

I2C features(1) I2C1 I2C3

Standard-mode (up to 100 kbit/s) X X

Fast-mode (up to 400 kbit/s) X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X
Programmable analog and digital noise filters X X
SMBus/PMBus hardware support X X

50/178 DS11929 Rev 5

STM32WB55xx Functional overview

Table 14. I2C implementation (continued)

I2C features(1) I2C1 I2C3

Independent clock X X
Wakeup from Stop 0 / Stop 1 mode on address match X X
Wakeup from Stop 2 mode on address match - X
1. X: supported

3.23 Universal synchronous/asynchronous receiver transmitter

(USART)
The STM32WB55xx devices feature one universal synchronous receiver transmitter.
This interface provides asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and has
LIN Master/Slave capability. It provides hardware management of the CTS and RTS signals,
and RS485 Driver Enable.
The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart
Card mode (ISO 7816 compliant) and SPI-like communication capability.
The USART supports synchronous operation (SPI mode), and can be used as an SPI
master.
The USART has a clock domain independent from the CPU clock, allowing the it to wake up
the MCU from Stop mode using baudrates up to 200 Kbaud.The wake up events from Stop
mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
The USART interface can be served by the DMA controller.

3.24 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one Low-Power UART, enabling asynchronous serial communication
with minimum power consumption. The LPUART supports half duplex single wire
communication and modem operations (CTS/RTS), allowing multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

DS11929 Rev 5 51/178

54
Functional overview STM32WB55xx

having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interfaces can be served by the DMA controller.

3.25 Serial peripheral interface (SPI1, SPI2)

Two SPI interfaces allow communication up to 32 Mbit/s in master and up to 24 Mbit/s in
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.

3.26 Serial audio interfaces (SAI1)

The device embeds a dual channel SAI peripheral that supports full duplex audio operation.
The SAI bus interface handles communications between the microcontroller and the serial
audio protocol.
The SAI peripheral supports:
• One independent audio sub-block that can be a transmitter or a receiver, with the
respective FIFO
• 8-word integrated FIFOs
• Synchronous or asynchronous mode
• Master or slave configuration
• Clock generator to target independent audio frequency sampling when audio sub-block
is configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable
• Frame synchronization active level configurable (offset, bit length, level)
• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/Mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in slave mode
– Late frame synchronization signal detection in slave mode
– Codec not ready for the AC’97 mode in reception

52/178 DS11929 Rev 5

STM32WB55xx Functional overview

• Interruption sources when enabled:

– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of the SAI audio sub-block.
The PDM (Pulse Density Modulation) block allows the user to manage up to three digital
microphone pairs (with two different clocks). This block performs Right and Left microphone
de-interleaving and time alignment through programmable delay lines in order to properly
feed the SAI.

3.27 Quad-SPI memory interface (QUADSPI)

The Quad-SPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the QUADSPI registers
• Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting
• Memory-mapped mode: the external Flash memory is mapped and is seen by the
system as if it were an internal memory. This mode can be used for the Execute In
Place (XIP)
The Quad-SPI interface supports:
• Three functional modes: indirect, status-polling, and memory-mapped
• SDR and DDR support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
• Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Programmable masking for external Flash memory flag management
• Timeout management
• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error

DS11929 Rev 5 53/178

54
Functional overview STM32WB55xx

3.28 Development support

3.28.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are
shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is
used to switch between JTAG-DP and SW-DP.

3.28.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32WB55xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.

54/178 DS11929 Rev 5

STM32WB55xx Pinouts and pin description

4 Pinouts and pin description

Figure 8. STM32WB55Cx UFQFPN48 pinout(1)(2)

VDDUSB
PA15
PA14

PA13
PA12
PA11
VDD
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 PA10
PC14-OSC32_IN 2 35 VDD
PC15-OSC32_OUT 3 34 VDDSMPS
PH3-BOOT0 4 33 VLXSMPS
PB8 5 32 VSSSMPS
PB9 6 31 VFBSMPS
NRST 7
UFQFPN48 30 PE4
VDDA 8 29 PB1
PA0 9 28 PB0
PA1 10 27 AT1
PA2 11 26 AT0
PA3 12 25 OSC_IN
13
14
15
16
17
18
19
20
21
22
23
24
PB2
VDD
RF1
VSSRF
VDDRF
OSC_OUT
PA4
PA5
PA6
PA7
PA8
PA9

MS42406V3

1. The above figure shows the package top view.

2. The exposed pad must be connected to ground plane.

Figure 9. STM32WB55Rx VFQFPN68 pinout(1)(2)

VDDUSB
PC12

PC10
PC11

PA15
PA14

PA13
PA12
PA11
VDD

PD1
PD0
PB7
PB6
PB5
PB4
PB3
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

VBAT 1 51 PA10
PC13 2 50 PC6
PC14-OSC32_IN 3 49 PB15
PC15-OSC32_OUT 4 48 PB14
PH3-BOOT0 5 47 PB13
PB8 6 46 PB12
PB9 7 45 VDD
NRST 8 44 VDDSMPS
PC0 9 VFQFPN68 43 VLXSMPS
PC1 10 42 VSSSMPS
PC2 11 41 VFBSMPS
PC3 12 40 PE4
VREF+ 13 39 PB1
VDDA 14 38 PB0
PA0 15 37 AT1
PA1 16 36 AT0
PA2 17 35 OSC_IN
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
PC4
PC5
PB2
PB10

VDD
RF1
VSSRF
VDDRF
OSC_OUT
PA3
PA4
PA5
PA6
PA7
PA8
PA9

PB11

MS45417V2

1. The above figure shows the package top view.

2. The exposed pad must be connected to ground plane.

DS11929 Rev 5 55/178

72
Pinouts and pin description STM32WB55xx

Figure 10. STM32WB55Vx WLCSP100 ballout(1)

1 2 3 4 5 6 7 8 9 10

A PA11 PA12 PA14 PA15 PA13 PC10 PD2 PD7 PB3 VDD

B VDD VSS VDDUSB PC9 PA10 PC11 PD5 PD12 VSS PE1

C PB13 PD3 PD1 PD0 PC12 PD6 PB4 PE0 PD13 VBAT

PC15- PC14-
D VDDSMPS PC6 PD4 PD8 PD9 PB5 PB7 PD14
OSC32_OUT OSC32_IN

E VLXSMPS PB14 PC7 PD10 PD11 PE2 PD15 PH3-BOOT0 PH1 PH0

F VSSSMPS VFBSMPS PB15 PC8 PB6 PA2 PB8 PC0 NRST PB9

G PE4 PE3 PB12 PC4 PC13 PA1 PA0 PC1 PC2 PC3

H PB1 PB0 AT0 AT1 PC5 PA7 PA6 VREF+ VDDA VSSA

J OSC_IN OSC_OUT VDDRF VSSRF VSS PB11 PA8 PA3 VSS VDD

K VSSRF VSSRF VSSRF RF1 VDD PB10 PB2 PA9 PA5 PA4

Radio USB SMPS VDD VSS

MS42407V3

1. The above figure shows the package top view.

Figure 11. STM32WB55Vx BGA129 ballout(1)

MS51777V1

1. The above figure shows the package top view.

56/178 DS11929 Rev 5

STM32WB55xx Pinouts and pin description

Table 15. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name

S Supply pin

Pin type I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RF RF I/O

RST Bidirectional reset pin with weak pull-up resistor

I/O structure Option for TT or FT I/Os

_f (1) I/O, Fm+ capable

_l (2) I/O, with LCD function supplied by VLCD

UFBGA129
VFQFPN68

(function after Alternate functions Additional functions

reset)

reset)

LPTIM1_ETR, I2C1_SCL,
USART1_TX, TSC_G2_IO3,
46 66 F5 A2 PB6 I/O FT_fla - LCD_SEG6, SAI1_FS_B, COMP2_INP
TIM16_CH1N, MCO,
CM4_EVENTOUT
LPTIM1_IN2, TIM1_BKIN,
I2C1_SDA, USART1_RX,
47 67 D7 C3 PB7 I/O FT_fla - TSC_G2_IO4, LCD_SEG21, COMP2_INM, PVD_IN
TIM17_CH1N,
CM4_EVENTOUT
- - - J5 VSS S - - - -
- - - J7 VSS S - - - -
- - - J9 VSS S - - - -
- - - B8 VSS_DCAP4 S - - - -
48 68 A10 - VDD S - - - -
- - - A8 VSS_DCAP4 S - - - -
- - - F2 VSS_DCAP1 S - - - -
- - - J12 VSS_DCAP3 S - - - -
- - - N7 VSS_DCAP2 S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA),
the use of the PC13, PC14 and PC15 GPIOs in output mode is limited:
- the speed should not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0351, available on www.st.com.
3. On UFQFPN48 VDDA is connected to VREF+.
4. RF pin, use the nominal PCB layout.
5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).
6. Reserved, must be kept unconnected.
7. High frequency (above 100 KHz) may impact the RF performances.
8. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and
PB4 pins and the internal pull-down on PA14 pin are activated.

66/178 DS11929 Rev 5

Table 17. Alternate functions

STM32WB55xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM2/
TIM1/ SPI2/ COMP1/
TIM1/ I2C1/ SPI1/ USB/ TIM16/
SYS_AF TIM2/ SAI1/ RF USART1 LPUART1 TSC LCD COMP2/ SAI1 EVENTOUT
TIM2 I2C3 SPI2 QUADSPI TIM17/
LPTIM1 TIM1 TIM1
LPTIM2

TIM2_ COMP1_ SAI1_ TIM2_ CM4_

PA0 -
CH1
- - - - - - - - - -
OUT EXTCLK ETR EVENTOUT

TIM2_ I2C1_ SPI1_ CM4_

PA1 -
CH2
- -
SMBA SCK
- - - - LCD_SEG0 - - -
EVENTOUT

TIM2_ LPUART1 QUADSPI_ COMP2_ CM4_

PA2 LSCO
CH3
- - - - - -
_TX
-
BK1_NCS
LCD_SEG1
OUT
- -
EVENTOUT

TIM2_ SAI1_ LPUART1 QUADSPI_ SAI1 CM4_

PA3 -
CH4
-
PDM_CK1
- - - -
_RX
-
CLK
LCD_SEG2 -
_MCLK_A
-
EVENTOUT

SPI1_ SAI1 LPTIM2_ CM4_

PA4 - - - -
NSS
- - - - - LCD_SEG5 -
_FS_B OUT EVENTOUT

TIM2_ TIM2_ SPI1_ SAI1 LPTIM2_ CM4_

DS11929 Rev 5

PA5 -
CH1 ETR
-
SCK
- - - - - - -
_SD_B ETR EVENTOUT

TIM1_ SPI1_ LPUART1 QUADSPI_ TIM1_ TIM16 CM4_

PA6 -
BKIN
- -
MISO
- -
_CTS
-
BK1_IO3
LCD_SEG3
BKIN
-
_CH1 EVENTOUT

TIM1_ I2C3_ SPI1_ QUADSPI_ COMP2_ TIM17 CM4_

PA7 -
CH1N
- -
SCL MOSI
- - - -
BK1_IO2
LCD_SEG4
OUT
-
_CH1 EVENTOUT
A
TIM1_ SAI1_ USART1_ SAI1 LPTIM2_ CM4_
PA8 MCO
CH1
-
PDM_CK2
- - -
CK
- - LCD_COM0 -
_SCK_A OUT EVENTOUT

TIM1_ SAI1_ I2C1_ SPI2_ USART1_ SAI1 CM4_

PA9 -
CH2
-
PDM_DI2 SCL SCK
-
TX
- - LCD_COM1 -
_FS_A
-
EVENTOUT

TIM1_ SAI1_ I2C1_ USART1_ USB_CRS SAI1 TIM17 CM4_

PA10 -
CH3
-
PDM_DI1 SDA
-
RX
- -
_SYNC
LCD_COM2 -
_SD_A _BKIN EVENTOUT

Pinouts and pin description

TIM1_ TIM1_ SPI1_ USART1_ TIM1_ CM4_
PA11 -
CH4 BKIN2
- -
MISO
-
CTS
- - USB_DM -
BKIN2
- -
EVENTOUT

TIM1_ SPI1_ USART1_ LPUART1 CM4_

PA12 -
ETR
- - -
MOSI
-
RTS_DE _RX
- USB_DP - - - -
EVENTOUT

JTMS- SAI1 CM4_

PA13 SWDIO
- - - - - - - IR_OUT - USB_NOE - -
_SD_B
-
EVENTOUT

JTCK- LPTIM1_ I2C1_ SAI1 CM4_

PA14 SWCLK OUT
- -
SMBA
- - - - - - LCD_SEG5 -
_FS_B
-
EVENTOUT

TIM2_ TIM2_ SPI1_ TSC_G3 CM4_

PA15 JTDI - MCO - - - LCD_SEG17 - - -
67/178

CH1 ETR NSS _IO1 EVENTOUT

Table 17. Alternate functions (continued)
68/178

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM2/
TIM1/ SPI2/ COMP1/
TIM1/ I2C1/ SPI1/ USB/ TIM16/
SYS_AF TIM2/ SAI1/ RF USART1 LPUART1 TSC LCD COMP2/ SAI1 EVENTOUT
TIM2 I2C3 SPI2 QUADSPI TIM17/
LPTIM1 TIM1 TIM1
LPTIM2

EXT
COMP1_ CM4_
PB0 - - - - - - _PA - - - -
OUT
- -
EVENTOUT
_TX

LPUART1 LPTIM2_ CM4_

PB1 - - - - - - - -
_RTS_DE
- - - - -
IN1 EVENTOUT

RTC_ LPTIM1_ I2C3_ SPI1_ SAI1_ CM4_

PB2 OUT OUT
- -
SMBA NSS
- - - - - LCD_VLCD -
EXTCLK
-
EVENTOUT

JTDO-
TIM2_ SPI1_ USART1_ SAI1_ CM4_
PB3 TRACE
CH2
- - -
SCK
-
RTS_DE
- - - LCD_SEG7 -
SCK_B
-
EVENTOUT
SWO

I2C3_ SPI1_ USART1_ TSC_G2 SAI1_ TIM17_ CM4_

PB4 NJTRST - - -
SDA MISO
-
CTS
-
_IO1
- LCD_SEG8 -
MCLK_B BKIN EVENTOUT
DS11929 Rev 5

LPTIM1_ I2C1_ SPI1_ USART1_ LPUART1 TSC_G2 COMP2_ SAI1_ TIM16_ CM4_
PB5 -
IN1
- -
SMBA MOSI
-
CK _TX _IO2
- LCD_SEG9
OUT SD_B BKIN EVENTOUT

LPTIM1_ I2C1_ USART1_ TSC_G2 SAI1_ TIM16_ CM4_

PB6 MCO
ETR
- -
SCL
- -
TX
-
_IO3
- LCD_SEG6 -
FS_B CH1N EVENTOUT

LPTIM1_ TIM1_ I2C1_ USART1_ TSC_G2 TIM17_ CM4_

B PB7 -
IN2
-
BKIN SDA
- -
RX
-
_IO4
- LCD_SEG21 - -
CH1N EVENTOUT

TIM1_ SAI1_ I2C1_ QUADSPI_ SAI1_ TIM16_ CM4_

PB8 -
CH2N
-
PDM_CK1 SCL
- - - - -
BK1_IO1
LCD_SEG16 -
MCLK_A CH1 EVENTOUT

TIM1_ SAI1_ I2C1_ SPI2_ TSC_G7 QUADSPI_ SAI1_ TIM17_ CM4_

PB9 -
CH3N
-
PDM_DI2 SDA NSS
- - IR_OUT
_IO4 BK1_IO0
LCD_COM3 -
FS_A CH1 EVENTOUT

TIM2_ I2C3_ SPI2_SC LPUART1 TSC QUADSPI_ COMP1_ SAI1_ CM4_

PB10 -
CH3
- -
SCL K
- -
_RX _SYNC CLK
LCD_SEG10
OUT SCK_A
-
EVENTOUT

TIM2_ I2C3_ LPUART1 QUADSPI_ COMP2_ CM4_

PB11 -
CH4
- -
SDA
- - -
_TX
-
BK1_NCS
LCD_SEG11
OUT
- -
EVENTOUT

TIM1_ TIM1_ I2C3_ SPI2_ LPUART1 TSC_G1 SAI1_ CM4_

PB12 -
BKIN
-
BKIN SMBA NSS
- -
_RTS _IO1
- LCD_SEG12 -
FS_A
-
EVENTOUT

STM32WB55xx
TIM1_ I2C3_ SPI2_ LPUART1 TSC_G1 SAI1_ CM4_
PB13 -
CH1N
- -
SCL SCK
- -
_CTS _IO2
- LCD_SEG13 -
SCK_A
-
EVENTOUT

TIM1_ I2C3_ SPI2_ TSC_G1 SAI1_ CM4_

PB14 -
CH2N
- -
SDA MISO
- - -
_IO3
- LCD_SEG14 -
MCLK_A
-
EVENTOUT

RTC_ TIM1_ SPI2_ TSC_G1 SAI1_ CM4_

PB15 REFIN CH3N
- - -
MOSI
- - -
_IO4
- LCD_SEG15 -
SD_A
-
EVENTOUT
Table 17. Alternate functions (continued)

STM32WB55xx
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port TIM2/
TIM1/ SPI2/ COMP1/
TIM1/ I2C1/ SPI1/ USB/ TIM16/
SYS_AF TIM2/ SAI1/ RF USART1 LPUART1 TSC LCD COMP2/ SAI1 EVENTOUT
TIM2 I2C3 SPI2 QUADSPI TIM17/
LPTIM1 TIM1 TIM1
LPTIM2

LPTIM1_ I2C3 LPUART1 LPTIM2_ CM4_

PC0 -
IN1
- -
_SCL
- - -
_RX
- - LCD_SEG18 - -
IN1 EVENTOUT

LPTIM1_ SPI2_ I2C3 LPUART1 CM4_

PC1 -
OUT
-
MOSI _SDA
- -
_TX
- - LCD_SEG19 - - -
EVENTOUT

LPTIM1_ SPI2_ CM4_

PC2 -
IN2
- - -
MISO
- - - - - LCD_SEG20 - - -
EVENTOUT

LPTIM1_ SAI1_ SPI2_ SAI1 LPTIM2_ CM4_

PC3 -
ETR
-
PDM_DI1
-
MOSI
- - - - - LCD_VLCD -
_SD_A ETR EVENTOUT

CM4_
PC4 - - - - - - - - - - - LCD_SEG22 - - -
EVENTOUT

SAI1_ CM4_
PC5 - - - - - - - - - - LCD_SEG23 - - -
DS11929 Rev 5

PDM_DI3 EVENTOUT

TSC_G4 CM4_
PC6 - - - - - - - - -
_IO1
- LCD_SEG24 - - -
EVENTOUT

TSC_G4 CM4_
PC7 - - - - - - - - -
_IO2
- LCD_SEG25 - - -
EVENTOUT

TSC_G4 CM4_
C PC8 - - - - - - - - -
_IO3
- LCD_SEG26 - - -
EVENTOUT

TIM1 TSC_G4 SAI1 CM4_

PC9 - - -
_BKIN
- - - - -
_IO4
USB_NOE LCD_SEG27 -
_SCK_B
-
EVENTOUT

LCD_COM4
TRACE TSC_G3 CM4_
PC10 D1
- - - - - - - -
_IO2
- LCD_SEG28 - - -
EVENTOUT
LCD_SEG40

Pinouts and pin description

LCD_COM5
TSC_G3 CM4_
PC11 - - - - - - - - -
_IO3
- LCD_SEG29 - - -
EVENTOUT
LCD_SEG41

LCD_COM6
TRACE TSC_G3 CM4_
PC12 D3
- - - - - - - -
_IO4
- LCD_SEG30 - - -
EVENTOUT
LCD_SEG42

CM4_
PC13 - - - - - - - - - - - - - - -
EVENTOUT

CM4_
PC14 - - - - - - - - - - - - - - -
69/178

EVENTOUT

CM4_
PC15 - - - - - - - - - - - - - - -
EVENTOUT
Table 17. Alternate functions (continued)
70/178

Pinouts and pin description

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

E PE2 TRACECK - -
PDM_CK1
- - - - -
G7_IO1
- LCD_SEG38 -
MCLK_A
-
EVENTOUT

CM4_
PE3 - - - - - - - - - - - - - - -
EVENTOUT

CM4_
PE4 - - - - - - - - - - - - - - -
EVENTOUT

CM4_
PH0 - - - - - - - - - - - - - - -
DS11929 Rev 5

EVENTOUT

CM4_
H PH1 - - - - - - - - - - - - - - -
EVENTOUT

CM4_
PH3 LSCO - - - - - - - - - - - - - -
EVENTOUT

Pinouts and pin description

71/178
Memory mapping STM32WB55xx

5 Memory mapping

The STM32WB55xx devices feature a single physical address space that can be accessed
by the application processor and by the RF subsystem.
A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,
exclusively accessible by the CPU2, protected against execution, read and write from CPU1
and DMA.
In case of shared resources the SW should implement arbitration mechanism to avoid
access conflicts. This happens for peripherals Reset and Clock Controller (RCC), Power
Controller (PWC), EXTI and Flash interface, and can be implemented using the built-in
semaphore block (HSEM).
By default the RF subsystem and CPU2 operate in secure mode. This implies that part of
the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by
the CPU2. In this case the Host processor (CPU1) has no access to these resources.
The detailed memory map and the peripheral mapping of the STM32WB55xx devices can
be found in the reference manual RM0434.

72/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 12.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 13.

Figure 12. Pin loading conditions Figure 13. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V1 MS19211V1

DS11929 Rev 5 73/178

159
Electrical characteristics STM32WB55xx

6.1.6 Power supply scheme

Figure 14. Power supply scheme (all packages except BGA129)

VBAT

Backup circuitry
1.55 V to 3.6 V (LSE, RTC and
backup registers)
Power switch
VDD VCORE
n x VDD
Regulator

VDDIO1
OUT
Kernel logic

Level shifter
IO (CPU, digital
GPIOs
n x 100 nF + 1 x 4.7 μF logic
IN and memories

n x VSS

VDDA
VDDA
VREF
ADCs
10 nF + 1 μF VREF+ OPAMPs
100 nF 1 μF COMPs
VREF-
VREFBUF

VSSA

VDD
VDDSMPS
SMPS
SMPS Regulator

4.7 μF VLXSMPS

L1(1)
VFBSMPS

4.7 μF
VSSSMPS

Exposed pad
To all modules

MS45423V3

1. The value of L1 depends upon the frequency, as indicated in Table 6.

74/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Figure 15. Power supply scheme (BGA129 package)

VDD_DCAPx(2)

1 x 100 nF
VSS_DCAPx(2)

VBAT

Backup circuitry
1.55 V to 3.6 V (LSE, RTC and
backup registers)
Power switch
VDD VCORE
n x VDD
Regulator

VDDIO1
OUT
Kernel logic

Level shifter
IO (CPU, digital
GPIOs
1 x 4.7 μF logic
IN and memories

n x VSS

VDDA
VDDA
VREF
ADCs
10 nF + 1 μF VREF+ OPAMPs
100 nF 1 μF COMPs
VREF-
VREFBUF

VSSA

VDD
VDDSMPS
SMPS
SMPS Regulator

4.7 μF VLXSMPS

L1(1)
VFBSMPS

4.7 μF
VSSSMPS

Exposed pad
To all modules

MS53132V1

1. The value of L1 depends upon the frequency, as indicated in Table 6.

2. VDD_DCAPx and VSS_DCAPx balls are connected to VDD and VSS internally. They simplify the 2-layer
board layout and especially the ground plane below the BGA.
VDD power supply can be done with a single connection to the center of the BGA on the bottom layer of the
board. The decoupling 100 nF capacitors are connected between VDDCAPx and VSSCAPx without cutting
the board ground plane.

DS11929 Rev 5 75/178

159
Electrical characteristics STM32WB55xx

Caution: Each power supply pair (VDD / VSS, VDDA / VSSA etc.) must be decoupled with filtering
ceramic capacitors as shown in Figure 14. These capacitors must be placed as close as
possible to (or below) the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.

6.1.7 Current consumption measurement

Figure 16. Current consumption measurement scheme

IDDSMPS

VDDSMPS

IDDRF

VDDRF

IDDUSB

VDDUSB

IDDVBAT

VBAT
IDD

VDD

IDDA

VDDA

MS45416V1

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18, Table 19 and Table 20
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.

76/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 18. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage

VDDX - VSS (including VDD, VDDA, VDDUSB, VLCD, -0.3 4.0
VDDRF, VDDSMPS, VBAT)
min (VDD, VDDA, VDDUSB, VLCD, VDDRF, V
Input voltage on FT_xxx pins
VDDSMPS) + 4.0(3)(4)
VIN(2) VSS-0.3
Input voltage on TT_xx pins 4.0
Input voltage on any other pin 4.0
Variations between different VDDX
|∆VDDx| - 50
power pins of the same domain
mV
Variations between all the different
|VSSx-VSS| - 50
ground pins(5)
1. All main power (VDD, VDDRF, VDDA, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19 for the maximum allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.

Table 19. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 130
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 130
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 100
Injected current on FT_xxx, TT_xx, RST and B pins, except PB0 and PB1 –5 / +0(4)
IINJ(PIN)(3)
Injected current on PB0 and PB1 -5/0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD, VDDRF, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage
characteristics for the maximum allowed input voltage values.

DS11929 Rev 5 77/178

159
Electrical characteristics STM32WB55xx

5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).

Table 20. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150

°C
TJ Maximum junction temperature 130

78/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3 Operating conditions

6.3.1 Summary of main performance

Table 21. Main performance at VDD = 3.3 V

Parameter Test conditions Typ Unit

VBAT (VBAT = 1.8 V, VDD = 0 V) 0.002

Shutdown (VDD = 1.8 V) 0.013
Standby (VDD = 1.8 V, 32 Kbytes RAM retention) 0.320
Stop2 1.85
Core current
ICORE Sleep (16 MHz) 740
consumption
LP run (2 MHz) 320
Run (64 MHz) 5000
Radio RX 4500
µA
Radio TX 0 dBm output power 5200
Advertising
13
(Tx = 0 dBm; Period 1.28 s; 31 bytes, 3 channels)
BLE
Advertising
4
Peripheral (Tx = 0 dBm, 6 bytes; period 10.24 s, 3 channels)
IPERI current LP timers - 6
consumption
I2C3 - 7.1
LPUART - 7.7
RTC - 2.5

6.3.2 General operating conditions

Table 22. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 64

fPCLK1 Internal APB1 clock frequency - 0 64 MHz
fPCLK2 Internal APB2 clock frequency - 0 64
VDD Standard operating voltage - 1.71(1) 3.6
ADC or COMP used 1.62
VREFBUF used 2.4
VDDA Analog supply voltage 3.6 V
ADC, COMP, VREFBUF
0
not used
VBAT Backup operating voltage - 1.55 3.6

DS11929 Rev 5 79/178

159
Electrical characteristics STM32WB55xx

Table 22. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

VFBSMPS SMPS Feedback voltage - 1.4 3.6

VDDRF Minimum RF voltage - 1.71 3.6
USB used 3.0 3.6
VDDUSB USB supply voltage
USB not used 0 3.6 V
TT_xx I/O –0.3 VDD + 0.3

VIN I/O input voltage min (min (VDD, VDDA,

All I/O except TT_xx –0.3 VDDUSB, VLCD) + 3.6 V,
5.5 V)(2)(3)
UFQFPN48 - 392.0
Power dissipation at
TA = 85 °C for suffix 6 VFQFPN68 - 425.0
PD mW
or WLCSP100 - 454.0
TA = 105 °C for suffix 7(4)
BGA129 - 342.5

Ambient temperature for the Maximum power dissipation 85

–40
suffix 6 version Low-power dissipation(5) 105
TA
Ambient temperature for the Maximum power dissipation 105
–40 °C
suffix 7 version Low-power dissipation(5) 125
Suffix 6 version 105
TJ Junction temperature range –40
Suffix 7 version 125
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between min (VDD, VDDA, VDDUSB, VLCD) + 3.6 V and 5.5V.
3. For operation with voltage higher than min (VDD, VDDA, VDDUSB, VLCD) + 0.3 V, the internal pull-up and pull-down resistors
must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.5: Thermal
characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.5:
Thermal characteristics).

6.3.3 RF BLE characteristics

RF characteristics are given at 1 Mbps, unless otherwise specified.

Table 23. RF transmitter BLE characteristics

Symbol Parameter Test conditions Min Typ Max Unit

Fop Frequency operating range - 2402 - 2480

MHz
Fxtal Crystal frequency - - 32 -

∆F Delta frequency - - 250 - KHz

Rgfsk On Air data rate - - 1 2 Mbps

PLLres RF channel spacing - - 2 - MHz

80/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 24. RF transmitter BLE characteristics (1 Mbps)(1)

Symbol Parameter Test conditions Min Typ Max Unit

SMPS Bypass or ON
(VFBSMPS = 1.7 V and - 6.0 -
VDD > 1.95 V)
Maximum output power
SMPS Bypass or ON
Prf (VFBSMPS = 1.4 V and - 3.7 - dBm
VDD > 1.71 V), Code 29

0 dBm output power - - 0 -

Minimum output power - - -20 -

Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB

BW20dB 20 dB signal bandwidth - - 670 - KHz

2 MHz Bluetooth® Low Energy:-20 dBm - -50 -
IBSE In band spurious emission dBm
®
≥ 3 MHz Bluetooth Low Energy: -30 dBm - -53 -

fd Frequency drift Bluetooth® Low Energy: ±50 kHz -50 - +50 KHz
®
Bluetooth Low Energy: KHz/
maxdr Maximum drift rate -20 - +20
±20 KHz / 50 µs 50 µs
Bluetooth® Low Energy:
fo Frequency offset -150 - +150
±150 kHz
KHz
Bluetooth® Low Energy:
∆f1 Frequency deviation average 225 - 275
between 225 and 275 kHz

Frequency deviation Bluetooth® Low Energy:> 0.80 0.80 - - -

∆fa
∆f2 (average) / ∆f1 (average)

Out of band < 1 GHz - - -61 -

OBSE(2) dBm
spurious emission ≥ 1 GHz - - -46 -
1. :Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and
impedance matching networks to interface with a 50 Ω antenna.
2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

DS11929 Rev 5 81/178

159
Electrical characteristics STM32WB55xx

Table 25. RF transmitter BLE characteristics (2 Mbps)(1)

Symbol Parameter Test conditions Min Typ Max Unit

SMPS Bypass or ON
(VFBSMPS = 1.7 V and - 6.0 -
VDD > 1.95 V)
Maximum output power
SMPS Bypass or ON
Prf (VFBSMPS = 1.4 V and - 3.7 - dBm
VDD > 1.71 V), Code 29

0 dBm output power - - 0 -

Minimum output power - - -20 -

Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB

BW20dB 20 dB signal bandwidth - - 670 - KHz

4 MHz Bluetooth® Low Energy:-20 dBm - -56 -
®
IBSE In band spurious emission 5 MHz Bluetooth Low Energy: -20 dBm - -57 - dBm
®
≥ 6 MHz Bluetooth Low Energy: -30 dBm -58

fd Frequency drift Bluetooth® Low Energy: ±50 kHz -50 - 50 KHz

Bluetooth® Low Energy: KHz/

maxdr Maximum drift rate -20 - 20
±20 KHz / 50 µs 50 µs

fo Frequency offset Bluetooth® Low Energy: ±150 kHz -150 - 150

Bluetooth®Low Energy: KHz
∆f1 Frequency deviation average 450 - 550
between 450 and 550 kHz

Frequency deviation Bluetooth® Low Energy:> 0.80 0.80 - - -

∆fa
∆f2 (average) / ∆f1 (average)

Out of band < 1 GHz - - -61 -

82/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 26. RF receiver BLE characteristics (1 Mbps)

Symbol Parameter Test conditions Typ Unit

PER <30.8%
Prx_max Maximum input signal 6
Bluetooth® Low Energy: min -10 dBm
High sensitivity mode (SMPS Bypass) PER <30.8% -96
Psens(1) ® dBm
High sensitivity mode (SMPS ON) Bluetooth Low Energy: max -70 dBm -95.5

Rssimaxrange RSSI maximum value - -7

Rssiminrange RSSI minimum value - -94

Rssiaccu RSSI accuracy - 2

DS11929 Rev 5 83/178

159
Electrical characteristics STM32WB55xx

Table 26. RF receiver BLE characteristics (1 Mbps) (continued)

Symbol Parameter Test conditions Typ Unit

30 to 2000 MHz
-3
Bluetooth® Low Energy: -30 dBm
2003 to 2399 MHz
-5
Bluetooth® Low Energy: -35 dBm
P_OBB Out of band blocking dBm
2484 to 2997 MHz
-2
Bluetooth® Low Energy: -35 dBm
3 to 12.75 GHz
7
Bluetooth® Low Energy: -30 dBm
1. With ideal TX.

Table 27. RF receiver BLE characteristics (2 Mbps)

Symbol Parameter Test conditions Typ Unit

PER <30.8%
Prx_max Maximum input signal 6
Bluetooth® Low Energy: min -10 dBm
High sensitivity mode (SMPS Bypass) PER <30.8% -93
Psens(1) dBm
High sensitivity mode (SMPS ON) Bluetooth® Low Energy: max -70 dBm -92.5

Rssimaxrange RSSI maximum value - -7

Rssiminrange RSSI minimum value - -94

Rssiaccu RSSI accuracy - 2

C/Ico Co-channel rejection Bluetooth® Low Energy spec: 21 dB 9

Adj ≥ 8MHz
-53
Bluetooth® Low Energy: -27 dB
Adj ≤ -8 MHz
-50
Bluetooth® Low Energy:-27 dB
Adj = 6 MHz
-49
Bluetooth® Low Energy:-27 dB
dB
Adj = -6 MHz
C/I Adjacent channel interference -46
Bluetooth® Low Energy:-15 dB
Adj = 4 MHz
-42
Bluetooth® Low Energy:-17 dB
Adj = 2 MHz
-3
Bluetooth® Low Energy:15 dB
Adj = -2 MHz
-3
Bluetooth® Low Energy:15 dB
C/Image Image rejection (Fimage = -4 MHz) Bluetooth® Low Energy: -9 dB -26

84/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 27. RF receiver BLE characteristics (2 Mbps) (continued)

Symbol Parameter Test conditions Typ Unit

|f2-f1| = 6 MHz
-29
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 8 MHz
P_IMD Intermodulation -30
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 10 MHz
-29
Bluetooth® Low Energy:-50 dBm
30 to 2000 MHz
-3 dBm
Bluetooth® Low Energy: -30 dBm
2003 to 2399 MHz
-9
Bluetooth® Low Energy: -35 dBm
P_OBB Out of band blocking
2484 to 2997 MHz
-3
Bluetooth® Low Energy: -35 dBm
3 to 12.75 GHz
4
Bluetooth® Low Energy: -30 dBm
1. With ideal TX.

Table 28. RF BLE power consumption for VDD = 3.3 V

Symbol Parameter Typ Unit

TX maximum output power consumption (SMPS Bypass) 12.7

Itxmax
TX maximum output power consumption (SMPS On, VFBSMPS = 1.7 V) 7.8
TX 0 dBm output power consumption (SMPS Bypass) 8.8
Itx0dbm mA
TX 0 dBm output power consumption (SMPS On, VFBSMPS = 1.4 V) 5.2
Rx consumption (SMPS Bypass) 7.9
Irxlo
Rx consumption (SMPS On, VFBSMPS = 1.4 V) 4.5

6.3.4 RF 802.15.4 characteristics

Table 29. RF transmitter 802.15.4 characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fop Frequency operating range - 2405 - 2480

Fxtal Crystal frequency - - 32 - MHz
∆F Delta frequency - - 5 -
Roqpsk On Air data rate - - 250 - Kbps
PLLres RF channel spacing - - 5 - MHz

DS11929 Rev 5 85/178

159
Electrical characteristics STM32WB55xx

Table 29. RF transmitter 802.15.4 characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

SMPS Bypass or ON
(VFBSMPS = 1.7 V) and - 5.7 -
VDD > 1.95 V)
Maximum output power(1)
SMPS Bypass or ON
Prf (VFBSMPS = 1.4 V and - 3.7 - dBm
VDD > 1.71 V)
0 dBm output power - - 0 -
Minimum output power - - -20 -
Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB
EVMrms EVM rms Pmax - 8 - %
Txpd Transmit power density |f - fc| > 3.5 MHz - -35 - dB
1. Measured in conducted mode, based on reference design (see AN5165), using output power specific
external RF filter and impedance matching networks to interface with a 50 Ω antenna.

Table 30. RF receiver 802.15.4 characteristics

Symbol Parameter Conditions Typ Unit

Prx_max Maximum input signal 6

Sensitivity (SMPS Bypass) PER < 1% -100 dBm
Rsens
Sensitivity (SMPS On) -98

C/adj Adjacent channel rejection - 35

dB
C/alt Alternate channel rejection - 46

Figure 17. Typical link quality indicator code vs. Rx level

240 TEST_NAME
220 TP/154/PHY24/RECEIVERͲ06/Ch11(2405MHz)
200
TP/154/PHY24/RECEIVERͲ06/Ch19(2445MHz)
180
160 TP/154/PHY24/RECEIVERͲ06/Ch26(2480MHz)

140
LQI

120
100
80
60
40
20
0
-120 -115-110 -105-100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20

Pin (dBm)
PARAM2

86/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Figure 18. Typical energy detection (T = 27°C, VDD = 3.3 V)

240
224
208
192
176
160
144

ED
128
112
96
80
64
48
32
16
0

Input power

Table 31. RF 802.15.4 power consumption for VDD = 3.3 V

Symbol Parameter Typ Unit

TX maximum output power consumption (SMPS Bypass) 11.7

Itxmax
TX maximum output power consumption (SMPS On, VFBSMPS = 1.7 V) 6.5
TX 0 dBm output power consumption (SMPS Bypass) 9.1
Itx0dbm mA
TX 0 dBm output power consumption (SMPS On, VFBSMPS = 1.4 V) 4.5
Rx consumption (SMPS Bypass) 9.2
Irxlo
Rx consumption (SMPS On) 4.5

DS11929 Rev 5 87/178

159
Electrical characteristics STM32WB55xx

6.3.5 Operating conditions at power-up / power-down

The parameters given in Table 32 are derived from tests performed under the ambient
temperature condition summarized in Table 22.

Table 32. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate - ∞

tVDD -
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA -
VDDA fall time rate 10 ∞
µs/V
VDDUSB rise time rate 0 ∞
tVDDUSB -
VDDUSB fall time rate 10 ∞
VDDRF rise time rate - ∞
tVDDRF -
VDDRF fall time rate - ∞

6.3.6 Embedded reset and power control block characteristics

The parameters given in Table 33 are derived from tests performed under the ambient
temperature conditions summarized in Table 22: General operating conditions.

Table 33. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

tRSTTEMPO(2) Reset temporization after BOR0 is detected VDD rising - 250 400 μs
Rising edge 1.62 1.66 1.70
VBOR0(2) Brown-out reset threshold 0
Falling edge 1.60 1.64 1.69
Rising edge 2.06 2.10 2.14
VBOR1 Brown-out reset threshold 1
Falling edge 1.96 2.00 2.04
Rising edge 2.26 2.31 2.35
VBOR2 Brown-out reset threshold 2
Falling edge 2.16 2.20 2.24
Rising edge 2.56 2.61 2.66
VBOR3 Brown-out reset threshold 3
Falling edge 2.47 2.52 2.57
V
Rising edge 2.85 2.90 2.95
VBOR4 Brown-out reset threshold 4
Falling edge 2.76 2.81 2.86
Rising edge 2.10 2.15 2.19
VPVD0 Programmable voltage detector threshold 0
Falling edge 2.00 2.05 2.10
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1
Falling edge 2.15 2.20 2.25
Rising edge 2.41 2.46 2.51
VPVD2 PVD threshold 2
Falling edge 2.31 2.36 2.41

88/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 33. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit

Rising edge 2.56 2.61 2.66

VPVD3 PVD threshold 3
Falling edge 2.47 2.52 2.57
Rising edge 2.69 2.74 2.79
VPVD4 PVD threshold 4
Falling edge 2.59 2.64 2.69
V
Rising edge 2.85 2.91 2.96
VPVD5 PVD threshold 5
Falling edge 2.75 2.81 2.86
Rising edge 2.92 2.98 3.04
VPVD6 PVD threshold 6
Falling edge 2.84 2.90 2.96
Hysteresis in
- 20 -
continuous mode
Vhyst_BORH0 Hysteresis voltage of BORH0
Hysteresis in
- 30 - mV
other mode
Hysteresis voltage of BORH (except
Vhyst_BOR_PVD - - 100 -
BORH0) and PVD
BOR(3) (except BOR0) and PVD
IDD (BOR_PVD)(2) - - 1.1 1.6 µA
consumption from VDD
VPVM1 VDDUSB peripheral voltage monitoring - 1.18 1.22 1.26
Rising edge 1.61 1.65 1.69 V
VPVM3 VDDA peripheral voltage monitoring
Falling edge 1.6 1.64 1.68
Vhyst_PVM3 PVM3 hysteresis - - 10 -
mV
Vhyst_PVM1 PVM1 hysteresis - - 10 -
IDD (PVM1)(2) PVM1 consumption from VDD - - 0.2 -
µA
IDD (PVM3)(2) PVM3 consumption from VDD - - 2 -
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current
characteristics tables.

DS11929 Rev 5 89/178

159
Electrical characteristics STM32WB55xx

6.3.7 Embedded voltage reference

The parameters given in Table 34 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 22: General operating
conditions.

Table 34. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –40 °C < TA < +125 °C 1.182 1.212 1.232 V
ADC sampling time when reading
tS_vrefint (1) - 4(2) - -
the internal reference voltage
µs
Start time of reference voltage
tstart_vrefint - - 8 12(2)
buffer when ADC is enable
VREFINT buffer consumption from
IDD(VREFINTBUF) - - 12.5 20(2) µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT VDD = 3 V - 5 7.5(2) mV
over the temperature range
TCoeff Temperature coefficient –40 °C < TA < +125 °C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25 °C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.

Figure 19. VREFINT vs. temperature

V
1.235

1.23

1.225

1.22

1.215

1.21

1.205

1.2

1.195

1.19

1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1

90/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.8 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 16: Current consumption
measurement scheme.

Typical and maximum current consumption

The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0434 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For Flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
The parameters given in Table 35 to Table 46 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 22: General
operating conditions.

DS11929 Rev 5 91/178

159
92/178

Electrical characteristics
Table 35. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V
Conditions Typ Max(1)
Symbol Parameter Unit
- Voltage fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C
scaling
16 MHz 1.90 1.90 2.00 2.20 2.40 2.52 2.96
Range 2
2 MHz 0.960 0.985 1.10 1.25 1.25 1.57 2.05
fHCLK = fHSI16 up to
16 MHz included, 64 MHz 8.15 8.25 8.40 8.60 9.30 9.60 10.02
Supply fHCLK = fHSE = 32 MHz Range 1 32 MHz 4.20 4.25 4.40 4.65 4.25 4.63 5.17
IDD(Run) current in fHSI16 + PLL ON
Run mode above 32 MHz 16 MHz 2.25 2.30 2.40 2.65 2.65 2.91 3.52
All peripherals 64 MHz 5.00 5.00 5.10 5.20 - - -
disabled SMPS mA
32 MHz 3.15 3.15 3.25 3.35 - - -
Range 1
DS11929 Rev 5

16 MHz 2.30 2.30 2.35 2.45 - - -

2 MHz 0.335 0.360 0.470 0.670 0.480 0.910 1.47
Supply
current in fHCLK = fMSI 1 MHz 0.170 0.210 0.325 0.520 0.270 0.730 1.31
IDD(LPRun)
Low-power All peripherals disabled 400 kHz 0.0815 0.120 0.230 0.425 0.140 0.590 1.18
run mode
100 kHz 0.0415 0.076 0.190 0.385 0.070 0.550 1.14
1. Guaranteed by characterization results, unless otherwise specified.

STM32WB55xx
Table 36. Current consumption in Run and Low-power run modes, code with data processing

STM32WB55xx
running from SRAM1, VDD = 3.3 V
Conditions Typ Max(1)
Symbol Parameter Unit
- Voltage fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C
scaling
16 MHz 2.00 2.05 2.15 2.30 2.57 3.04 3.64
Range 2
2 MHz 0.970 1.00 1.10 1.25 1.62 1.90 2.55
fHCLK = fHSI16 up to
16 MHz included, 64 MHz 8.80 8.90 9.00 9.20 10.50 10.80 11.30
Supply fHCLK = fHSE = 32 MHz Range 1 32 MHz 4.50 4.55 4.70 4.90 4.63 4.89 5.62
IDD(Run) current in fHSI16 + PLL ON
Run mode above 32 MHz 16 MHz 2.40 2.40 2.55 2.70 2.50 2.70 3.21
All peripherals 64 MHz 5.25 5.30 5.35 5.45 - - -
disabled SMPS mA
32 MHz 3.25 3.25 3.35 3.45 - - -
Range 1
16 MHz 2.35 2.35 2.40 2.45 - - -
DS11929 Rev 5

2 MHz 0.265 0.285 0.385 0.550 0.440 0.940 1.620

Supply
current in fHCLK = fMSI 1 MHz 0.135 0.170 0.270 0.430 0.290 0.760 1.480
IDD(LPRun)
Low-power All peripherals disabled 400 kHz 0.066 0.097 0.195 0.360 0.200 0.670 1.380
run mode
100 kHz 0.031 0.0625 0.160 0.325 0.170 0.470 1.330
1. Guaranteed by characterization results, unless otherwise specified.

Electrical characteristics
93/178
Electrical characteristics STM32WB55xx

Table 37. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V
Conditions TYP TYP
Symbol Parameter Unit Unit
Voltage
- Code 25 °C 25 °C
scaling

Reduced code(1) 1.90 119

fHCLK = 16 MHz
Coremark 1.85 116

Range 2
fHCLK = fHSI16 up to 16 MHz included, fHSI16 + PLL ON above 32 MHz Dhrystone 2.1 1.85 mA 116 µA/MHz
Fibonacci 1.75 109
While(1) 1.60 100
(1)
Reduced code 8.15 127
fHCLK = 64 MHz Coremark 8.00 125
Range 1

Dhrystone 2.1 8.10 mA 127 µA/MHz

All peripherals disable

Fibonacci 7.60 119

Supply current in While(1) 6.85 107

IDD(Run)
Run mode Reduced code(1) 5.00 78
fHCLK = 64 MHz, Range 1, SMPS On
fHCLK = 64 MHz

Coremark 4.95 77
Dhrystone 2.1 4.95 mA 77 µA/MHz
Fibonacci 4.75 74
While(1) 4.40 69
Reduced code(1) 4.07 64
Range 1, SMPS On

level = 0 dBm(2)
When RF Tx

Coremark 3.99 62
Dhrystone 2.1 4.04 mA 63 µA/MHz
Fibonacci 3.79 59
While(1) 3.42 53
Reduced code(1) 320 160
Coremark 350 175
Supply current in fHCLK = fMSI = 2 MHz
IDD(LPRun) Dhrystone 2.1 350 µA 175 µA/MHz
Low-power run All peripherals disable
Fibonacci 390 195
While(1) 225 113
1. Reduced code used for characterization results provided in Table 35 and Table 36.
2. Value computed. MCU consumption when RF TX and SMPS are ON.

94/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 38. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V
Conditions TYP TYP
Symbol Parameter Unit Unit
Voltage
- Code 25 °C 25 °C
scaling

Reduced code(1) 2.00 125

fHCLK = 16 MHz
Coremark 1.75 109

Range 2
fHCLK = fHSI16 up to 16 MHz included, fHSI16 + PLL ON above 32 MHz
Dhrystone 2.1 1.95 mA 122 µA/MHz
Fibonacci 1.85 116
While(1) 1.85 116
Reduced code(1) 8.80 138

fHCLK = 64 MHz
Range 1 Coremark 7.50 117
Dhrystone 2.1 8.60 mA 134 µA/MHz
All peripherals disable

Fibonacci 7.90 123

Supply current in While(1) 8.00 125

IDD(Run)
Run mode Reduced code(1) 5.25 82
fHCLK = 64 MHz, Range 1, SMPS On
fHCLK = 64 MHz

Coremark 4.65 73
Dhrystone 2.1 5.15 mA 80 µA/MHz
Fibonacci 4.85 76
While(1) 4.90 77
Reduced code(1) 4.39 69
Range 1, SMPS On

level = 0 dBm(2)
When RF Tx

Coremark 3.74 58
Dhrystone 2.1 4.29 mA 67 µA/MHz
Fibonacci 3.94 62
While(1) 3.99 62
Reduced code(1) 255 128
Coremark 205 103
Supply current in fHCLK = fMSI = 2 MHz
IDD(LPRun) Dhrystone 2.1 250 µA 125 µA/MHz
Low-power run All peripherals disable
Fibonacci 230 115
While(1) 220 110
1. Reduced code used for characterization results provided in Table 35 and Table 36.
2. Value computed. MCU consumption when RF TX and SMPS are ON.

DS11929 Rev 5 95/178

159
96/178

Electrical characteristics
Table 39. Current consumption in Sleep and Low-power sleep modes, Flash memory ON
Conditions TYP MAX(1)
Symbol Parameter Unit
Voltage
- fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C
scaling

fHCLK = fHSI16 up Range 2 16 MHz 0.740 0.765 0.865 1.05 0.840 1.210 1.810
to 16 MHz
64 MHz 2.65 2.70 2.80 3.00 3.00 3.33 3.91
included,
fHCLK = fHSE up Range 1 32 MHz 1.40 1.45 1.60 1.80 1.55 1.86 2.49
Supply
to 32 MHz
IDD(Sleep) current in 16 MHz 0.845 0.875 0.990 1.20 0.970 1.40 2.02
sleep mode, fHSI16 + PLL ON
above 32 MHz 64 MHz 2.60 2.60 2.65 2.75 - - -
SMPS
32 MHz 1.90 1.95 2.00 2.10 - - - mA
All peripherals Range 1
disabled 16 MHz 1.70 1.70 1.75 1.80 - - -
2 MHz 0.090 0.125 0.235 0.430 0.130 0.600 1.19
Supply
DS11929 Rev 5

current in fHCLK = fMSI 1 MHz 0.058 0.093 0.205 0.400 0.090 0.570 1.16
IDD(LPSleep)
low-power All peripherals disabled 400 kHz 0.044 0.0725 0.185 0.380 0.070 0.540 1.11
sleep mode
100 kHz 0.0315 0.0635 0.0175 0.370 0.055 0.530 1.13
1. Guaranteed by characterization results, unless otherwise specified.

Table 40. Current consumption in Low-power sleep modes, Flash memory in Power down
Conditions TYP MAX(1)
Paramet
Symbol Unit
er
- fHCLK 25 °C 55 °C 85 °C 105 °C 25 °C 85 °C 105 °C

Supply fHCLK = 2 MHz 94.0 115 200 335 135 610 1201
IDD(LPSl current in fMSI 1 MHz 56.5 86.0 170 305 94.2 560 1171
low- µA
eep) 400 kHz 40.5 66.5 150 285 68.0 540 1129
power All
sleep periphera 100 kHz 27.5 57.5 140 275 54.6 539 1131

STM32WB55xx
1. Guaranteed by characterization results, unless otherwise specified.
Table 41. Current consumption in Stop 2 mode

STM32WB55xx
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C
1.8 V 1.00 1.85 3.15 5.95 21.5 50.0 1.58 4.12 56.9 132.7
LCD disabled 2.4 V 1.10 1.85 3.20 6.00 22.0 51.0 - - - -
BLE disabled 3.0 V 1.10 1.85 3.25 6.10 22.0 52.0 1.60 4.17 57.9 135.6
Supply current
IDD in Stop 2 3.6 V 1.15 1.95 3.35 6.25 23.0 53.0 1.69 4.40 58.6 135.7
(Stop 2) mode, RTC
LCD enabled(2) 1.8 V 1.20 2.00 3.35 6.10 22.0 50.5 1.76 4.30 57.1 133.3
disabled
and clocked 2.4 V 1.20 2.00 3.40 6.20 22.0 51.0 - - - -
by LSI 3.0 V 1.25 2.10 3.45 6.30 22.5 52.0 1.85 4.41 58.1 135.8
BLE disabled
3.6 V 1.30 2.15 3.60 6.55 23.0 53.5 1.97 4.66 59.4 136.6
1.8 V 1.30 2.10 3.45 6.25 22.0 50.5 1.91 4.50 57.2 133.0
RTC clocked 2.4 V 1.45 2.25 3.55 6.40 22.5 51.5 - - - -
by LSI, µA
LCD disabled 3.0 V 1.50 2.30 3.70 6.55 22.5 52.5 2.11 4.64 58.3 136.1
DS11929 Rev 5

3.6 V 1.75 2.50 3.95 6.85 23.5 53.5 2.26 5.12 59.7 136.9
Supply current 1.8 V 1.35 2.20 3.55 6.30 22.0 50.5 1.99 4.57 57.4 133.8
IDD
in Stop 2 RTC clocked 2.4 V 1.50 2.35 3.65 6.50 22.5 51.5 - - - -
(Stop 2
mode, RTC by LSI,
with (2) 3.0 V 1.70 2.45 3.85 6.65 23.0 52.5 2.17 4.87 58.4 136.3
enabled, BLE LCD enabled
RTC)
disabled 3.6 V 1.80 2.60 4.05 6.95 23.5 54.0 2.41 5.11 59.9 137.1

RTC clocked by 1.8 V 1.35 2.20 3.50 6.25 22.0 50.5 1.91 4.29 57.1 133.5
LSE quartz(3) 2.4 V 1.45 2.25 3.65 6.40 22.5 51.5 - - - -
in low drive 3.0 V 1.55 2.45 3.80 6.65 23.0 52.5 2.01 4.31 58.0 135.9
mode
3.6 V 1.70 2.55 4.05 6.95 23.5 54.0 2.16 4.40 81.6 137.0

Electrical characteristics
97/178
Table 41. Current consumption in Stop 2 mode (continued)
98/178

Electrical characteristics
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C
Wakeup clock is
HSI16, voltage 3.0 V - 389 - - - - - - - -
Range 2. See(4).
Supply current Wakeup clock is
IDD
during MSI = 32 MHz,
(wakeup 3.0 V - 320 - - - - - - - -
wakeup from voltage µA
from (4)
Stop 2 mode Range 1. See .
Stop 2)
bypass mode Wakeup clock is
MSI = 4 MHz,
3.0 V - 528 - - - - - - - -
voltage
(4)
Range 2. See .
1. Guaranteed based on test during characterization, unless otherwise specified.
2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD
DS11929 Rev 5

3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading
capacitors.
4. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49: Low-power mode
wakeup timings.

STM32WB55xx
Table 42. Current consumption in Stop 1 mode

STM32WB55xx
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C
1.8 V 5.05 9.20 15.5 28.0 96.0 210 7.00 28.4 343.7 738.6
BLE disabled 2.4 V 5.10 9.25 15.5 28.5 96.5 215 - - - -
Supply LCD disabled 3.0 V 5.15 9.30 15.5 28.5 97.0 215 7.07 28.5 346.8 746.0
current in 3.6 V 5.25 9.45 16.0 29.0 97.5 215 7.30 28.8 351.0 749.4
IDD
Stop 1 mode,
(Stop 1) 1.8 V 5.05 9.30 15.5 28.5 96.0 210 7.10 28.7 344.4 739.0
RTC
BLE disabled 2.4 V 5.10 9.35 16.0 28.5 96.5 215 - - - -
disabled
LCD enabled(2),
clocked by LSI 3.0 V 5.20 9.65 16.0 28.5 97.0 215 7.26 29.6 345.0 747.0
3.6 V 5.55 9.85 16.0 29.0 98.5 215 7.62 29.8 349.0 750.8
1.8 V 5.30 9.35 16.0 28.5 96.5 215 7.30 29.5 343.7 739.2
RTC clocked by LSI 2.4 V 5.40 9.45 16.0 28.5 97.0 215 - - - -
µA
LCD disabled 3.0 V 5.70 9.55 16.5 29.0 98.5 220 7.69 29.7 347.2 746.1
DS11929 Rev 5

3.6 V 5.85 10.0 16.5 29.5 96.5 215 8.08 29.8 349.9 751.1
Supply
IDD current in 1.8 V 5.25 9.60 16.0 28.5 96.5 215 7.10 29.0 344.3 739.9
(Stop 1 Stop 1 mode, RTC clocked by LSI 2.4 V 5.30 9.75 16.0 29.0 97.0 215 - - - -
with RTC LCD enabled(2) 3.0 V 5.85 9.80 16.5 29.0 97.5 215 7.53 29.8 347.4 746.2
RTC) enabled,
3.6 V 5.90 10.5 16.5 29.0 98.5 220 8.18 29.9 350.6 751.8
BLE disabled
1.8 V 5.35 9.55 16.0 28.5 96.5 215 6.00 28.7 343.9 738.7
RTC clocked by 2.4 V 5.40 9.70 16.0 29.0 96.5 215 - - - -
LSE quartz(3) in
Low drive mode 3.0 V 5.75 9.70 16.0 29.0 97.5 215 7.40 28.9 346.6 743.8
3.6 V 5.90 10.0 16.5 29.5 99.0 220 7.58 29.2 349.0 749.9

Electrical characteristics
99/178
Table 42. Current consumption in Stop 1 mode (continued)
100/178

Electrical characteristics
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C
Wakeup clock
HSI16,
3.0 V - 129 - - - - - - - -
voltage Range 2.
Supply See (4).
IDD current Wakeup clock
(wakeup during MSI = 32 MHz,
3.0 V - 124 - - - - - - - - µA
from wakeup from voltage Range 1.
Stop1) Stop 1 See (4).
bypass mode Wakeup clock
MSI = 4 MHz,
3.0 V - 207 - - - - - - - -
voltage Range 2.
See (4).
1. Guaranteed based on test during characterization, unless otherwise specified.
DS11929 Rev 5

2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 49: Low-power mode wakeup
timings.

STM32WB55xx
Table 43. Current consumption in Stop 0 mode

STM32WB55xx
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

1.8 V 95.5 100 110 120 195 315 110.0 114.2 458.1 874.8
Supply current
in Stop 0 mode, 2.4 V 97.5 105 110 125 195 315 - - - -
RTC disabled, --
BLE disabled, 3.0 V 98.5 105 110 125 195 320 117.3 134.3 461.8 880.0
LCD disabled
3.6 V 100 105 115 125 200 320 165.0 135.7 494.0 884.1
Wakeup clock
HSI16,
IDD 3.0 V - 331 - - - - - - - -
voltage Range 2. µA
(Stop 0) See (2).

Supply current Wakeup clock is

during wakeup MSI = 32 MHz,
3.0 V - 349 - - - - - - - -
DS11929 Rev 5

from Stop 0 voltage Range 1.

(2).
Bypass mode See
Wakeup clock is
MSI = 4 MHz,
3.0 V - 196 - - - - - - - -
voltage Range 2.
(2).
See
1. Guaranteed by characterization results, unless otherwise specified.
2. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49: Low-power mode
wakeup timings.

Electrical characteristics
101/178
Table 44. Current consumption in Standby mode
102/178

Electrical characteristics
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C
1.8 V 0.270 0.320 0.515 0.920 3.45 8.20 0.300 0.828 7.850 19.300
BLE disabled 2.4 V 0.270 0.350 0.540 0.955 3.50 8.80 - - - -
Supply current No independent
in Standby watchdog 3.0 V 0.270 0.370 0.575 1.00 3.85 9.50 0.380 0.945 8.505 21.200
mode (backup 3.6 V 0.300 0.410 0.645 1.15 4.20 10.50 0.400 1.040 8.980 22.400
IDD
registers and
(Standby) 1.8 V 0.265 0.525 0.710 1.10 3.90 8.40 0.520 1.095 8.041 19.500
SRAM2a BLE disabled
retained), With 2.4 V 0.280 0.595 0.790 1.20 4.00 9.05 - - - -
RTC disabled independent
3.0 V 0.290 0.670 0.855 1.35 4.15 9.80 0.730 1.253 8.774 21.400
watchdog
3.6 V 0.295 0.770 0.990 1.50 4.60 11.00 0.851 1.356 9.360 22.840
1.8 V 0.500 0.600 0.780 1.20 3.70 8.45 0.680 1.165 8.143 19.660
RTC clocked by
LSI, no 2.4 V 0.630 0.705 0.910 1.30 3.80 9.10 - - - -
µA
independent 3.0 V 0.725 0.825 1.050 1.50 3.95 9.90 0.930 1.463 8.977 21.440
DS11929 Rev 5

watchdog
Supply current 3.6 V 0.860 0.970 1.200 1.70 4.25 11.00 1.050 1.628 9.634 23.080
in Standby
1.8 V 0.565 0.655 0.830 1.25 3.75 8.55 0.734 1.196 8.187 19.710
mode (backup RTC clocked by
IDD 2.4 V 0.635 0.790 0.975 1.40 4.10 9.20 - - - -
registers and LSI, with
(Standby with
SRAM2a independent 3.0 V 0.725 0.915 1.100 1.55 4.50 10.00 1.028 1.573 9.072 21.810
RTC)
retained), watchdog
3.6 V 0.870 1.050 1.300 1.80 4.90 11.00 1.144 1.723 9.730 23.200
RTC enabled
BLE disabled 1.8 V 0.525 0.625 0.840 1.25 3.75 8.60 0.600 1.061 8.029 19.610
RTC clocked by 2.4 V 0.665 0.755 0.960 1.35 4.05 9.25 - - - -
LSE quartz (2) in
low drive mode 3.0 V 0.775 0.880 1.100 1.55 4.40 10.00 0.600 1.100 8.719 21.570
3.6 V 0.935 1.050 1.300 1.80 5.00 11.00 0.750 1.171 9.460 23.030

STM32WB55xx
Table 44. Current consumption in Standby mode (continued)

STM32WB55xx
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

Supply 1.8 V 0.160 0.210 0.380 0.660 2.30 5.15 - - - -

current to be
subtracted in 2.4 V 0.165 0.245 0.375 0.650 2.15 5.20 - - - -
IDD
(3) Standby - µA
(SRAM2a)
mode when 3.0 V 0.155 0.250 0.385 0.630 2.25 5.20 - - - -
SRAM2a is
not retained 3.6 V 0.155 0.235 0.375 0.670 2.20 5.20 - - - -

Supply current
IDD Wakeup clock is
during
(wakeup from HSI16. See (4). 3.0 V - 1.73 - - - - - - - - mA
wakeup from
Standby) SMPS OFF
Standby mode
1. Guaranteed by characterization results, unless otherwise specified.
DS11929 Rev 5

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading
capacitors.
3. The supply current in Standby with SRAM2a mode is: IDD(Standby) + IDD(SRAM2a). The supply current in Standby with RTC with
SRAM2a mode is: IDD(Standby + RTC) + IDD(SRAM2a).
4. Wakeup with code execution from Flash memory. Average value given for a typical wakeup time as specified in Table 49.

Electrical characteristics
103/178
Table 45. Current consumption in Shutdown mode
104/178

Electrical characteristics
Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 85 °C 105 °C

Supply current in 1.8 V 0.039 0.013 0.030 0.100 0.635 1.950 - - 2.099 6.200
Shutdown mode
2.4 V 0.059 0.014 0.055 0.120 0.785 2.350 - - - -
IDD (backup
-
(Shutdown) registers
3.0 V 0.064 0.037 0.070 0.180 1.000 2.900 - 0.185 2.670 7.490
retained) RTC
disabled 3.6 V 0.071 0.093 0.140 0.280 1.300 3.700 - 0.247 3.120 8.450
µA
Supply current in 1.8 V 0.320 0.315 0.355 0.420 0.985 2.300 - 0.572 2.702 6.180
Shutdown mode RTC clocked
IDD 2.4 V 0.425 0.405 0.460 0.540 1.200 2.800 - - - -
(backup by LSE
(Shutdown
registers quartz (2) in low
with RTC) 3.0 V 0.535 0.535 0.595 0.700 1.500 3.450 - 0.664 2.990 7.800
retained) RTC drive mode
enabled 3.6 V 0.695 0.720 0.790 0.940 2.000 4.350 - 0.790 3.730 9.140
DS11929 Rev 5

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.

Table 46. Current consumption in VBAT mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VBAT 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C
1.8 V 1.00 2.00 4.00 10.0 52.0 145 - - - - - -
2.4 V 1.00 2.00 5.00 12.0 60.0 165 - - - - - -
RTC disabled
3.0 V 2.00 4.00 7.00 16.0 75.0 225 - - - - - -
Backup
domain 3.6 V 7.00 15.0 23.0 42.0 170 450 - - - - - -
IDD(VBAT) nA
supply 1.8 V 295 305 315 325 380 480 - - - - - -
current RTC enabled
and clocked 2.4 V 385 395 400 415 475 595 - - - - - -
by LSE 3.0 V 495 505 515 530 600 765 - - - - - -

STM32WB55xx
quartz(2)
3.6 V 630 645 660 685 830 1150 - - - - - -
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
Table 47. Current under Reset condition

STM32WB55xx
TYP MAX(1)
Symbol Conditions Unit
0 °C 25 °C 40 °C 55 °C 85 °C 105 °C 0 °C 25 °C 40 °C 55 °C 85 °C 105 °C
1.8 V - 410 - - - - - - - - - -
2.4 V - - - - - - - - - - - -
IDD(RST) nA
3.0 V - 550 - - - - - 750 - - - -
3.6 V - 750 - - - - - - - - - -
1. Guaranteed by characterization results, unless otherwise specified.
DS11929 Rev 5

Electrical characteristics
105/178
Electrical characteristics STM32WB55xx

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 69: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 48: Peripheral current consumption, the I/Os used by an application also contribute to
the current consumption. When an I/O pin switches, it uses the current from the I/O supply
voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or
external) connected to the pin:

I SW = V DD × f SW × C

where
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDD is the I/O supply voltage
• fSW is the I/O switching frequency
• C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
• CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

106/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 48. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 48. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.

Table 48. Peripheral current consumption

Low-power
Peripheral Range 1 Range 2 Unit
run and sleep

Bus Matrix(1) 2.40 2.00 1.80

TSC 1.25 1.05 1.05
CRC 0.465 0.375 0.380
AHB1 DMA1 1.90 1.55 1.80
DMA2 2.00 1.65 1.80
DMAMUX 4.15 3.40 4.45
All AHB1 Peripherals 12.0 10.0 11.5
AES1 4.00 3.30 3.90
ADC independent clock domain 2.55 2.10 2.10
AHB2(2)
ADC clock domain 2.25 1.90 1.90 µA/MHz
All AHB2 Peripherals 7.45 6.20 6.60
AHB3 QSPI 7.60 6.25 7.10
TRNG independent clock domain 3.80 N/A N/A
TRNG clock domain 2.00 N/A N/A
SRAM2 0.170 0.135 0.135
AHB Shared FLASH 8.35 6.90 8.45
AES2 6.95 5.75 7.00
PKA 4.40 3.65 4.25
All AHB Shared Peripherals 17.5 14.5 16.0

DS11929 Rev 5 107/178

159
Electrical characteristics STM32WB55xx

Table 48. Peripheral current consumption (continued)

Low-power
Peripheral Range 1 Range 2 Unit
run and sleep

RTCA 1.10 0.88 1.25

CRS 0.24 0.20 0.20
USB FS independent clock domain 3.20 N/A N/A
USB FS clock domain 2.05 N/A N/A
I2C1 independent clock domain 2.50 4.40 4.40
I2C1 clock domain 4.80 4.00 5.50
I2C3 independent clock domain 2.10 3.50 3.55
I2C3 clock domain 3.70 3.10 3.55
LCD 1.35 1.10 2.10
APB1 SPI2 1.65 1.40 2.25
LPTIM1 independent clock domain 2.10 3.40 3.00
LPTIM1 clock domain 3.60 3.00 3.80
TIM2 5.65 4.70 4.90
LPUART1 independent clock domain 2.70 4.15 3.85
LPUART1 clock domain 4.45 3.70 5.25
µA/MHz
LPTIM2 clock domain 3.95 3.25 4.50
LPTIM2 independent clock domain 2.20 3.70 3.80
WWDG 0.335 0.285 0.965
All APB1 Peripherals 27.0 22.5 25.5
(3)
AHB to APB2 1.10 0.885 1.35
TIM1 8.20 6.80 7.25
TIM17 2.85 2.40 2.40
TIM16 2.75 2.30 2.55
USART1 independent clock domain 4.40 7.80 7.00
APB2
USART1 clock domain 8.80 7.30 7.75
SPI1 1.75 1.45 1.45
SAI1 independent clock domain 2.50 1.50 3.50
SAI1 clock domain 2.40 N/A N/A
All APB2 on 28.0 23.0 25.5
ALL 97.5 80.5 90.0
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. GPIOs consumption during read and write accesses.
3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

108/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.9 Wakeup time from Low-power modes and voltage scaling

transition times
The wakeup times given in Table 49 are the latency between the event and the execution of
the first user instruction.
The device goes in Low-power mode after the WFE (Wait For Event) instruction.

Table 49. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time from

tWUSLEEP Sleep mode - 9 10
to Run mode No. of
CPU
Wakeup time from Wakeup in Flash with memory in power-down cycles
tWULPSLEEP Low-power sleep mode during low-power sleep mode (FPDS = 1 in 9 10
to Low-power run mode PWR_CR1) and with clock MSI = 2 MHz

Wakeup clock MSI = 32 MHz 2.38 2.96

Wake up time from Range 1
Stop 0 mode Wakeup clock HSI16 = 16 MHz 1.69 2.00
to Run mode in Flash Wakeup clock HSI16 = 16 MHz 1.70 2.01
memory Range 2
Wakeup clock MSI = 4 MHz 7.43 8.59
tWUSTOP0
Wakeup clock MSI = 32 MHz 2.63 3.00
Range 1
Wake up time from Wakeup clock HSI16 = 16 MHz 1.80 2.00
Stop 0 mode
to Run mode in SRAM1 Wakeup clock HSI16 = 16 MHz 1.82 2.02
Range 2
Wakeup clock MSI = 4 MHz 7.58 8.70
Wakeup clock MSI = 32 MHz 4.67 5.56
Wake up time from Range 1
Stop 1 mode Wakeup clock HSI16 = 16 MHz 5.09 6.03
to Run in Flash memory Wakeup clock HSI16 = 16 MHz 5.08 6.00
SMPS bypassed Range 2 µs
Wakeup clock MSI = 4 MHz 8.36 9.28
Wakeup clock MSI = 32 MHz 4.88 5.55
Wake up time from Range 1
Stop 1 mode Wakeup clock HSI16 = 16 MHz 5.29 5.95
to Run in SRAM1 Wakeup clock HSI16 = 16 MHz 5.28 5.96
tWUSTOP1 SMPS bypassed Range 2
Wakeup clock MSI = 4 MHz 8.49 9.30
Wake up time from
Stop 1 mode to
7.96 9.59
Low-power run mode Regulator in
in Flash memory Low-power
Wakeup clock MSI = 4 MHz
Wake up time from mode (LPR = 1
Stop 1 mode to in PWR_CR1)
8.00 9.47
Low-power run mode
in SRAM1

DS11929 Rev 5 109/178

159
Electrical characteristics STM32WB55xx

Table 49. Low-power mode wakeup timings(1) (continued)

Symbol Parameter Conditions Typ Max Unit

Wake up time from Wakeup clock MSI = 32 MHz 5.27 6.07

Range 1
Stop 2 mode Wakeup clock HSI16 = 16 MHz 5.71 6.52
to Run mode in Flash
memory Wakeup clock HSI16 = 16 MHz 5.72 6.52
Range 2
SMPS bypassed Wakeup clock MSI = 4 MHz 9.10 9.93
tWUSTOP2 µs
Wakeup clock MSI = 32 MHz 5.20 5.94
Wake up time from Range 1
Stop 2 mode to Run Wakeup clock HSI16 = 16 MHz 5.64 6.42
mode in SRAM1 Wakeup clock HSI16 = 16 MHz 5.64 6.43
SMPS bypassed Range 2
Wakeup clock MSI = 4 MHz 9.05 9.85
Wakeup time from
Standby mode
tWUSTBY Range 1 Wakeup clock HSI16 = 16 MHz 51.0 58.1 µs
to Run mode
SMPS Bypassed
1. Guaranteed by characterization results (VDD = 3 V, .T = 25 °C).

Table 50. Regulator modes transition times(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time from Low-power run mode to

tWULPRUN Code run with MSI 2 MHz 15.33 16.30
Run mode(2)
µs
Regulator transition time from Range 2 to
tVOST Code run with HSI16 21.4 28.9
Range 1 or Range 1 to Range 2(3)
1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C).
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.

Table 51. Wakeup time using LPUART(1)

Symbol Parameter Conditions Typ Max Unit

Wakeup time needed to calculate the maximum Stop mode 0 - 1.7

tWULPUART LPUART baud rate allowing to wakeup up from Stop µs
mode when LPUART clock source is HSI16 Stop mode 1/2 - 8.5

1. Guaranteed by design.

110/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.10 External clock source characteristics

High-speed external user clock generated from an external source
The high-speed external (HSE) clock must be supplied with a 32 MHz crystal oscillator.
The STM32WB55xx include internal programmable capacitances that can be used to tune
the crystal frequency in order to compensate the PCB parasitic one.
The characteristics in Table 52 and Table 53 are measured over recommended operating
conditions, unless otherwise specified. Typical values are referred to TA = 25 °C and
VDD = 3.0 V.

Table 52. HSE crystal requirements(1)

Symbol Parameter Conditions Min Typ Max Unit

fNOM Oscillator frequency - - 32 - MHz

Includes initial accuracy, stability over
fTOL Frequency tolerance temperature, aging and frequency pulling - - 20 ppm
due to incorrect load capacitance.
CL Load capacitance - 6 - 8 pF
ESR Equivalent series resistance - - - 100 Ω
PD Drive level - - - 100 µW
1. 32 MHz XTAL is specified for two specific references: NX2016SA and NX1612SA.

Table 53. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

Startup time VDDRF stabilized, XOTUNE=000000,

tSUA(HSE) - 1000 -
for 80% amplitude stabilization -40 to +125 °C range
µs
Startup time VDDRF stabilized, XOTUNE=000000,
tSUR(HSE) - 250 -
for XOREADY signal -40 to +125 °C range
IDDRF(HSE) HSE current consumption HSEGMC=000, XOTUNE=000000 - 50 - µA
XOTg(HSE) XOTUNE granularity - 1 5
ppm
XOTfp(HSE) XOTUNE frequency pulling ±20 ±40 -
Capacitor bank
XOTnb(HSE) XOTUNE number of tuning bits - 6 - bit
XOTst(HSE) XOTUNE setting time - - 0.1 ms

Note: For information about the trimming of the oscillator, refer to application note AN5042 “HSE
trimming for RF applications using the STM32WB Series”.

Low-speed external user clock generated from an external source

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. The information provided in this section is based on design simulation results
obtained with typical external components specified in Table 54. In the application, the

DS11929 Rev 5 111/178

159
Electrical characteristics STM32WB55xx

resonator and the load capacitors have to be placed as close as possible to the oscillator
pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 54. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.50
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 10
- - 1.70
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.70
High drive capability
tSU(LSE)(2) Startup time VDD stabilized - 2 - s
1. Guaranteed by design.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stable 32 MHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal refer to application note AN2867 “Oscillator design
guide for STM8S, STM8A and STM32 microcontrollers” available from www.st.com.

Figure 20. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

112/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden
to add one.
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics detailed in Section 6.3.17.
The recommend clock input waveform is shown in Figure 21.

Figure 21. Low-speed external clock source AC timing diagram

tw(LSEH)

VLSEH
90%
10%
VLSEL

tr(LSE) t
tf(LSE) tw(LSEL)
TLSE

MS19215V2

Table 55. Low-speed external user clock characteristics(1) – Bypass mode

Symbol Parameter Conditions Min Typ Max Unit

User external clock

fLSE_ext - 21.2 32.768 44.4 kHz
source frequency
OSC32_IN input pin
VLSEH - 0.7 VDDx - VDDx
high level voltage
V
OSC32_IN input pin
VLSEL - VSS - 0.3 VDDx
low level voltage
tw(LSEH) OSC32_IN high or
- 250 - - ns
tw(LSEL) low time
Includes initial
accuracy, stability over
ftolLSE Frequency tolerance -500 - +500 ppm
temperature, aging and
frequency pulling
1. Guaranteed by design.

6.3.11 Internal clock source characteristics

The parameters given in Table 56 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 22: General operating
conditions. The provided curves are characterization results, not tested in production.

DS11929 Rev 5 113/178

159
Electrical characteristics STM32WB55xx

High-speed internal (HSI16) RC oscillator

Table 56. HSI16 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
HSI16 oscillator frequency drift over TA= 0 to 85 °C -1 - 1
∆Temp(HSI16)
temperature TA= -40 to 125 °C -2 - 1.5
HSI16 oscillator frequency drift over
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05
VDD
tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2
μs
tstab (HSI16)(2) HSI16 oscillator stabilization time - - 3 5
IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA
1. Guaranteed by characterization results.
2. Guaranteed by design.

Figure 22. HSI16 frequency vs. temperature

MHz
16.4
+2%
16.3
+1.5%
16.2 +1%

16.1

15.9

-1%
15.8
-1.5%
15.7
-2%
15.6
-40 -20 0 20 40 60 80 100 120 °C
min mean max
MSv39299V1

114/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Multi-speed internal (MSI) RC oscillator

Table 57. MSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Range 0 98.7 100 101.3

Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31

MSI frequency Range 10 31.58 32 32.42

after factory Range 11 47.38 48 48.62
fMSI calibration, done
at VDD=3 V and Range 0 - 98.304 -
TA=30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL=
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA= -0 to 85 °C -3.5 - 3
∆TEMP(MSI)(2) frequency drift MSI mode %
over temperature TA= -40 to 125 °C -8 - 6

DS11929 Rev 5 115/178

159
Electrical characteristics STM32WB55xx

Table 57. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

VDD =
-1.2 -
1.62 to 3.6 V
Range 0 to 3 0.5
VDD =
-0.5 -
2.4 to 3.6 V

MSI oscillator VDD =

-2.5 -
frequency drift 1.62 to 3.6 V
∆VDD(MSI)(2) MSI mode Range 4 to 7 0.7
over VDD VDD =
(reference is 3 V) -0.8 -
2.4 to 3.6 V %
VDD =
-5 -
1.62 to 3.6 V
Range 8 to 11 1
VDD =
-1.6 -
2.4 to 3.6 V
Frequency TA= -40 to 85 °C - 1 2
∆FSAMPLING
variation in MSI mode
(MSI)(2)(6) TA= -40 to 125 °C - 2 4
sampling mode(3)
For next
- - - 3.458
P_USB Period jitter for PLL mode transition
Jitter(MSI)(6) USB clock(4) Range 11 For paired
- - - 3.916
transition
ns
For next
- - - 2
MT_USB Medium term jitter PLL mode transition
Jitter(MSI)(6) for USB clock(5) Range 11 For paired
- - - 1
transition
RMS cycle-to-
CC jitter(MSI)(6) PLL mode Range 11 - - 60 -
cycle jitter ps
P jitter(MSI)(6) RMS period jitter PLL mode Range 11 - - 50 -
Range 0 - - 10 20
Range 1 - - 5 10

MSI oscillator Range 2 - - 4 8

tSU(MSI)(6) μs
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(6) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency

116/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 57. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(6) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI at 48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI at 48 MHz clock.
5. Only accumulated jitter of MSI at 48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI at 48 MHz, for 1000 captures over
28 cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI at 48 MHz, for 1000 captures over
56 cycles.
6. Guaranteed by design.

DS11929 Rev 5 117/178

159
Electrical characteristics STM32WB55xx

Figure 23. Typical current consumption vs. MSI frequency

High-speed internal 48 MHz (HSI48) RC oscillator

Table 58. HSI48 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 frequency VDD = 3.0 V, TA = 30 °C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11(2) 0.18(2)
USER TRIM
HSI48 user trimming coverage ±32 steps ±3(3) ±3.5(3) -
COVERAGE
DuCy(HSI48) Duty cycle - 45(2) - 55(2)
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48 oscillator - - ±3(3) %
TA = –15 to 85 °C
ACCHSI48_REL over temperature
(factory calibrated) VDD = 1.65 V to 3.6 V,
- - ±4.5(3)
TA = –40 to 125 °C

HSI48 oscillator frequency drift VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

DVDD(HSI48)
with VDD VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)
tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs
IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA

118/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 58. HSI48 oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Next transition jitter

NT jitter - - ±0.15(2) -
Accumulated jitter on 28 cycles(4)
ns
Paired transition jitter (2)
PT jitter - - ±0.25 -
Accumulated jitter on 56 cycles(4)
1. VDD = 3 V, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.

Figure 24. HSI48 frequency vs. temperature

%
6

-2

-4

-6
-50 -30 -10 10 30 50 70 90 110 130
°C
Avg min max
MSv40989V1

Low-speed internal (LSI) RC oscillator

Table 59. LSI1 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI1 frequency kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34
tSU(LSI1)(2) LSI1 oscillator start-up time - - 80 130
μs
tSTAB(LSI1)(2) LSI1 oscillator stabilization time 5% of final frequency - 125 180
LSI1 oscillator power
IDD(LSI1)(2) - - 110 180 nA
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.

DS11929 Rev 5 119/178

159
Electrical characteristics STM32WB55xx

Table 60. LSI2 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TA = 30 °C 21.6 - 44.2

fLSI2 LSI2 frequency kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 21.2 - 44.4
tSU(LSI2)(2) LSI2 oscillator start-up time - 0.7 - 3.5 ms
LSI2 oscillator power
IDD(LSI2)(2) - - 500 1180 nA
consumption
Allowed temperature change
∆Tmax(LSI2) - - 1.5 0.4 °C
during sleep duration(3)
1. Guaranteed by characterization results.
2. Guaranteed by design.
3. Includes accuracy of 32 Mhz crystal.

6.3.12 PLL characteristics

The parameters given in Table 61 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 22: General operating conditions.

Table 61. PLL, PLLSAI1 characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock(2) - 2.66 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1 2 - 64
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 2 2 - 16
Voltage scaling Range 1 8 - 64
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 2 8 - 16
MHz
Voltage scaling Range 1 8 - 64
fPLL_R_OUT PLL multiplier output clock R
Voltage scaling Range 2 8 - 16
Voltage scaling Range 1 96 - 344
fVCO_OUT PLL VCO output
Voltage scaling Range 2 64 - 128
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 64 MHz ps
RMS period jitter - 30 -
VCO freq = 96 MHz - 200 260
PLL power consumption
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
on VDD(1)
VCO freq = 344 MHz - 520 650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.

120/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.13 Flash memory characteristics

Table 62. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max Unit

tprog 64-bit programming time - 81.7 90.8 µs

One row (64 double word) Normal programming 5.2 5.5

tprog_row
programming time Fast programming 3.8 4.0

One page (4 KByte) Normal programming 41.8 43.0

tprog_page ms
programming time Fast programming 30.4 31.0
tERASE Page (4 KByte) erase time - 22.0 24.5
tME Mass erase time - 22.1 25.0
Write mode 3.4 -
Average consumption from VDD
Erase mode 3.4 -
IDD mA
Write mode 7 (for 6 µs) -
Maximum current (peak)
Erase mode 7 (for 67 µs) -
1. Guaranteed by design.

Table 63. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = –40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
1 kcycle(2) at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
(2)
10 kcycles at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
10 kcycles(2) at TA = 105 °C 10
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.

DS11929 Rev 5 121/178

159
Electrical characteristics STM32WB55xx

6.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 64. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs”, available on www.st.com.

Table 64. EMS characteristics

Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 64 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 64 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flow must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (e.g. control registers)

122/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, which specifies the test board and the pin loading.

Table 65. EMI characteristics

Peripheral ON
SMPS OFF or ON
Monitored
Symbol Parameter Conditions [fHSE / fCPUM4, fCPUM0] Unit
frequency band
32 MHz / 64 MHz, 32 MHz

0.1 MHz to 30 MHz 1

30 MHz to 130 MHz 4
VDD = 3.6 V, TA = 25 °C, dBµV
SEMI Peak level WLCSP100 package 130 MHz to 1 GHz -1
compliant with IEC 61967-2
1 GHz to 2 GHz 7
EMI level 1.5 -

6.3.15 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 66. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value(1) Unit

Electrostatic discharge voltage TA = +25 °C, conforming to

VESD(HBM) 2 2000
(human body model) ANSI/ESDA/JEDEC JS-001
V
Electrostatic discharge voltage TA = +25 °C, conforming to C2a(2) 500(2)
VESD(CDM)
(charge device model) ANSI/ESD STM5.3.1 JS-002 C1(3) 250(3)
1. Guaranteed by characterization results.
2. UFQFPN48, VFQPN68 and WLCSP100 packages.
3. UFBGA129 package.

DS11929 Rev 5 123/178

159
Electrical characteristics STM32WB55xx

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• a supply overvoltage is applied to each power supply pin
• a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 67. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II

6.3.16 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA / 0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 68.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.

Table 68. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on all pins except PB0, PB1 -5 N/A(2)

IINJ mA
Injected current on PB0, PB1 pins -5 0
1. Guaranteed by characterization results.
2. Injection not possible.

124/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.17 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under the conditions summarized in Table 22: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.

Table 69. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

I/O input
- - 0.3 x VDD
low level voltage(1)
VIL
I/O input
0.39 x VDD - 0.06
low level voltage(2)
V
I/O input
0.7 x VDD - -
high level voltage(1) 1.62 V < VDD < 3.6 V
VIH
I/O input
0.49 x VDD + 0.26 - -
high level voltage(2)
TT_xx, FT_xxx
Vhys and NRST I/O - 200 - mV
input hysteresis
0 ≤ VIN ≤ Max(VDDXXX)(3) - - ±100
Max(VDDXXX) ≤ VIN ≤
FT_xx - - 650
Max(VDDXXX) +1 V(2)(3)(4)
input leakage current
Max(VDDXXX) +1 V < VIN ≤
- - 200(7)
5.5 V(2)(3)(4)(5)(6)
0 ≤ VIN ≤ Max(VDDXXX)(3) - - ±150
Ilkg FT_lu, FT_u and Max(VDDXXX) ≤ VIN ≤ nA
- - 2500
PC3 IO Max(VDDXXX) +1 V(2)(3)
input leakage current
Max(VDDXXX) +1 V < VIN ≤
- - 250
5.5 V(1)(3)(4)(8)
VIN ≤ Max(VDDXXX)(3) - - ±150
TT_xx
input leakage current Max(VDDXXX) ≤ VIN < - - 2000
3.6 V(3)
Weak pull-up
RPU VIN = VSS 25 40 55
equivalent resistor(1)
kΩ
Weak pull-down
RPD VIN = VDD 25 40 55
equivalent resistor(1)
CIO I/O pin capacitance - - 5 - pF
1. Tested in production.
2. Guaranteed by design, not tested in production.
3. Represents the pad leakage of the I/O itself. The total product pad leakage is given by
ITotal_Ileak_max = 10 μA + number of I/Os where VIN is applied on the pad x Ilkg(Max).
4. Max(VDDXXX) is the maximum value among all the I/O supplies.
5. VIN must be lower than [Max(VDDXXX) + 3.6 V].
6. Refer to Figure 25: I/O input characteristics.

DS11929 Rev 5 125/178

159
Electrical characteristics STM32WB55xx

7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB, VLCD) + 0.3 V, the internal pull-up and pull-down resistors must
be disabled. All FT_xx IO except FT_lu, FT_u and PC3.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS, whose
contribution to the series resistance is minimal (~10%).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 25 .

Figure 25. I/O input characteristics

Vil-Vih (all IO except BOOT0)
3

2.5

TTL requirement Vih min = 2V

cmos vil spec 30%

cmos vih spec 70%
Voltage

1.5 ttl vil spec ttl

ttl vih spec ttl
datasheet Vil_rule
datasheet Vih_rule

TTL requirement Vil min = 0.8V

0.5

0
1.5 2 2.5 3 3.5

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2.
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 18: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 22: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT
unless otherwise specified).

126/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 70. Output voltage characteristics(1)

Symbol Parameter Conditions Min Max Unit

VOL(2) Output low level voltage for an I/O pin CMOS port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 0.4 -

VOL(2) Output low level voltage for an I/O pin TTL port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V 2.4 -

VOL(2) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 1.3 -
V
VOL(2) Output low level voltage for an I/O pin |IIO| = 4 mA - 0.4
VOH(2) Output high level voltage for an I/O pin VDD ≥ 1.62 V VDD - 0.45 -
|IIO| = 20 mA
- 0.4
VDD ≥ 2.7 V
Output low level voltage for an FT I/O |IIO| = 10 mA
VOLFM+(2) - 0.4
pin in FM+ mode (FT I/O with “f” option) VDD ≥ 1.62 V
|IIO| = 2 mA
- 0.4
1.62 V ≥ VDD ≥ 1.08 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 18: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports
and control pins) must always respect the absolute maximum ratings Σ IIO.
2. Guaranteed by design.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Table 71.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 22: General
operating conditions.

Table 71. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5

C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 1
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 1.5
00
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25
C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 52
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17
C=10 pF, 1.62 V ≤ VDD ≤ ≤2.7 V - 37

DS11929 Rev 5 127/178

159
Electrical characteristics STM32WB55xx

Table 71. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25

C=50 pF, 1.62 V ≤ VDD ≤ ≤2.7 V - 10
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 15
01
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 9
C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 16
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 9
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 25
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100(3)
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 37.5
10
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.8
C=50 pF, 1.62 V ≤ VDD ≤ 2.7 V - 11
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 5
C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120(3)
C=30 pF, 1.62 V ≤ VDD ≤ 2.7 V - 50
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 180(3)
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 75(3)
11
C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.3
C=30 pF, 1.62 V ≤ VDD ≤ 2.7 V - 6
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.7
C=10 pF, 1.62 V ≤ VDD ≤ 2.7 V - 3.3
1. The maximum frequency is defined with (Tr+ Tf) ≤ 2/3 T, and Duty cycle comprised between 45 and 55%.
2. The fall and rise time are defined, respectively, between 90 and 10%, and between 10 and 90% of the
output waveform.
3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

6.3.18 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 22: General operating conditions.

128/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 72. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

NRST input
VIL(NRST) - - - 0.3 x VDD
low level voltage
V
NRST input
VIH(NRST) - 0.7 x VDD - -
high level voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input
VF(NRST) - - - 70
filtered pulse
ns
NRST input
VNF(NRST) 1.71 V ≤ VDD ≤ 3.6 V 350 - -
not filtered pulse
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10%).

Figure 26. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 72, otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.

DS11929 Rev 5 129/178

159
Electrical characteristics STM32WB55xx

6.3.19 Analog switches booster

Table 73. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit

VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
Booster consumption for
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
Booster consumption for
- - 900
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.

130/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.20 Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Table 74 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 22: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 74. ADC characteristics(1) (2) (3)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6 V

Positive reference VDDA ≥ 2 V 2 - VDDA V

VREF+
voltage VDDA < 2 V VDDA V
Negative reference
VREF- - VSSA V
voltage
Range 1 - - 64
fADC ADC clock frequency MHz
Range 2 - - 16
Resolution = 12 bits - - 4.26

Sampling rate Resolution = 10 bits - - 4.92

for FAST channels Resolution = 8 bits - - 5.81
Resolution = 6 bits - - 7.11
fs Msps
Resolution = 12 bits - - 3.36

Sampling rate Resolution = 10 bits - - 4.00

for SLOW channels Resolution = 8 bits - - 4.57
Resolution = 6 bits - - 7.11
fADC = 64 MHz
External trigger - - 4.26 MHz
fTRIG Resolution = 12 bits
frequency
Resolution = 12 bits - - 15 1/fADC
(VREF++ (VREF++
(VREF++
VCMIN Input common mode Differential mode VREF-) / 2 VREF-) / 2 V
VREF-) / 2
- 0.18 + 0.18
Conversion voltage
VAIN (4) - 0 - VREF+ V
range(2)
External input
RAIN - - - 50 kΩ
impedance
Internal sample and hold
CADC - - 5 - pF
capacitor
Conversion
tSTAB Power-up time - 1
cycle
fADC = 64 MHz 1.8125 µs
tCAL Calibration time
- 116 1 / fADC

DS11929 Rev 5 131/178

159
Electrical characteristics STM32WB55xx

Table 74. ADC characteristics(1) (2) (3) (continued)

Symbol Parameter Conditions Min Typ Max Unit

CKMODE = 00 1.5 2 2.5

Trigger conversion
latency Regular and CKMODE = 01 - - 2.0
tLATR 1/fADC
injected channels CKMODE = 10 - - 2.25
without conversion abort
CKMODE = 11 - - 2.125
CKMODE = 00 2.5 3 3.5
Trigger conversion
latency Injected CKMODE = 01 - - 3.0
tLATRINJ 1/fADC
channels aborting a CKMODE = 10 - - 3.25
regular conversion
CKMODE = 11 - - 3.125
fADC = 64 MHz 0.039 - 10.0 µs
ts Sampling time
- 2.5 - 640.5 1/fADC
ADC voltage regulator
tADCVREG_STUP - - - 20 µs
start-up time
fADC = 64 MHz
0.234 - 1.019 µs
Total conversion time Resolution = 12 bits
tCONV
(including sampling time) ts + 12.5 cycles for successive
Resolution = 12 bits 1/fADC
approximations = 15 to 653
fs = 4.26 Msps - 730 830
ADC consumption from
IDDA(ADC) fs = 1 Msps - 160 220 µA
the VDDA supply
fs = 10 ksps - 16 50
fs = 4.26 Msps - 130 160
ADC consumption from
IDDV_S(ADC) the VREF+ single ended fs = 1 Msps - 30 40 µA
mode
fs = 10 ksps - 0.6 2
fs = 4.26 Msps - 250 310
ADC consumption from
IDDV_D(ADC) the VREF+ differential fs = 1 Msps - 60 70 µA
mode
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. SMPS in bypass mode.
4. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.

132/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 75. ADC sampling time(1)(2)

Fast channel Slow channel
Resolution RAIN
(bits) (kΩ) Minimum sampling Sampling Minimum sampling Sampling
time (ns) cycles time (ns) cycles

0 33 6.5 57 6.5
0.05 37 6.5 62 6.5
0.1 42 6.5 67 6.5
0.2 51 6.5 76 6.5
0.5 78 6.5 104 12.5
12 1 123 12.5 151 12.5
5 482 47.5 526 47.5
10 931 92.5 994 92.5
20 1830 247.5 1932 247.5
50 4527 640.5 4744 640.5
100 9021 640.5 9430 640.5
0 27 2.5 47 6.5
0.05 30 2.5 51 6.5
0.1 34 6.5 55 6.5
0.2 41 6.5 62 6.5
0.5 64 6.5 85 6.5
10 1 100 12.5 124 12.5
5 395 47.5 431 47.5
10 763 92.5 816 92.5
20 1500 247.5 1584 247.5
50 3709 640.5 3891 640.5
100 7391 640.5 7734 640.5
0 21 2.5 37 2.5
0.05 24 2.5 40 6.5
0.1 27 2.5 43 6.5
0.2 32 6.5 49 6.5
0.5 50 6.5 67 6.5
8 1 78 6.5 97 6.5
5 308 47.5 337 24.5
10 595 92.5 637 47.5
20 1169 247.5 1237 92.5
50 2891 247.5 3037 247.5
100 5762 640.5 6038 640.5

DS11929 Rev 5 133/178

159
Electrical characteristics STM32WB55xx

Table 75. ADC sampling time(1)(2) (continued)

Fast channel Slow channel
Resolution RAIN
(bits) (kΩ) Minimum sampling Sampling Minimum sampling Sampling
time (ns) cycles time (ns) cycles

0 15 2.5 26 2.5
0.05 17 2.5 28 2.5
0.1 19 2.5 31 2.5
0.2 23 2.5 35 2.5
0.5 36 6.5 48 6.5
6 1 56 6.5 69 6.5
5 221 24.5 242 24.5
10 427 47.5 458 47.5
20 839 92.5 890 92.5
50 2074 247.5 2184 247.5
100 4133 640.5 4342 640.5
1. Guaranteed by design.
2. VDD = 1.62 V, Cpcb = 4.7 pF, 125 °C, booster enabled.

134/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 76. ADC accuracy - Limited test conditions 1(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Single Fast channel (max speed) - 4 5

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 3.5 4.5
Differential
Slow channel (max speed) - 3.5 4.5

Single Fast channel (max speed) - 1 2.5

ended Slow channel (max speed) - 1 2.5
EO Offset error
Fast channel (max speed) - 1.5 2.5
Differential
Slow channel (max speed) - 1.5 2.5

Single Fast channel (max speed) - 2.5 4.5

ended Slow channel (max speed) - 2.5 4.5
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential
Slow channel (max speed) - 2.5 3.5
Fast channel (max speed) - 1 1.5
ADC clock frequency ≤ 64 MHz,

Single
Sampling rate ≤ 4.26 Msps,

Differential ended Slow channel (max speed) - 1 1.5

VDDA = VREF+ = 3 V,

ED linearity
error Fast channel (max speed) - 1 1.2
Differential
TA = 25 °C

Slow channel (max speed) - 1 1.2

Single Fast channel (max speed) - 1.5 2.5

Integral ended Slow channel (max speed) - 1.5 2.5
EL linearity
error Fast channel (max speed) - 1 2
Differential
Slow channel (max speed) - 1 2

Single Fast channel (max speed) 10.4 10.5 -

Effective ended Slow channel (max speed) 10.4 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.8 10.9 -
Differential
Slow channel (max speed) 10.8 10.9 -

DS11929 Rev 5 135/178

159
Electrical characteristics STM32WB55xx

Table 76. ADC accuracy - Limited test conditions 1(1)(2)(3) (continued)

Symbol Parameter Conditions(4) Min Typ Max Unit

ADC clock frequency ≤ 64 MHz,

Fast channel (max speed) - -74 -73

Sampling rate ≤ 4.26 Msps,

Single

VDDA = VREF+ = 3 V,
ended
Slow channel (max speed) - -74 -73

TA = 25 °C
Total
THD harmonic dB
distortion Fast channel (max speed) - -79 -76

Differential
Slow channel (max speed) - -79 -76

1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.

136/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 77. ADC accuracy - Limited test conditions 2(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Single Fast channel (max speed) - 4 6.5

Total ended Slow channel (max speed) - 4 6.5
ET unadjusted
error Fast channel (max speed) - 3.5 5.5
Differential
Slow channel (max speed) - 3.5 5.5

Single Fast channel (max speed) - 1 4.5

ended Slow channel (max speed) - 1 5
EO Offset error
Fast channel (max speed) - 1.5 3
Differential
Slow channel (max speed) - 1.5 3

Single Fast channel (max speed) - 2.5 6

ended Slow channel (max speed) - 2.5 6
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential
Slow channel (max speed) - 2.5 3.5
Fast channel (max speed) - 1 1.5
ADC clock frequency ≤ 64 MHz,

Single
Sampling rate ≤ 4.26 Msps,

Differential ended Slow channel (max speed) - 1 1.5

ED linearity
error Fast channel (max speed) - 1 1.2
Differential
VDDA ≥ 2 V
TA = 25 °C

Slow channel (max speed) - 1 1.2

Single Fast channel (max speed) - 1.5 3.5

Integral ended Slow channel (max speed) - 1.5 3.5
EL linearity
error Fast channel (max speed) - 1 3
Differential
Slow channel (max speed) - 1 2.5

Single Fast channel (max speed) 10 10.5 -

Effective ended Slow channel (max speed) 10 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.7 10.9 -
Differential
Slow channel (max speed) 10.7 10.9 -

DS11929 Rev 5 137/178

159
Electrical characteristics STM32WB55xx

Table 77. ADC accuracy - Limited test conditions 2(1)(2)(3) (continued)

Symbol Parameter Conditions(4) Min Typ Max Unit

ADC clock frequency ≤ 64 MHz,

Fast channel (max speed) - -74 -65

Sampling rate ≤ 4.26 Msps,

Single
ended
Slow channel (max speed) - -74 -67

VDDA ≥ 2 V
TA = 25 °C
Total
THD harmonic dB
distortion Fast channel (max speed) - -79 -70

Differential
Slow channel (max speed) - -79 -71

138/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 78. ADC accuracy - Limited test conditions 3(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Single Fast channel (max speed) - 5.5 7.5

Total ended Slow channel (max speed) - 4.5 6.5
ET unadjusted
error Fast channel (max speed) - 4.5 7.5
Differential
Slow channel (max speed) - 4.5 5.5

Single Fast channel (max speed) - 2 5

ended Slow channel (max speed) - 2.5 5
EO Offset error
Fast channel (max speed) - 2 3.5
Differential
Slow channel (max speed) - 2.5 3

Single Fast channel (max speed) - 4.5 7

ended Slow channel (max speed) - 3.5 6
EG Gain error LSB
Fast channel (max speed) - 3.5 4
Differential
Slow channel (max speed) - 3.5 5
Fast channel (max speed) - 1.2 1.5
ADC clock frequency ≤ 64 MHz,

1.65 V ≤ VDDA = VREF+ ≤ 3.6 V,

Single
Sampling rate ≤ 4.26 Msps,

Differential ended
Voltage scaling Range 1

Slow channel (max speed) - 1.2 1.5

ED linearity
error Fast channel (max speed) - 1 1.2
Differential
Slow channel (max speed) - 1 1.2

Single Fast channel (max speed) - 3 3.5

Integral ended Slow channel (max speed) - 2.5 3.5
EL linearity
error Fast channel (max speed) - 2 2.5
Differential
Slow channel (max speed) - 2 2.5

Single Fast channel (max speed) 10 10.4 -

Effective ended Slow channel (max speed) 10 10.4 -
ENOB number of bits
bits Fast channel (max speed) 10.6 10.7 -
Differential
Slow channel (max speed) 10.6 10.7 -

DS11929 Rev 5 139/178

159
Electrical characteristics STM32WB55xx

Table 78. ADC accuracy - Limited test conditions 3(1)(2)(3) (continued)

Symbol Parameter Conditions(4) Min Typ Max Unit

ADC clock frequency ≤ 64 MHz,

1.65 V ≤ VDDA = VREF+ ≤ 3.6 V,

Fast channel (max speed) - -69 -67

Sampling rate ≤ 4.26 Msps,

Voltage scaling Range 1

Single
ended
Slow channel (max speed) - -71 -67
Total
THD harmonic dB
distortion Fast channel (max speed) - -72 -71

Differential
Slow channel (max speed) - -72 -71

140/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 79. ADC accuracy - Limited test conditions 4(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Single Fast channel (max speed) - 5 5.4

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 4 5
Differential
Slow channel (max speed) - 3.5 4.5

Single Fast channel (max speed) - 2 4

ended Slow channel (max speed) - 2 4
EO Offset error
Fast channel (max speed) - 2 3.5
Differential
Slow channel (max speed) - 2 3.5

Single
Differential ended
Voltage scaling Range 2

Slow channel (max speed) - 1 1.5

ED linearity
error Fast channel (max speed) - 1 1.2
Differential
Slow channel (max speed) - 1 1.2

Single Fast channel (max speed) - 2.5 3

Integral ended Slow channel (max speed) - 2.5 3
EL linearity
error Fast channel (max speed) - 2 2.5
Differential
Slow channel (max speed) - 2 2.5

Single Fast channel (max speed) 10.2 10.5 -

Effective ended Slow channel (max speed) 10.2 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.6 10.7 -
Differential
Slow channel (max speed) 10.6 10.7 -

DS11929 Rev 5 141/178

159
Electrical characteristics STM32WB55xx

Table 79. ADC accuracy - Limited test conditions 4(1)(2)(3) (continued)

Symbol Parameter Conditions(4) Min Typ Max Unit

1.65 V ≤ VDDA = VREF+ ≤ 3.6 V,

ADC clock frequency ≤ 16 MHz,
Fast channel (max speed) - -71 -69

Voltage scaling Range 2

Single
ended
Slow channel (max speed) - -71 -69
Total
THD harmonic dB
distortion Fast channel (max speed) - -73 -72

Differential
Slow channel (max speed) - -73 -72

Figure 27. ADC accuracy characteristics

VSSA EG (1) Example of an actual transfer curve

4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET EO = offset error: maximum deviation
(3)
7 between the first actual transition and
(1)
6 the first ideal one.
EG = gain error: deviation between the last
5
EO EL
ideal transition and the last actual one.
4 ED = differential linearity error: maximum
3 deviation between actual steps and the ideal ones.
ED
EL = integral linearity error: maximum deviation
2
between any actual transition and the end point
1 LSB IDEAL
1 correlation line.

0
1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA

MS19880V2

142/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Figure 28. Typical connection diagram using the ADC

VDDA

VT Sample and hold ADC converter

RAIN(1) AINx RADC

12-bit
converter
Cparasitic(2) VT Ilkg (3) CADC
VAIN

MS33900V5

1. Refer to Table 74: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 69: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 69: I/O static characteristics for the values of Ilkg.

General PCB design guidelines

Power supply decoupling has to be performed as shown in Figure 14: Power supply scheme
(all packages except BGA129). The 10 nF capacitor needs to be ceramic (good quality),
placed as close as possible to the chip.

6.3.21 Voltage reference buffer characteristics

Table 80. VREFBUF characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VRS = 0 2.4 - 3.6

Normal mode
Analog supply VRS = 1 2.8 - 3.6
VDDA
voltage VRS = 0 1.65 - 2.4
Degraded mode(2)
VRS = 1 1.65 - 2.8
V
VRS = 0 2.046(3) 2.048 2.049(3)
Normal mode
VREFBUF_ Voltage VRS = 1 2.498(3) 2.5 2.502(3)
OUT reference output VRS = 0 VDDA-150 mV - VDDA
Degraded mode(2)
VRS = 1 VDDA-150 mV - VDDA
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution
CL Load capacitor - - 0.5 1 1.5 µF
Equivalent
esr series resistor - - - - 2 Ω
of Cload
Static load
Iload - - - - 4 mA
current

DS11929 Rev 5 143/178

159
Electrical characteristics STM32WB55xx

Table 80. VREFBUF characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Iload = 500 µA - 200 1000

Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 500
Iload_reg Load regulation 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA
Tcoeff_
-40 °C < TJ < +125 °C - - +
vrefint
Temperature 50
TCoeff ppm/ °C
coefficient Tcoeff_
0 °C < TJ < +50 °C - - vrefint +
50

Power supply DC 40 60 -
PSRR dB
rejection 100 kHz 25 40 -
CL = 0.5 µF(4) - 300 350
tSTART Start-up time CL = 1.1 µF(4) - 500 650 µs
CL = 1.5 µF(4) - 650 800
Control of
maximum DC
current drive on
IINRUSH - - - 8 - mA
VREFBUF_OUT
during start-up
phase (5)
Iload = 0 µA - 16 25
VREFBUF
IDDA
consumption Iload = 500 µA - 18 30 µA
(VREFBUF)
from VDDA
Iload = 4 mA - 35 50
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer cannot maintain accurately the output voltage that will follow (VDDA - drop
voltage).
3. Guaranteed by test in production.
4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
5. To correctly control the VREFBUF in-rush current during start-up phase and scaling change, the VDDA voltage must be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.

144/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.22 Comparator characteristics

Table 81. COMP characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 1.62 - 3.6

Comparator
VIN - 0 - VDDA V
input voltage range
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV

Scaler static consumption BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER)
from VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs

High-speed VDDA ≥ 2.7 V - - 5

mode VDDA < 2.7 V - - 7
Comparator startup time
tSTART to reach propagation VDDA ≥ 2.7 V - - 15 µs
delay specification Medium mode
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 40

High-speed VDDA ≥ 2.7 V - 55 80

ns
mode VDDA < 2.7 V - 55 100
(3) Propagation delay with
tD
100 mV overdrive Medium mode - 0.55 0.9
µs
Ultra-low-power mode - 4 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
No hysteresis - 0 -
Low hysteresis - 8 -
Vhys Comparator hysteresis mV
Medium hysteresis - 15 -
High hysteresis - 27 -
Static - 400 600
Ultra-low-
With 50 kHz ±100 mV nA
power mode - 1200 -
overdrive square signal
Static - 5 7
Comparator consumption Medium
IDDA(COMP) With 50 kHz ±100 mV
from VDDA mode - 6 -
overdrive square signal
µA
Static - 70 100
High-speed
mode With 50 kHz ±100 mV
- 75 -
overdrive square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 34: Embedded internal voltage reference.
3. Guaranteed by characterization results.

DS11929 Rev 5 145/178

159
Electrical characteristics STM32WB55xx

6.3.23 Temperature sensor characteristics

Table 82. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C

(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV / °C
V30 Voltage at 30 °C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
Sensor buffer start-up time in continuous mode(4) - 8 15 µs
(TS_BUF)(1)

tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs

tS_temp(1) ADC sampling time when reading the temperature 5 - - µs

Temperature sensor consumption from VDD, when

IDD(TS)(1) - 4.7 7 µA
selected by ADC
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 11:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.24 VBAT monitoring characteristics

Table 83. VBAT monitoring characteristics

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 39 - kΩ

Q Ratio on VBAT measurement - 3 - -
(1)
Er Error on Q -10 - 10 %
tS_vbat(1) ADC sampling time when reading the VBAT 12 - - µs
1. Guaranteed by design.

Table 84. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

Battery VBRS = 0 - 5 -
RBC charging kΩ
resistor VBRS = 1 - 1.5 -

146/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

6.3.25 SMPS step-down converter characteristics

The SMPS step-down converter characteristic are given at 4 MHz clock, with a 20 mA load
(unless otherwise specified), using a 10 µH inductor and a 4.7 µF capacitor.

6.3.26 LCD controller characteristics

The devices embed a built-in step-up converter to provide a constant LCD reference voltage
independently from the VDD voltage. An external capacitor Cext must be connected to the
VLCD pin to decouple this converter.
Table 85. LCD controller characteristics(1)
Symbol Parameter Conditions Min Typ Max Unit

VLCD LCD external voltage - - 3.6

VLCD0 LCD internal reference voltage 0 - 2.62 -
VLCD1 LCD internal reference voltage 1 - 2.76 -
VLCD2 LCD internal reference voltage 2 - 2.89 -
VLCD3 LCD internal reference voltage 3 - 3.04 - V
VLCD4 LCD internal reference voltage 4 - 3.19 -
VLCD5 LCD internal reference voltage 5 - 3.32 -
VLCD6 LCD internal reference voltage 6 - 3.46 -
VLCD7 LCD internal reference voltage 7 - 3.62 -
Buffer OFF
0.2 - 2
(BUFEN=0 is LCD_CR register)
Cext VLCD external capacitance μF
Buffer ON
1 - 2
(BUFEN=1 is LCD_CR register)
Supply current from VDD at Buffer OFF
- 3 -
VDD = 2.2 V (BUFEN=0 is LCD_CR register)
ILCD(2) μA
Supply current from VDD at Buffer OFF
- 1.5 -
VDD = 3.0 V (BUFEN=0 is LCD_CR register)
Buffer OFF
- 0.5 -
(BUFFEN = 0, PON = 0)
Buffer ON
- 0.6 -
Supply current from VLCD (BUFFEN = 1, 1/2 Bias)
IVLCD μA
(VLCD = 3 V) Buffer ON
- 0.8 -
(BUFFEN = 1, 1/3 Bias)
Buffer ON
- 1 -
(BUFFEN = 1, 1/4 Bias)
RHN Total High resistor value for Low drive resistive network - 5.5 - MΩ
RLN Total Low resistor value for High drive resistive network - 240 - kΩ

DS11929 Rev 5 147/178

159
Electrical characteristics STM32WB55xx

Table 85. LCD controller characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

V44 Segment/Common highest level voltage - VLCD -

V34 Segment/Common 3/4 level voltage - 3/4 VLCD -
V23 Segment/Common 2/3 level voltage - 2/3 VLCD -
V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V
V13 Segment/Common 1/3 level voltage - 1/3 VLCD -
V14 Segment/Common 1/4 level voltage - 1/4 VLCD -
V0 Segment/Common lowest level voltage - 0 -
1. Guaranteed by design.
2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio = 64, all pixels active, no LCD connected.

6.3.27 Timer characteristics

The parameters given in the following tables are guaranteed by design. Refer to
Section 6.3.17 for details on the input/output alternate function characteristics (output
compare, input capture, external clock, PWM output).

Table 86. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 64 MHz 15.625 - ns

Timer external clock frequency - 0 fTIMxCLK/2

fEXT MHz
on CH1 to CH4 fTIMxCLK = 64 MHz 0 40
TIM1, TIM16, TIM17 - 16
ResTIM Timer resolution bit
TIM2 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 64 MHz 0.015625 1024 µs

Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 64 MHz - 67.10 s
1. TIMx, is used as a general term where x stands for 1, 2, 16 or 17.

148/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 87. IWDG min/max timeout period at 32 kHz (LSI1)(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC
period of uncertainty.

6.3.28 Clock recovery system (CRS)

The devices embed a special block for the automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range.
This automatic trimming is based on the external synchronization signal, which can be
derived from USB Sart Of Frame (SOF) signalization, from LSE oscillator, from an external
signal on CRS_SYNC pin or generated by user software.
For faster lock-in during startup it is also possible to combine automatic trimming with
manual trimming action.

6.3.29 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.

Table 88. Minimum I2CCLK frequency in all I2C modes

Symbol Parameter Condition Min Unit

Standard-mode - 2
Analog filter ON, DNF = 0 9
I2CCLK Fast-mode
f(I2CCLK) Analog filter OFF, DNF = 1 9 MHz
frequency
Analog filter ON, DNF = 0 19
Fast-mode Plus
Analog filter OFF, DNF = 1 16

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual RM0434).

DS11929 Rev 5 149/178

159
Electrical characteristics STM32WB55xx

The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL
I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive
requirement in Fast-mode Plus is supported partially.
This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up. Refer to Section 6.3.17 for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 89 for its characteristics.

Table 89. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that

tAF 50(2) 110(3) ns
are suppressed by the analog filter
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered

SPI characteristics
Unless otherwise specified, the parameters given in Table 90 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 22: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.17 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).

150/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 90. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode
1.65 < VDD < 3.6 V 32
Voltage Range 1
Master transmitter mode
1.65 < VDD < 3.6 V 32
Voltage Range 1
Slave receiver mode
fSCK 1.65 < VDD < 3.6 V 32
SPI clock frequency Voltage Range 1 - - MHz
1/tc(SCK)
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V 32(2)
Voltage Range 1
Slave mode transmitter/full duplex
1.65 < VDD < 3.6 V 20.5(2)
Voltage Range 1
Voltage Range 2 8
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4xTPCLK - -
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2xTPCLK - -
-
tw(SCKH)
SCK high and low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1
tw(SCKL)
tsu(MI) Master mode 1.5 - -
Data input setup time
tsu(SI) Slave mode 1 - -
th(MI) Master mode 5 - -
Data input hold time ns
th(SI) Slave mode 1 - -
ta(SO) Data output access time 9 - 34
Slave mode
tdis(SO) Data output disable time 9 - 16
Slave mode 2.7 < VDD < 3.6 V
- 14.5 15.5
Voltage Range 1
Slave mode 1.65 < VDD < 3.6 V
tv(SO) - 15.5 24
Data output valid time Voltage Range 1
Slave mode 1.65 < VDD < 3.6 V ns
- 19.5 26
Voltage Range 2
tv(MO) Master mode (after enable edge) - 2.5 3
th(SO) Slave mode (after enable edge) 8 - -
Data output hold time
th(MO) Master mode (after enable edge) 1 - -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.

DS11929 Rev 5 151/178

159
Electrical characteristics STM32WB55xx

Figure 29. SPI timing diagram - slave mode and CPHA = 0

Figure 30. SPI timing diagram - slave mode and CPHA = 1

NSS input

tSU(NSS) tc(SCK) th(NSS)

SCK input

CPHA=1
CPOL=0 tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tr(SCK)
tv(SO) th(SO) tdis(SO)
ta(SO) tf(SCK)
MISO
MSB OUT BIT6 OUT LSB OUT
OUTPUT
tsu(SI) th(SI)
MOSI
INPUT MSB IN BIT 1 IN LSB IN

ai14135b

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

152/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Figure 31. SPI timing diagram - master mode

High

NSS input

tc(SCK)
SCK Output

CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN

th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

DS11929 Rev 5 153/178

159
Electrical characteristics STM32WB55xx

Quad-SPI characteristics
Unless otherwise specified, the parameters given in Table 91 and Table 92 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 22: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 15 or 20 pF
• Measurement points are set at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.17 for more details on the input/output alternate function
characteristics.

Table 91. Quad-SPI characteristics in SDR mode(1)

Symbol Parameter Conditions Min Typ Max Unit

1.65 < VDD< 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
1.65 < VDD< 3.6 V, CLOAD = 15 pF
- - 48
FCK Quad-SPI Voltage Range 1
MHz
1/t(CK) clock frequency 2.7 < VDD< 3.6 V, CLOAD = 15 pF
- - 60
Voltage Range 1
1.65 < VDD < 3.6 V CLOAD = 20 pF
- - 16
Voltage Range 2
tw(CKH) Quad-SPI clock t(CK)/2 - 0.5 - t(CK)/2 + 1
fAHBCLK= 48 MHz, presc=1
tw(CKL) high and low time t(CK)/2 - 1 - t(CK)/2 + 0.5
Voltage Range 1 2 - -
ts(IN) Data input setup time
Voltage Range 2 3.5 - -
Voltage Range 1 4.5 - -
th(IN) Data input hold time ns
Voltage Range 2 6 - -
Voltage Range 1 - 1 1.5
tv(OUT) Data output valid time
Voltage Range 2 - 1 1.5
Voltage Range 1 0 - -
th(OUT) Data output hold time
Voltage Range 2 0 - -
1. Guaranteed by characterization results.

154/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 92. Quad-SPI characteristics in DDR mode(1)

Symbol Parameter Conditions Min Typ Max Unit

1.65 < VDD < 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
2.0 < VDD < 3.6 V, CLOAD = 20 pF
- - 50
FCK Quad-SPI clock Voltage Range 1
MHz
1/t(CK) frequency 1.65 < VDD < 3.6 V, CLOAD = 15 pF
- - 48
Voltage Range 1
1.65 < VDD < 3.6 V CLOAD = 20 pF
- - 16
Voltage Range 2
tw(CKH) Quad-SPI clock t(CK)/2 - t(CK)/2 + 1
fAHBCLK = 48 MHz, presc=0
t high and low time t(CK)/2 - 1 - t(CK)/2
w(CKL)

Data input setup Voltage Range 1 2.5

tsr(IN) - -
time on rising edge Voltage Range 2 3.5

Data input setup Voltage Range 1 2.5

tsf(IN) - -
time on falling edge Voltage Range 2 1.5

Data input hold Voltage Range 1 5.5

thr(IN) - -
time on rising edge Voltage Range 2 6.5

Data input hold Voltage Range 1 5

thf(IN) - -
time on falling edge Voltage Range 2 6
DHHC=0 4 5.5
Data output valid Voltage Range 1 ns
tvr(OUT) DHHC=1 - t(CK)/2 + 1 t(CK)/2 + 1.5
time on rising edge
Voltage Range 2 4.5 7
DHHC=0 4 6
Data output valid Voltage Range 1
tvf(OUT) DHHC=1 - t(CK)/2 + 1 t(CK)/2 + 2
time on falling edge
Voltage Range 2 6 7.5
DHHC=0 2 - -
Data output hold Voltage Range 1
thr(OUT) DHHC=1 t(CK)/2 + 0.5 - -
time on rising edge
Voltage Range 2 3.5 - -
DHHC=0 3 - -
Data output hold Voltage Range 1
thf(OUT) DHHC=1 t(CK)/2 + 0.5 - -
time on falling edge
Voltage Range 2 5 - -
1. Guaranteed by characterization results.

DS11929 Rev 5 155/178

159
Electrical characteristics STM32WB55xx

Figure 32. Quad-SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)

Clock
tv(OUT) th(OUT)

Data output D0 D1 D2

ts(IN) th(IN)

Data input D0 D1 D2
MSv36878V1

Figure 33. Quad-SPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)

Data output IO0 IO1 IO2 IO3 IO4 IO5

tsf(IN) thf(IN) tsr(IN) thr(IN)

Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3

SAI characteristics

Unless otherwise specified, the parameters given in Table 93 for SAI are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized inTable 22: General operating conditions, with
the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement are performed at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.17 for more details on the input/output alternate function
characteristics (CK,SD,FS).

156/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

Table 93. SAI characteristics(1)

Symbol Parameter Conditions Min Max Unit

fMCLK SAI main clock output - - 50

Master transmitter
2.7 V ≤ VDD ≤ 3.6 V - 23.5
Voltage Range 1
Master transmitter
1.65 V ≤ VDD ≤ 3.6 V - 16
Voltage Range 1
Master receiver
- 16
Voltage Range 1
MHz
fCK SAI clock frequency(2) Slave transmitter
2.7 V ≤ VDD ≤ 3.6 V - 26
Voltage Range 1
Slave transmitter
1.65 V ≤ VDD ≤ 3.6 V - 20
Voltage Range 1
Slave receiver
- 32
Voltage Range 1
Voltage Range 2 - 8
Master mode
- 21
2.7 V ≤ VDD ≤ 3.6 V
tv(FS) FS valid time
Master mode
- 30
1.65 V ≤ VDD ≤ 3.6 V
th(FS) FS hold time Master mode 10 -
tsu(FS) FS setup time Slave mode 1.5 -
th(FS) FS hold time Slave mode 2.5 -
tsu(SD_A_MR) Master receiver 1 -
Data input setup time
tsu(SD_B_SR) Slave receiver 1.5 -
th(SD_A_MR) Master receiver 6.5 -
Data input hold time ns
th(SD_B_SR) Slave receiver 2.5 -
Slave transmitter (after enable edge)
- 19
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
- 25
1.65 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 -
Master transmitter (after enable edge)
- 18.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 25
1.65 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 -
1. Guaranteed by characterization results.
2. APB clock frequency must be at least twice SAI clock frequency.

DS11929 Rev 5 157/178

159
Electrical characteristics STM32WB55xx

Figure 34. SAI master timing waveforms

1/fSCK

SAI_SCK_X
th(FS)

SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)

SAI_SD_X Slot n
(receive)
MS32771V1

Figure 35. SAI slave timing waveforms

1/fSCK

SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)

SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)

SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)

SAI_SD_X Slot n
(receive)
MS32772V1

158/178 DS11929 Rev 5

STM32WB55xx Electrical characteristics

USB characteristics
The STM32WB55xx USB interface is fully compliant with the USB specification version 2.0,
and is USB-IF certified (for Full-speed device operation).

Table 94. USB electrical characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDDUSB (2)
USB transceiver operating voltage - 3.0 - 3.6 V
USB crystal-less
Tcrystal_less - -15 - 85 °C
operation temperature
Embedded USB_DP pull-up value
RPUI - 900 1250 1600
during idle
Embedded USB_DP pull-up value Ω
RPUR - 1400 2300 3200
during reception
ZDRV(3) Output driver impedance(4) Driving high and low 28 36 44
1. TA = -40 to 125 °C unless otherwise specified.
2. The STM32WB55xx USB functionality is ensured down to 2.7 V, but the full USB electrical characteristics
are degraded in the 2.7 to 3.0 V voltage range.
3. Guaranteed by design.
4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.

DS11929 Rev 5 159/178

159
Package information STM32WB55xx

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 UFBGA129 package information

Figure 36. UFBGA - 129 balls, 7 x 7 mm, 0.5 mm fine pitch, square ball grid array
package outline
SEATING

C
PLANE

A1 corner index area A4

B A2
A B C D E F G H I J K L M
b
1
e
2
3
4
5
6
7 E1 E
8
9
10
11
b (129 balls) 12
eee M C A B 13

fff M C F
e F
A1

D1 A
D
A

ddd C
BOTTOM VIEW
B09R_UFBGA129_ME_V1

1. Drawing is not to scale.

2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metalized markings, or other feature of package body or integral heat slug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.

Table 95. UFBGA129 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A(2) - - 0.60 - - 0.024

A1 - - 0.11 - - 0.004
A2 - 0.13 - - 0.005 -
A4 - 0.32 - - 0.013 -
b(3) 0.24 0.29 0.34 0.009 0.011 0.013

160/178 DS11929 Rev 5

STM32WB55xx Package information

Table 95. UFBGA129 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

D 6.85 7.00 7.15 0.270 0.276 0.281

E 6.85 7.00 7.15 0.270 0.276 0.281
D1 - 6.00 - - 0.236 -
E1 - 6.00 - - 0.236 -
e - 0.50 - - 0.020 -
F - 0.50 - - 0.020 -
ddd - - 0.08 - - 0.003
(4)
eee - - 0.15 - - 0.006
fff(5) - - 0.05 - - 0.002
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. - UFBGA stands for Ultra Thin Profile Fine Pitch Ball Grid Array.
- Ultra thin profile: 0.50 < A ≤ 0.65mm / Fine pitch: e < 1.00mm pitch.
- The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1²+A2²+A4² tolerance values).
3. The typical balls diameters before mounting is 0.20 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datum A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.

Figure 37. UFBGA129 recommended footprint

Dpad

Dsm
BGA_WLCSP_FT_V1

DS11929 Rev 5 161/178

172
Package information STM32WB55xx

Table 96. UFBGA129 recommended PCB design rules

Dimension Recommended values

Pitch 0.5 mm
Dpad 0,360 mm
Dsm 0.460 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.360 mm
Stencil thickness 0.100 mm

7.2 WLCSP100 package information

Figure 38. WLCSP - 100 balls, 4.390 x 4.371 mm, 0.4 mm pitch, wafer level chip scale
package outline

e1
F A1 BALL LOCATION A1
10 1
G
A

DETAIL A
e4

e2 E E

K
K

e e3 H
D A
D
BOTTOM VIEW TOP VIEW A2
A3 A2 SIDE VIEW

BUMP

FRONT VIEW A1

SEATING PLANE
DETAIL A
ROTATED 90
A08S_WLCSP100_ME_V1

162/178 DS11929 Rev 5

STM32WB55xx Package information

Table 97. WLCSP100 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 0.59 - - 0.023
A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
(2)
A3 - 0.025 - - 0.001 -
b 0.22 0.25 0.28 0.009 0.010 0.0110
D 4.38 4.40 4.42 0.1715 0.1728 0.1742
E 4.36 4.38 4.40 0.1707 0.1721 0.1735
e - 0.40 - - 0.0157 -
e1 - 3.60 - - 0.1417 -
e2 - 3.60 - - 0.1417 -
e3 - 0.08 - - 0.0031 -
e4 - 0.08 - - 0.0033 -
(3)
F - 0.480 - - 0.0187 -
(3)
G - 0.306 - - 0.0119 -
H - 0.32 - - 0.0124 -
K - 0.47 - - 0.0185 -
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
ccc - - 0.10 - - 0.0039
ddd - - 0.05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to the 3rd decimal place.
2. Nominal dimension rounded to the 3rd decimal place results from process capability.
3. Calculated dimensions are rounded to 3rd decimal place.

DS11929 Rev 5 163/178

172
Package information STM32WB55xx

Figure 39. WLCSP100 recommended footprint

Dpad
Dsm

A08S_WLCSP100_FP_V1

1. Dimensions are expressed in millimeters.

Table 98. WLCSP100 recommended PCB design rules

Dimension Recommended values

Pitch 0.4 mm
Dpad 0.225 mm
Dsm 0.290 mm typ. (depends on the soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm

164/178 DS11929 Rev 5

STM32WB55xx Package information

7.3 VFQFPN68 package information

Figure 40. VFQFPN68, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat
package outline
PIN 1 IDENTIFIER
LASER MARKING ddd C
D
A
A1
68 67 A2
1
2

E E

(2X) 0.10 C
SEATING
C PLANE

TOP VIEW SIDE VIEW

L
D2

2
1

PIN 1 ID
C 0.30 X 45'
68 67 b
e
EXPOSED PAD AREA
BOTTOM VIEW B029_VFQFPN68_ME_V1

1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed
version. Very thin profile: 0.80 < A ≤ 1.00 mm.
2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other
feature of package body. Exact shape and size of this feature is optional.

Table 99. VFQFPN68 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 0.02 0.05 0 0.0008 0.0020
A3 - 0.20 - - 0.0008 -
b 0.15 0.20 0.25 0.0059 0.0079 0.0098
D 7.85 8.00 8.15 0.3091 0.3150 0.3209
D2 6.30 6.40 6.50 0.2480 0.2520 0.2559

DS11929 Rev 5 165/178

172
Package information STM32WB55xx

Table 99. VFQFPN68 mechanical data (continued)

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

E 7.85 8.00 8.15 0.3091 0.3150 0.3209

E2 6.30 6.40 6.50 0.2480 0.2520 0.2559
e - 0.40 - - 0.0157 -
L 0.40 0.50 0.60 0.0157 0.0197 0.0236
ddd - - 0.08 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 41. VFQFPN68 recommended footprint

8.30
7.00
6.65

0.15 6.40

6.65
7.00
8.30
6.40

0.25

0.82
0.65
0.40
B029_VFQFPN68_FP_V2

1. Dimensions are expressed in millimeters.

166/178 DS11929 Rev 5

STM32WB55xx Package information

7.4 UFQFPN48 package information

Figure 42. UFQFPN48 - 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
Pin 1 identifier
laser marking area
D

A
E E
T Seating
plane
ddd A1
e b

Detail Y
D
Y

Exposed pad
area D2
1

L
48
C 0.500x45°
pin1 corner R 0.125 typ.

E2 Detail Z

48
Z
A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package, it must be electrically connected to
the PCB ground.

DS11929 Rev 5 167/178

172
Package information STM32WB55xx

Table 100. UFQFPN48 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 43. UFQFPN48 recommended footprint

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80
A0B9_FP_V2

1. Dimensions are expressed in millimeters.

168/178 DS11929 Rev 5

STM32WB55xx Package information

Device marking for UFQFPN48

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.

Figure 44. UFQFPN48 marking example (package top view)

Product STM32WB55
identification(1) CGU6

Date code
Y WW

Pin 1 identifier B
Revision code

MS51581V1

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.

DS11929 Rev 5 169/178

172
Package information STM32WB55xx

7.5 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 22: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the equation:
TJ max = TA max + (PD max x ΘJA)
where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max),
• PINT max is the product of IDD and VDD, expressed in Watt. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
• PI/O max = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Note: When the SMPS is used, a portion of the power consumption is dissipated into the external
inductor, therefore reducing the chip power dissipation. This portion depends mainly on the
inductor ESR characteristics.
Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the
chip power consumption.
Note: RF characteristics (such as sensitivity, Tx power, consumption) are provided up to 85 °C.

Table 101. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

51.0
UFQFPN48 - 7 mm x 7 mm
Thermal resistance junction-ambient
47.0
VFQFPN68 - 8 mm x 8 mm
ΘJA °C/W
Thermal resistance junction-ambient
44.0
WLCSP100 - 0.4 mm pitch
Thermal resistance junction-ambient
58.4
BGA129 - 0.5 mm pitch

7.5.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

7.5.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8.

170/178 DS11929 Rev 5

STM32WB55xx Package information

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32WB55xx at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.

Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL = 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V = 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 101 TJmax is calculated as follows:
– For VFQFPN68, 47 °C/W
TJmax = 82 °C + (47 °C/W × 447 mW) = 82 °C + 21 °C = 103 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C), see Section 8.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8).
Note: With this given PDmax user can find the TAmax allowed for a given device temperature range
(order code suffix 7).
Suffix 7: TAmax = TJmax - (47°C/W × 447 mW) = 125°C -21°C = 104 °C

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW

DS11929 Rev 5 171/178

172
Package information STM32WB55xx

Using the values obtained in Table 101 TJmax is calculated as follows:

– For UFQFPN48, 51°C/W
TJmax = 100 °C + (51 °C/W × 134 mW) = 100 °C + 7 °C = 107 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8), unless user reduces the power dissipation to be able to use suffix 6 parts.

172/178 DS11929 Rev 5

STM32WB55xx Ordering information

8 Ordering information

Example: STM32 WB 55 V G V 6 TR

Device family
STM32 = Arm® based 32-bit microcontroller

Product type
WB = Wireless Bluetooth®

Device subfamily
55 = Die 5, full set of features

Pin count
C = 48 pins
R = 68 pins
V = 100 pins

Flash memory size

C = 256 KB
E = 512 KB
G = 1 MB

Package
U = UFQFPN48 7 x 7 mm
V = VFQFPN68 8 x 8 mm
Y = WLCSP100 0.4 mm pitch
Q = BGA129 0.5 mm pitch

Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
7 = Industrial temperature range, -40 to 105 °C (125 °C junction)

Packing
TR = tape and reel
xxx = programmed parts

DS11929 Rev 5 173/178

DS11929 Rev 5 177/178

177
STM32WB55xx

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

178/178 DS11929 Rev 5

BFT Sce-Ma
No ratings yet
BFT Sce-Ma
16 pages
Connection To CS8C Via FTP Client Software
No ratings yet
Connection To CS8C Via FTP Client Software
4 pages
990-091 - 1215 Addressable Call Point (MCP) Datasheet
No ratings yet
990-091 - 1215 Addressable Call Point (MCP) Datasheet
4 pages
Iot Based On Home Automation
0% (2)
Iot Based On Home Automation
13 pages
AOC L19W931 22W931 SvcMnls
No ratings yet
AOC L19W931 22W931 SvcMnls
88 pages
En DM00235987
100% (1)
En DM00235987
23 pages
Dual DC Regulated Power Supply
No ratings yet
Dual DC Regulated Power Supply
17 pages
2016 - Starr, K. - Control Loop Performance Monitoring (ABBs Experience Over Two Decades)
No ratings yet
2016 - Starr, K. - Control Loop Performance Monitoring (ABBs Experience Over Two Decades)
7 pages
Bently Nevada 3500 15
No ratings yet
Bently Nevada 3500 15
6 pages
ABB Contactor Relays
100% (1)
ABB Contactor Relays
17 pages
Self Switching Power Supply
No ratings yet
Self Switching Power Supply
20 pages
WeeBee Z-0002 ZigBee Module Manual
No ratings yet
WeeBee Z-0002 ZigBee Module Manual
20 pages
Wonderware Siemens - SIDirect OI Server G-2.2 Series SMC - Technology Matrix
No ratings yet
Wonderware Siemens - SIDirect OI Server G-2.2 Series SMC - Technology Matrix
4 pages
FPA 5000 Data Sheet enUS FPA 5000
No ratings yet
FPA 5000 Data Sheet enUS FPA 5000
7 pages
SCE - EN - 020-060 - R1209 - Diagnose Und Fehlersuche
No ratings yet
SCE - EN - 020-060 - R1209 - Diagnose Und Fehlersuche
36 pages
How To Setup Teamviewer VPN
No ratings yet
How To Setup Teamviewer VPN
10 pages
Wincc Oa User Days 2016 Communication Drivers Protocols
No ratings yet
Wincc Oa User Days 2016 Communication Drivers Protocols
13 pages
00 - Simatic S7-1200 (Srpski)
No ratings yet
00 - Simatic S7-1200 (Srpski)
46 pages
Rittal Automation Systems - We Automate Panel Building 5 4329
No ratings yet
Rittal Automation Systems - We Automate Panel Building 5 4329
108 pages
Sensors
100% (1)
Sensors
40 pages
FX5 Users Manual Melsec Communication Protocol ENG Ver A
No ratings yet
FX5 Users Manual Melsec Communication Protocol ENG Ver A
104 pages
CanOpen Primer
No ratings yet
CanOpen Primer
13 pages
Setup Teamviewer - VPN Connection To Program Remote PLC'S and Hmi-Panels
No ratings yet
Setup Teamviewer - VPN Connection To Program Remote PLC'S and Hmi-Panels
7 pages
Design of Single Phase Inverter Using Dspic30F4013: Mr. R.Senthilkumar
No ratings yet
Design of Single Phase Inverter Using Dspic30F4013: Mr. R.Senthilkumar
7 pages
T3806
No ratings yet
T3806
1 page
VMware Health Analyzer Install and User Guide v5.0.5 en
No ratings yet
VMware Health Analyzer Install and User Guide v5.0.5 en
48 pages
SCE EN 010-020 R1209 S7-1200 Blocks
No ratings yet
SCE EN 010-020 R1209 S7-1200 Blocks
41 pages
FP1200 - 2000C Control Panels PDF
No ratings yet
FP1200 - 2000C Control Panels PDF
150 pages
Lez10a KNX Architecture v3.0
No ratings yet
Lez10a KNX Architecture v3.0
26 pages
Foxtrot For Building
No ratings yet
Foxtrot For Building
37 pages
Blu 1000.1 1200.1 PAB 2013 GAS
No ratings yet
Blu 1000.1 1200.1 PAB 2013 GAS
14 pages
Sew Motor Eurodriver
No ratings yet
Sew Motor Eurodriver
361 pages
Model-Based Control of The Mitsubishi PA-10 Robot Arm: Application To Robot-Assisted Surgery
No ratings yet
Model-Based Control of The Mitsubishi PA-10 Robot Arm: Application To Robot-Assisted Surgery
6 pages
Library Guideline DOC v13 en
No ratings yet
Library Guideline DOC v13 en
101 pages
s71500 Counting Measuring Function Manual en-US en-US
No ratings yet
s71500 Counting Measuring Function Manual en-US en-US
205 pages
Oi Wsd161 Wsl2
100% (1)
Oi Wsd161 Wsl2
85 pages
TC V1 28 en
No ratings yet
TC V1 28 en
40 pages
Rittal AC Unit Basic Tech Guide
100% (1)
Rittal AC Unit Basic Tech Guide
7 pages
93c46 Datasheet
No ratings yet
93c46 Datasheet
12 pages
Elfin-EW1X User ManualV1.3 (20200415)
100% (1)
Elfin-EW1X User ManualV1.3 (20200415)
26 pages
Omron E5cj-Q2hb Datasheet
100% (1)
Omron E5cj-Q2hb Datasheet
6 pages
Io Link Handbook
No ratings yet
Io Link Handbook
68 pages
XL Web Specification
No ratings yet
XL Web Specification
4 pages
3HAC17076-1 Revh en
No ratings yet
3HAC17076-1 Revh en
642 pages
IEC Moeller
No ratings yet
IEC Moeller
66 pages
Autosim 200 en
No ratings yet
Autosim 200 en
8 pages
SIEMENSG120
100% (1)
SIEMENSG120
358 pages
DAC Using ATmega 16 PDF
No ratings yet
DAC Using ATmega 16 PDF
4 pages
Kvs Ether Net IP
No ratings yet
Kvs Ether Net IP
876 pages
Suswe
No ratings yet
Suswe
47 pages
stm32wb55vg PDF
No ratings yet
stm32wb55vg PDF
183 pages
STM 32 WB 55 CC
No ratings yet
STM 32 WB 55 CC
196 pages
STM 32 WB 10 CC
No ratings yet
STM 32 WB 10 CC
112 pages
STM32WLE5CCU6
No ratings yet
STM32WLE5CCU6
145 pages
STM 32 WL 55 CC
No ratings yet
STM 32 WL 55 CC
148 pages
STM 32 Wle 5 CC
No ratings yet
STM 32 Wle 5 CC
149 pages
STM 32 L 412 KB
No ratings yet
STM 32 L 412 KB
192 pages
stm32l433vc (1)
No ratings yet
stm32l433vc (1)
227 pages
STM 32 L 433 CC
No ratings yet
STM 32 L 433 CC
227 pages
STM32L476RG STMicroelectronics
No ratings yet
STM32L476RG STMicroelectronics
271 pages
STM 32 L 412 KB
No ratings yet
STM 32 L 412 KB
198 pages
Analog Dialogue, Volume 45, Number 4: Analog Dialogue, #4
From Everand
Analog Dialogue, Volume 45, Number 4: Analog Dialogue, #4
Analog Dialogue
No ratings yet
KRH / KLH Series: Small & Compact Product ! Customization Service !
No ratings yet
KRH / KLH Series: Small & Compact Product ! Customization Service !
10 pages
About Slicing
No ratings yet
About Slicing
2 pages
Roatary Actuators - Rima
No ratings yet
Roatary Actuators - Rima
6 pages
Baumer - HOG10 DN 1024 I SR 16H7 KLK - EN - 20230816 - DS
No ratings yet
Baumer - HOG10 DN 1024 I SR 16H7 KLK - EN - 20230816 - DS
4 pages
Ropeblock - Open Spelter Sockets With Bolt and Nut - Metric
No ratings yet
Ropeblock - Open Spelter Sockets With Bolt and Nut - Metric
1 page
CMP E Type Explosive
No ratings yet
CMP E Type Explosive
2 pages
Wire Rope Guidelines - Strand Core
No ratings yet
Wire Rope Guidelines - Strand Core
1 page
Fy 2008 Evaluation of The 2007 Toyota Camry Hybrid Synergy Drive System
No ratings yet
Fy 2008 Evaluation of The 2007 Toyota Camry Hybrid Synergy Drive System
102 pages
Reversible Pump - Bucher Gear Pump AP05
No ratings yet
Reversible Pump - Bucher Gear Pump AP05
26 pages
Newtek CT Nylon-Casing
No ratings yet
Newtek CT Nylon-Casing
16 pages
Roatary Actuators - Micromatic Repair Manual - 26R-2 Thru 26R-124
No ratings yet
Roatary Actuators - Micromatic Repair Manual - 26R-2 Thru 26R-124
14 pages
O-Ring - NOK AS568 Series
No ratings yet
O-Ring - NOK AS568 Series
4 pages
Roatary Actuators - Micromatic Repair Manual - HS-1.5 Thru HS-015
No ratings yet
Roatary Actuators - Micromatic Repair Manual - HS-1.5 Thru HS-015
11 pages
X-Ring - Trelleborg
No ratings yet
X-Ring - Trelleborg
32 pages
Ethernet Physical Layer Transceiver - TI DP83867IR
No ratings yet
Ethernet Physical Layer Transceiver - TI DP83867IR
131 pages
Comparators With Shutdown - TI TLV3501
No ratings yet
Comparators With Shutdown - TI TLV3501
29 pages
dp83848q q1
No ratings yet
dp83848q q1
83 pages
Ethernet Physical Layer Transceiver - TI DP83825I
No ratings yet
Ethernet Physical Layer Transceiver - TI DP83825I
78 pages
Comparators With Shutdown - Maxim MAX40008-MAX40009
No ratings yet
Comparators With Shutdown - Maxim MAX40008-MAX40009
14 pages
Comparators With Shutdown - TI LMV761
No ratings yet
Comparators With Shutdown - TI LMV761
25 pages
Arm STM32H742 PDF
No ratings yet
Arm STM32H742 PDF
357 pages
Acti 9 iEM3000 - A9MEM3235
No ratings yet
Acti 9 iEM3000 - A9MEM3235
2 pages
Panasonic Controlrelay Catalog PDF
No ratings yet
Panasonic Controlrelay Catalog PDF
6 pages
Belch Sample CH 10
No ratings yet
Belch Sample CH 10
30 pages
Aspire 5935-5935g (sm50 - MV) Service Manual Guide SG - sm50-mv - 032709
No ratings yet
Aspire 5935-5935g (sm50 - MV) Service Manual Guide SG - sm50-mv - 032709
224 pages
Evaluating Your Current Computer System
No ratings yet
Evaluating Your Current Computer System
8 pages
Lesson 1-Introducing Basic Network Concepts
No ratings yet
Lesson 1-Introducing Basic Network Concepts
38 pages
DVD Home Theater System: Owner'S Manual
No ratings yet
DVD Home Theater System: Owner'S Manual
42 pages
AWS Dev Part1
No ratings yet
AWS Dev Part1
178 pages
E50417 H1176 C151 A8
No ratings yet
E50417 H1176 C151 A8
558 pages
PCI Express 10G Dual Port Copper Server Adapter
No ratings yet
PCI Express 10G Dual Port Copper Server Adapter
7 pages
GRID Licensing Guide
No ratings yet
GRID Licensing Guide
22 pages
H67H2 M3 Manual
No ratings yet
H67H2 M3 Manual
84 pages
RCPT Info
No ratings yet
RCPT Info
2 pages
HP Pavillion dv9700
No ratings yet
HP Pavillion dv9700
2 pages
ICND1 CH - 7
No ratings yet
ICND1 CH - 7
62 pages
Starting With Tableau: Downloading The Tableau Trial
No ratings yet
Starting With Tableau: Downloading The Tableau Trial
5 pages
Manual PHP JRU
No ratings yet
Manual PHP JRU
29 pages
CHP 4 Reading Organizer - Student Version
No ratings yet
CHP 4 Reading Organizer - Student Version
6 pages
April / May Examination, 2014
No ratings yet
April / May Examination, 2014
3 pages
Cisco Flex Link
No ratings yet
Cisco Flex Link
10 pages
HC5 Service Manual
100% (1)
HC5 Service Manual
112 pages
Switch Matrix Controller
No ratings yet
Switch Matrix Controller
56 pages
RS232 Camera User Guide V1.1
No ratings yet
RS232 Camera User Guide V1.1
15 pages
Vehicle Communication Box: Appendix 1 Technical Specification
No ratings yet
Vehicle Communication Box: Appendix 1 Technical Specification
32 pages
EVE 2 Module Manual Rev 1.4
No ratings yet
EVE 2 Module Manual Rev 1.4
18 pages
SCADA Overview PDF
No ratings yet
SCADA Overview PDF
21 pages
Jbase Database - Administration
100% (3)
Jbase Database - Administration
17 pages
Microcontroller-Based Spartan-3 Generation Fpga Configurator
No ratings yet
Microcontroller-Based Spartan-3 Generation Fpga Configurator
6 pages
ICT Presentation
No ratings yet
ICT Presentation
26 pages
TAC Xenta: Connection Cable TAC Xenta-RS232 (Part No. 007309030 To Be Phased Out
No ratings yet
TAC Xenta: Connection Cable TAC Xenta-RS232 (Part No. 007309030 To Be Phased Out
2 pages

Arm STM32WB55 PDF

Uploaded by

Arm STM32WB55 PDF

Uploaded by

STM32WB55xx

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4

and MAC, supporting Thread and

October 2019 DS11929 Rev 5 1/178

– High speed internal 16 MHz factory – Touch sensing controller, up to 18 sensors

Table 1. Device summary

STM32WB55CC, STM32WB55RC, STM32WB55VC

2/178 DS11929 Rev 5

DS11929 Rev 5 3/178

3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 41

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4/178 DS11929 Rev 5

6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DS11929 Rev 5 5/178

6.3.29 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 149

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

6/178 DS11929 Rev 5

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS11929 Rev 5 7/178

Table 45. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

8/178 DS11929 Rev 5

Table 97. WLCSP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

DS11929 Rev 5 9/178

Figure 1. STM32WB55xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10/178 DS11929 Rev 5

DS11929 Rev 5 11/178

The STM32WB55xx multiprotocol wireless and ultra-low-power devices embed a powerful

12/178 DS11929 Rev 5

Table 2. STM32WB55xx devices features and peripheral counts

Flash memory density 256 KB 512 KB 1 MB 256 KB 512 KB 1 MB 256 KB 512 KB 1 MB

DS11929 Rev 5 13/178

Table 2. STM32WB55xx devices features and peripheral counts (continued)

Ambient operating temperature:-40 to +105 °C

14/178 DS11929 Rev 5

Figure 1. STM32WB55xx block diagram

AHB Lite (Shared)

FPU MPU Power Supply POR/

DMA2 7 channels WWDG

DS11929 Rev 5 15/178

3.2 Arm® Cortex®-M4 core with FPU

16/178 DS11929 Rev 5

3.3.1 Adaptive real-time memory accelerator (ART Accelerator™)

3.3.2 Memory protection unit

3.3.3 Embedded Flash memory

DS11929 Rev 5 17/178

Main 1 Yes Yes Yes No No No

System 1 Yes No No Yes No No

Option 1 Yes Yes Yes Yes Yes Yes

18/178 DS11929 Rev 5

3.3.4 Embedded SRAM

3.4 Security and safety

3.5 Boot modes and FW update

DS11929 Rev 5 19/178

3.6.1 RF front-end block diagram

20/178 DS11929 Rev 5

Figure 2. STM32WB55xx RF front-end block diagram

VDDSMPS VSSSMPS VLXSMPS VFBSMPS VDDRF

3.6.2 BLE general description

DS11929 Rev 5 21/178

In addition, according to Bluetooth® specification v5.0, the BLE block provides:

22/178 DS11929 Rev 5

3.6.3 802.15.4 general description

3.6.4 RF pin description

Table 4. RF pin list

3.6.5 Typical RF application schematic

DS11929 Rev 5 23/178

Figure 3. STM32WB55xx external components for the RF part

Table 5. Typical external components

C1 Decoupling capacitance for RF 100 nf // 100 pF

3.7 Power supply management

3.7.1 Power supply distribution

24/178 DS11929 Rev 5

Figure 4. Power distribution

SMPS configuration LDO configuration