1.The ARM core uses ____ Architecture.

a) RISC b) CISC c) Both D) none

2. ARM Processor specifically designed for to reduce ___

a) Size b) Power Consumption C) both d) none.

3.ARM Processor core is a key component of ___ bit embedded system.

a)8 b) 16 c)32 d)64

4.RISC Philosophy implemented with ___ major deign goals.

a) 4 b)6 c)8 d)16

5.____ is the processing of instruction broken down to smaller unit.

a) Pipeline b) ALU c) MCU d) All

6.Register contains ___

a) Address b) data c) both d) none

7.___ Instruction used to transfer the data between register and memory.

a) Load b)store c) bothd) none

8.The design rule s allow a RISC to be __

a)simpler b) complicated c) both d) none

9.ARM means ___

a) Advance Risc Machine b) Advance Review machine c) Advance Risc mechanism d) All

10.RISC means ____

a)Reduced Instruction set computer b) Reduced Instruct set computer C) both d) None

11.CISC means _____

a) Complicated Instruction set computer b) completed Instruction set computer C) both d) None

12.___ is used to communicate between part of the device

13.____ is used to connect peripherals.

a) PCI b) ALU c) MCU d) All

14.ARM bus has __ Architecture level.

a) 2 b) 3 c) 4 d) 5

15._____ level covers electrical characteristics.

a) Physical b) logical c)temporal d) all

16.____ level govern communication between the processor and peripheral.

a) Physical b) logical c)temporal d) all

17.AMBA bus was introduced in the year of _____

a)1996 b)2000 c)1998 d) 1990

18.AMBA means____

a) Advance microcontroller bus architecture b) advance Machine bus architecture C) both d)

19.____ is placed between main memory and core .

a)cacheb) RAM c)ROM d) all

20.____ is used to sped up data transfer

a)cacheb) RAM c)ROM d) all

21.____ doesn't require refreshing.

a)SRAM b) DRAM c) PROM d) EPROM

22.____ interrupt controller available in ARM Processor.

a)2 b)3 c)4 d)5

23.____ memory require refreshing.

24.SRAM means____

a)Static RAM b) Stable RAM c) Standard RAM d) none.

25. Application of ARM processor is____

a) automotive) consumable c) mobile d) all

1.In ARM processor data items are placed in ____ file.

a)Register b) I/O c) memory d) all

2.ARM instruction typically have ___ source register.

a)2b)3c)4d)5

3.ALU means____

a) Arithmetic logic unit b) Adder logic unit c) both d) none

4.MAU means ________

a) Multiply Accumulate unit b) Multiple adder unit c) Multiple accumulate unit d) none

5.General purpose registers holds the _____

a) Data b) Address c)both d) none

6.___ Register is used as the stack pointer.

a) r13 b) r14 c) r15 d) r16

7.____ register is called the link register.

a) r13 b) r14c) r15 d) r16

8.In ARM program register has __ types

a) 2 b) 3 c) 4 d) 5

9. Privileged mode allows ___ access .

10. Non Privileged mode allows ___ access .

a) read b) write c) bothd) none

11. In ARM consists of ______ processor mode.

a) 7 b) 5 c) 4 d) 6

13.How many bank registers are available in ARM?

a) 20 b) 25 c) 30 d) 40

14. The SPSR store the ___ mode of CPSR

a) Present b) previous c) both d) none

15.____ are used to stop specific interrupt.

a) Interrupt mask b) Interrupt request c) both d) none

16. CPSR has ___ interrupt mask bits.

a)2 b) 5 c) 6 d) 4

17.___ interrupt levels available on theARM processor.

a) 2 b) 5 c) 6 d) 4

18.____ is the mechanism of RISC processor.

a) pipeline b) task c) sequence d) none

19. _____ is the process of loading instructions

a) Fetch b) decode c) Execute d) all

20.____ is used to identify the instruction to be executed.

a)Fetch b) decode c) Execute d) all

21.MMU means ____

a) Memory management unit b) memory mask unit c) main memory unit d) none
22.MPU means ____

a) Memory protection unit b) memory processor unit c) multiple process unit d) none

23.____ are used to extent the instruction set.

a) Coprocessor b) pipeline c) multiprocessor d) none

24.____ is used to organize memory.

a) MMU b) MPU c) MCU d) none

25.____ vector is used by external hardware to interrupt the normal execution.

a) Interrupt b) mask c) Pipeline d) none

1.ARM instruction commonly take ___ operands.

a) 2 b) 3 c) both d) none

2.Data processing instructions manipulate data within ___

a) registers b) memory c) address d) all

3.___ instruction used to add and subtract of 32 bits.

a) Arithmetic b) logical c) compare d) all

4.____ instruction perform bitwise operations.

a) Arithmeticb) logical c) compare d) all

5.____ instruction are used to test a register.

a) Arithmeticb)logical c) compare d) all.

6 ___ instruction changes the flow of execution.

a) Arithmeticb)logical c) compare d) Branch.

7.___ instruction used to load word in register.

A) LDR b) STR c) STRB d) LDRB

8. ___ instruction used to save a word or byte from a register.

9.___ instruction used to load a byte in to a register.

A) LDR b) STR c) STRB d) LDRB

10. ___ instruction used to save a byte from a register.

A) LDR b) STR c) STRB d) LDRB

11.___ instruction used to carry out stack operations

a) Load b) store c) both d) none

12.___ operation remove the data from the stack.

a) POP b) PUSH c) both d) none

13. ___ operation place the data on to stack.

a)POPb) PUSH c) both d) none

14. SW1 is a ___interrupt instruction.

a) Software b) hardware c) both d) none

15.___ instruction change the content of memory with the content of register.

a) SWAP b) load c) store d) add

16.____ instruction transfer the content of CPSR into a register file.

a)MRS b) CPSR c) MSR d) none

17. .____ instruction transfer the content of register into a CPSR file.

a)MRS b) CPSR c) MSR d) none

18. ___ is called the system control coprocessor

a) CP15 b) CP16 c) CP18 d) CP17

19.THUMP has ___ code density.

a)higherb) lower c) medium d) none

a) 32 b) 16 c) 8 d)64

21.___ is used for arithmetic shift left.

a) ASR b)ASLc) CMP d) CMN

22. ____ is used for logical shift left.

a) LSL b) ASL c) CMP d)LSR

23. ____ is used for logical shift left.

a) LSL b) ASL c) CMP d)LSR

24.___ is used for compare two 32-bit integer.

a) LSL b) ASL c) CMP d)CMN

25. ___ is used for comparenegative two 32-bit integer.

a) LSL b) ASL c) CMP d) CMN

1) AD microcontroller 7128 has ______ bytes of Flash memory.

a)126k b)256k c) 512 d) 1M

2) AD microcontroller 7128 has ______ bytes of SRAM

a)8k b)16k c)24k d) none

3) AD microcontroller 7128 has ______ ADC channel.

a)8b)10 c) 12 d) 24

4) The ARM7 core Support___

a) RISC b) CISC c) Both d) None

5) AD microcontroller 7128 has____ Pin GPIO Port

a)14b)28 c) 32 d) 42

6)ADC consists of up to ____single-ended inputs.

7) The ARM7 core is a ____it Reduced Instruction Set Computer

a) 32 b) 16 c)8 d)64

8) ARM supports____types of exceptions.

a)5 b) 4 c) 3 d) 2

9) ARM7TDMI has a total of ____ registers.

a)37b)24 c)8 d)16

10 ) ARM7TDMI has a total of ____ General Purpose registers .

a)31 b) 24 c)8 d)16

11) ARM7TDMI has a total of ____ status registers .

a)6 b)24 c)8 d)16

12) Thumb code usually uses more instructions for the _____ job.

a)Same b)different c) both d) none

13) The 128kBytes of Flash/EE are organised as_____ banks

a) 2 b)24 c)8 d)16

14) The MMR space provides an______ between the CPU and all on-chip peripherals

a)Interface b) logic c) link d) none

15) _____is provided to service general-purpose interrupt handling of internal and external
events.

a)IRQ b) FIQ c) SWI d) None

16) ___is provided to service data transfer or communication channel with low latency.

a)IRQ b) FIQ c) SWI d) None

17) _____ is used to make a call to an operating system.

18) The minimum latency for FIQ or IRQ interrupts is ___ cycle

a) 5 b) 10 c)15 d)20

19) ____Bytes of SRAM are available to the user, organized as 2k X 32 bits.

a) 8k b) 8M c) 8G d) 8

20) The access time reading or writing a MMR depends on the___

a)AMBA b)AMCA c)AMDA d)AMEA

21) The ARM7TDMI is an ARM7 core with ____additional features.

a) 4 b) 10 c)15 d)20

22) The ARM7TDMI T support for the _____

A )Thump b)Multiplies c)debug d) none

23) The ARM7TDMI D support for ____

A )Thump b)Multiplies c)debug d) none

24) The ARM7TDMI M support for ____

A )Thumpb)Multiplies c)debug d) none

25) ADC consists of a _____bit successive-approximation converter

a)12 b) 5 c) 16 d)24
1) ADC can operate in___ different modes.

a)3 b) 5 c) 16 d)24

2)_____ mode, for small and balanced signals.

a)Fully differential b)Single-ended c)both d) None

3)____mode isused for any single-ended signals.

a)Fully differential b)Single-ended c)both d) None

4)Single or continuous conversion modes can be initiated in ____

a) Software b) Hardware c) firmware d) all

5)____Control Register allows the programmer to enable the ADC peripheral

a)ADCCON b) ADCCP c )ADCCN d) none

6)ADCCP refers ADC ___Channel selection Register

a)Positive b) Negative c) Both d) None

7)ADCCN refers ADC ___Channel selection Register

a)Positiveb) Negative c) Both d) None

8)____ register indicates ADC conversion result is ready.

a) Status b) control c) both d) none

9)ADC Data Result Register, hold the ____bit ADC result

a)12 b) 5 c) 16 d)24

10)___ Register. Resets all the ADC registers

a)ADC Reset b) ADCCP c )ADCCNd)ADCCON

.11)The ADuC7128 contains a successive approximation ADC based on___ capacitive DACs.

a)2 b) 5 c) 16 d)24

12)The ADuC7128 provides an on-chip bandgap reference of___ volts.

13)Fetching instructions from SRAM takes_____ clock cycle

a)1 b) 5 c) 16 d)24

14)In ARM mode, where instructions are 32 bits,_____ cycles are needed to fetch any
instruction.

a)2 b) 5 c) 16 d)24

15)The ADuC7128 integrates a _____oscillator, a clock divider and a PLL.

a)32.768kHz b) 32.768MHz c)32.768GHz d) None

16) The ADuC7128 integrates a ______channel PWM interface.

a)6 b) 5 c) 16 d)24

17)The ADuC7128 provides _______ general purposeI/O.

a)28 b) 5 c) 16 d)24

18)The ADuC7128 contains______ identical UART blocks.

a)2 b) 5 c) 16 d)24

19)COMxTX is a ______bit transmit register.

a)8 b) 5 c) 16 d)24

20) COMxRX: is a 8-bit ____register.

a) Transmit b)Receive c

21) COMxIEN1is a _____bit network enable register.

a)8 b) 5 c) 16 d)24

22) COMxADR is a 8-bit ___ network address register.

a)Read b)write C) Both d) none

23) The MISO pin is configured as an input line in ____mode.

24)The MOSI pin is configured as an ____line in master mode

a)Output b)Input c) both d) none

25)The master serial clock (SCL) is used to ______the data

a)synchronize b) asynchronize c) both d) none