Lecture Outline

ESE 570: Digital Integrated Circuits and

!  3 Regions of operation for MOSFET
VLSI Fundamentals "  Subthreshold
"  Linear
Lec 5: January 31, 2019 "  Saturation
MOS Operating Regions, pt. 1 !  Level 1 Model

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MOS Capacitor with External Bias 2-terminal MOS Cap # 3-terminal nMOS
!  Three Regions of Operation:
"  Accumulation Region – VG < 0 (Cut-off) 0

"  Depletion Region – VG > 0, small (Subthreshold)

"  Inversion Region – VG ≥ VT, large (Above Threshold)

VG ≥ V T

- - - - - - - - - -

Cut-off/Subthreshold Above threshold

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2-terminal MOS Cap # 3-terminal nMOS nMOS = MOS cap + source/drain

VG VD
VSB = 0
VS
VG VD
VS - -
- - -
-
- - - - -
- - - - - -
- - - -
depletion region - -

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 Review: Threshold Voltage MOSFET – IV Characteristics

50
VDS

Drain current [arbitrary unit]

40
Qox Q
for VSB = 0 VT =VT 0 = ΦGC − − 2ΦF − B0
Cox Cox 30
IDS
for VSB != 0 VT = VT 0 + γ ( 2Φ F −VSB − 2Φ F ) 20

2qN Aε Si
γ= 10
Cox

0
0 2 4 6 8 10
Gate to source voltage [V]

VGS
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MOSFET – IV Characteristics Cutoff Region

VGS < 0 NMOS TRANSISTOR IN CUTOFF REGION
VG VD
VDS <VGS -VTH
VS

VGS -Vth - - -
IDS -
Depletion
VDS ≥VGS -VTH - - - - - -
region
Immobile
Substrate or
p acceptor
Bulk B
ions

No depletion or inversion layer under oxide, no current flow

VDS
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Depletion Region Onset of Inversion Region

VGS = VT0n + δ
0 < VGS < VTH VDS = 0
VG VD
VS VG VD
QI
QB0
- - - - - - -
- - - - -
- - - depletion region-
- - - -
- -
-
- - -

Depletion layer under oxide, leakage/subthreshold current flow

Depletion region, and thin inversion layer (aka channel)
Thermal equilibrium in channel, leakage-level current flow
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 MOSFET – IV Characteristics Linear Region
VDS VGS > VT0
50
VDS small, VDS < VGS - VT0
Drain current [arbitrary unit]

40

30
IDS -
- - - -
20 n+ - - n+
- - - -
10

Channel acts like voltage controlled resistor

0 Current flows proportional to VDS ( I D ∝VDS )
0 2 4 6 8 10
As VD increases, channel depth at the drain decreases
Gate to source voltage [V]

VGS
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Channel Voltage Voltage along Channel

!  Voltage varies along channel !  Voltage divider between VS and VD
!  Channel acts as a resistor
"  Serves as a voltage divider between VS and VD

y=0 y=L

V(y)
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Voltage along Channel Voltage along Channel

!  Voltage divider between VS and VD !  Voltage divider between VS and VD

y=0 y=L y=0 y=L

Vd Vd
V(y) V(y)
Vs y Vs y
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 Voltage along Channel Channel Field
!  Voltage divider between VS and VD !  When voltage gap VG - Vy drops below Vth, channel
drops out of inversion
"  If VDS = VGS – Vth #VGS – VDS =VG – VD = Vth

y=0 y=L
Vd
V(y)
Vs
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Linear/Saturation Region Edge Saturation Region

VGS > VT0 VGS > VT0
VDS = VGS – VT0 VDS > VGS – VT0

VDS - VDSAT

- -
-
- - - z - - - - V(x) = VDSAT
n+ - - - n+ n+ -
- - n+ -
- -
- - - - - -

Voltage divider along channel, until pinch off

As VD increases, channel depth at the drain decreases

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MOSFET IV Characteristics – Linear Region

VGS > VT0
Level 1 Model VDS small, VDS < VGS - VT0

Linear and Saturation IV Models

n+ z n+

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 MOSFET IV Characteristics – Linear Region MOSFET IV Characteristics – Linear Region
VGS > VT0 VGS > VT0
VDS small, VDS < VGS - VT0 VDS small, VDS < VGS - VT0

n+ z n+ n+ z n+

V(y) V(y)

Boundary Conditions: Boundary Conditions: V(y=0) = VS = 0, V(y=L) =VDS

Mobile charge in inverted channel: Mobile charge in inverted channel:

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MOSFET IV Characteristics – Linear Region MOSFET IV Characteristics – Linear Region

VGS > VT0
VDS small, VDS < VGS - VT0

z
n+ n+ yy
z
x
dy
dR = −
V(y) W ⋅ µ n ⋅ QI (y)

Boundary Conditions: V(y=0) = VS = 0, V(y=L) =VDS

Mobile charge in inverted channel: QI(y) = - Cox [VGS – V(y) - VT0] µn = electron mobility = cm2/(V sec)

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MOSFET IV Characteristics – Linear Region MOSFET IV Characteristics – Linear Region

dy dy
QI(y) = – Cox [VGS – V(y) – VT0] dR = − QI(y) = – Cox [VGS – V(y) – VT0] dR = −
W ⋅ µ n ⋅ QI (y) W ⋅ µ n ⋅ QI (y)

Incremental potential dVCS ID Incremental potential dVCS ID

drop across the dVC = I D ⋅ dR =− dy drop along the dVC = I D ⋅ dR =− dy
channel segment with W ⋅ µ n ⋅ QI (y) channel segment with W ⋅ µ n ⋅ QI (y)
width dy width dy
−W ⋅ µ n ⋅ QI (y)⋅ dVC = I D ⋅ dy −W ⋅ µ n ⋅ QI (y)⋅ dVC = I D ⋅ dy

Integrate along the channel: V(y=0) = VS , V(y=L) = VDS

L VDS

∫ I D ⋅ dy = ∫ −W ⋅ µn ⋅ QI ( y) ⋅ dVC
0 0
VDS
I D ⋅ L = W ⋅ µ n ⋅Cox ∫ (VGS −VC −VT 0 ) ⋅ dVC
0

W⎛ V2 ⎞
I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟
L ⎜⎝ GS T 0 DS 2 ⎟⎠
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 MOSFET IV Characteristics – Linear Region MOSFET IV Characteristics
!  Example: For an nMOS transistor with μn = 600cm2/Vsec,
W# V2 & Cox = 7x10-8 F/cm2, W = 20μm, L = 2 μm, VT0 = 1V, plot
I D = µ n ⋅ Cox % (VGS −VT 0 )VDS − DS (
L$ 2 ' the relationship between ID and VDS, VGS.

W
k ' = µ n ⋅ Cox k = k'
L

k' W k
ID =
2 L
(2(VGS −VT 0 )VDS −V 2DS ) ID =
2
(2(VGS −VT 0 )VDS −V 2DS )

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MOSFET IV Characteristics MOSFET IV Characteristics

!  Example: For an nMOS transistor with μn = 600cm2/Vsec, !  Example: For an nMOS transistor with μn = 600cm2/Vsec,
Cox = 7x10-8 F/cm2, W = 20μm, L = 2 μm, VT0 = 1V, plot Cox = 7x10-8 F/cm2, W = 20μm, L = 2 μm, VT0 = 1V, plot
the relationship between ID and VDS, VGS. the relationship between ID and VDS, VGS.
W⎛ V2 ⎞ W⎛ V2 ⎞
I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟⎟ I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟⎟
L ⎜⎝ GS T 0 DS 2 ⎠ L ⎜⎝ GS T 0 DS 2 ⎠
⎛ V2 ⎞ ⎛ V2 ⎞
I D = 0.42mA /V 2 ⎜⎜ (VGS −1.0)VDS − DS ⎟⎟ I D = 0.42mA /V 2 ⎜⎜ (VGS −1.0)VDS − DS ⎟⎟
⎝ 2 ⎠ ⎝ 2 ⎠

ID(VDS = VDSAT) and VDSAT = VGS - VT0

Assumptions:

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MOSFET IV Characteristics MOSFET IV Characteristics

W⎛ V2 ⎞ W⎛ V2 ⎞
I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟ I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟
L ⎜⎝ GS T 0 DS 2 ⎟⎠ L ⎜⎝ GS T 0 DS 2 ⎟⎠
VDS =VDSAT =VGS −VT 0 VDS =VDSAT =VGS −VT 0

W⎛ ⎞ W⎛ ⎞
2 2
(V −V ) (V −V )
I D = µ n ⋅Cox ⎜ (V −V )(V −V ) − GS T 0 ⎟ I D = µ n ⋅Cox ⎜ (V −V )(V −V ) − GS T 0 ⎟
L ⎜⎝ GS T 0 GS T 0 2 ⎟
⎠ L ⎜⎝ GS T 0 GS T 0 2 ⎟
⎠
µ n ⋅Cox W µ n ⋅Cox W
ID = (V −V ) 2 ID = (V −V ) 2
2 L GS T 0 2 L GS T 0

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 MOSFET IV Characteristics MOSFET IV Characteristics

W⎛ V2 ⎞ W⎛ V2 ⎞
I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟ I D = µ n ⋅Cox ⎜ (V −V )V − DS ⎟
L ⎜⎝ GS T 0 DS 2 ⎟⎠ L ⎜⎝ GS T 0 DS 2 ⎟⎠
VDS =VDSAT =VGS −VT 0 VDS =VDSAT =VGS −VT 0

W⎛ (V −V ) 2 ⎞ W⎛ (V −V ) 2 ⎞
I D = µ n ⋅Cox ⎜⎜ (VGS −VT 0 )(VGS −VT 0 ) − GS T 0 ⎟⎟ I D = µ n ⋅Cox ⎜⎜ (VGS −VT 0 )(VGS −VT 0 ) − GS T 0 ⎟⎟
L⎝ 2 ⎠ L⎝ 2 ⎠
µ n ⋅Cox W µ n ⋅Cox W
ID = (V −V ) 2 ID = (V −V ) 2
2 L GS T 0 2 L GS T 0
IN GENERAL
ID(VDS = VDSAT) = ID(sat) ID(VDS = VDSAT) = ID(sat)
ID(sat)
LINEAR SAT LINEAR SAT

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MOSFET IV Characteristics - Saturation MOSFET IV Characteristics - Saturation

VGS > VT0 VGS > VT0
VDSAT VDSAT
VDS > VGS – VT0 VDS > VGS – VT0
ΔL ΔL
n+ n+ n+ n+

µ n ⋅ Cox W 2 µ ⋅C W 2
I DSAT = (VGS − VT 0 ) = n ox $ ΔL ' (VGS − VT 0 )
2 L' 2 L &1− )
% L (

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MOSFET IV Characteristics - Saturation MOSFET IV Characteristics

µ n ⋅ Cox W µ ⋅C W W# V2 &
I DSAT =
2
(VGS − VT 0 ) = n ox $ ΔL ' (VGS − VT 0 )
2 Linear Region: I D = µ n ⋅ Cox % (VGS −VT 0 )VDS − DS (
2 L' 2 L$ 2 '
L &1− )
% L (
µ n ⋅ Cox W 2
Saturation Region: ID = (VGS − VT 0 ) (1+ λ ⋅VDS )
emprically ΔL 2 L
1− ≈ 1− λ ⋅VDS
L

If λ$VDS<<1, ΔL 1
1− ≈ 1− λ ⋅VDS ≈ λ≠0
L 1+ λ ⋅VDS λ=0

µ n ⋅ Cox W 2
ID = (VGS − VT 0 ) (1+ λ ⋅VDS )
2 L

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 MOSFET IV Characteristics MOSFET IV Characteristics
W# V2 & W# V2 &
Linear Region: I D = µ n ⋅ Cox % (VGS −VT 0 )VDS − DS ( Linear Region: I D = µ n ⋅ Cox % (VGS −VT 0 )VDS − DS ( (1+ λ ⋅VDS )
L$ 2 ' L$ 2 '

µ n ⋅ Cox W 2 µ n ⋅ Cox W 2
Saturation Region: ID = (VGS − VT 0 ) (1+ λ ⋅VDS ) Saturation Region: ID = (VGS − VT 0 ) (1+ λ ⋅VDS )
2 L 2 L
DISCONTINUOUS! DISCONTINUOUS!
@ VDS = VDSAT @ VDS = VDSAT
λ≠0 λ≠0
λ=0 λ=0

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MOSFET IV Characteristics MOSFET IV Characteristics, VSB≠0

W# V2 &
Linear Region: I D = µ n ⋅ Cox % (VGS −VT 0 )VDS − DS ( (1+ λ ⋅VDS ) VT = VT 0 + γ ( 2Φ F −VSB − 2Φ F )
L$ 2 '

µ n ⋅ Cox W 2
Saturation Region: ID = (VGS − VT 0 ) (1+ λ ⋅VDS ) W# V2 &
2 L Linear Region: I D = µ n ⋅ Cox % (VGS −VT (VSB ))VDS − DS ( (1+ λ ⋅VDS )
DISCONTINUOUS! L$ 2 '
Level 1 model
@ VDS = VDSAT
λ$VDS<<1
µ n ⋅ Cox W 2
λ≠0 Saturation Region: ID = (VGS − VT (VSB )) (1+ λ ⋅VDS )
λ=0 2 L

I D = f (VGS ,VDS ,VSB )

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nMOS IV Characteristics pMOS IV Characteristics

% %
' 0 VGS ≤ VTn ' 0 VGS ≥ VTp
' Cutoff/Subthreshold
' Cutoff/Subthreshold
' µ ⋅C W ' µ ⋅C W
I D = & n ox
2 L
( GS Tn SB )) VDS − V 2DS ) (1+ λ ⋅VDS )
2 (V − V (V VGS > VTn ,VDS < VGS − VTn I D = & p ox
2 L
( )
2 (VGS − VTp (VSB )) VDS − V 2DS (1+ λ ⋅VDS ) VGS < VTp ,VDS > VGS − VTp
' Linear/Resistive ' Linear/Resistive
' µ n ⋅ Cox W 2 ' µ p ⋅ Cox W 2
' (VGS − VTn (VSB )) (1+ λ ⋅VDS ) VGS > VTn ,VDS ≥ VGS − VTn ' (VGS − VTp (VSB )) (1+ λ ⋅VDS ) VGS < VTp ,VDS ≤ VGS − VTp
( 2 L Saturation ( 2 L Saturation

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 Measurement of Parameters – kn,p Probe Station

D
G B

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Probe Station Measurement of Parameters – kn,p

D
G B

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Measurement of Parameters – kn,p Measurement of Parameters – kn,p

D D
G B G B

S S

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 Measurement of Parameters – γ Measurement of Parameters – γ

D D
G B G B

S
=> S
=>
SA SA
T T

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Measurement of Parameters – λ Measurement of Parameters – λ

=> SAT => SAT

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Measurement of Parameters – λ

Subthreshold
=> SAT

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 Below Threshold Below Threshold
!  Transition from insulating to conducting is non- !  Transition from insulating to conducting is non-
linear, but not abrupt linear, but not abrupt
!  Current does flow !  Current does flow
"  But exponentially dependent on VGS "  But exponentially dependent on VGS

Penn ESE 570 Spring 2019 – Khanna 61 Penn ESE 570 Spring 2019 – Khanna 62

Parasitic NPN BJT Subthreshold

!  We have an NPN sandwich, mobile minority carriers in the P If VGS < Vth ,
region
⎛ W ⎞ ⎜ GS th ⎟ ⎛
⎛ V −V ⎞ ⎛ VDS ⎞ ⎞
!  This is a BJT! ⎜ ⎟
I DS = I S ⎜ ⎟ e⎝ nkT /q ⎠ ⎜1− e⎝ −kT /q ⎠ ⎟ (1+ λVDS )
"  Except that the base potential is here controlled through a capacitive ⎝L⎠ ⎜ ⎟
divider, and not directly an electrode ⎝ ⎠

!  Current is from the parasitic NPN BJT transistor

when gate is below threshold and there is no
conducting channel
"  n is the capacitive divider between parasitic capacitances
"  Typically 1 < n < 1.5 C +C js ox
n=
Cox

Penn ESE 570 Spring 2019 - Khanna 63 Penn ESE 570 Spring 2019 – Khanna 64

Subthreshold Subthreshold Slope

If VGS < Vth , !  Exponent in VGS determines how steep the turnon
is
⎛W ⎞
⎛ VGS −Vth ⎞
⎜ ⎟ ⎛ ⎛ VDS ⎞
⎜ ⎟ ⎞ " kT %
I DS = I S ⎜ ⎟ e ⎝ nkT /q ⎠ ⎜1− e ⎝ −kT /q ⎠ ⎟ (1+ λVDS ) S = n$ ' ln(10)
⎝L⎠ ⎜ ⎟ # q&
⎝ ⎠

!  Current is from the parasitic NPN BJT transistor "  Units: V/decade
when gate is below threshold and there is no €
"  Every S Volts, IDS is scaled by factor of 10
conducting channel
n is the capacitive divider between parasitic capacitances
⎛ W ⎞ ⎜ GS th ⎟ ⎛
"  ⎛ V −V ⎞ ⎛ VDS ⎞ ⎞
⎜ ⎟
"  Typically 1 < n < 1.5 C +C I DS = I S ⎜ ⎟ e⎝ nkT /q ⎠ ⎜1− e⎝ −kT /q ⎠ ⎟ (1+ λVDS )
n= js ox
⎝L⎠ ⎜ ⎟
Cox ⎝ ⎠
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 Subthreshold Slope IDS vs. VGS
!  Exponent in VGS determines how steep the turnon
is " % kT
S = n$ ' ln(10)
# q&
"  Units: V/dec
"  Every S Volts, IDS is scaled by factor of 10 (Logscale)
€
!  n – depends on parasitic capacitance divider
"  n=1 # S=60mV at Room Temp. (ideal)
"  n=1.5 # S=90mV
"  Single gate structure showing S=90-110mV

Penn ESE 570 Spring 2019 – Khanna 67 Penn ESE 570 Spring 2019 – Khanna 68

IDS vs. VGS Subthreshold Slope

!  If S=100mV and Vth=300mV,
what is Ids(Vgs=300mV)/Ids(Vgs=0V) ?

!  What if S=60mV?

(Logscale) " kT %
S S = n$ ' ln(10)
# q&

⎛ W ⎞ ⎜ GS th ⎟ ⎛
⎛ V −V ⎞ ⎛ VDS ⎞ ⎞
⎜ ⎟
I S ⎜ ⎟ e⎝ nkT /q ⎠ ⎜1− e⎝ −kT /q ⎠ ⎟ (1+ λVDS )
I DS = €
⎝L⎠ ⎜ ⎟
⎝ ⎠
Penn ESE 570 Spring 2019 – Khanna 69 Penn ESE 570 Spring 2019 – Khanna 70

Steady State Leakage

!  What current flows in steady state? !  Call this steady-state current flow leakage
!  What causes (and determines) !  Ids,leak
the magnitude of current flow?
!  Which device?

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 Big Idea Admin
!  3 Regions of operation for MOSFET !  HW 2 due tomorrow
"  Subthreshold !  HW 3 due Friday, 2/8
"  Linear "  Posted tomorrow
"  Saturation "  Gets you started with Cadence
"  Pinch Off "  Make sure you can setup and launch Cadence over the weekend
"  Channel length modulation "  Don’t wait until night before homework is due!
!  Level 1 Model
"  ID=f (VGS, VDS, VSB)
"  Empirical measured parameters: k, γ,λ

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