6 .

1 REGISTERS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 6 .1
1. Registers
 An n-bit register is a set of n flip-flops (or latches) controlled by the same signals
(Synchronization signal, Reset, Set).
 They are used to store n-bit data.

inn-1 inn-2 in1 in0

....
inn-1

inn-2

inn-3

in0
Reset
Load Reg n bits

....
S S S S
D Q D Q D Q D Q
_ _ _ (n) _ outn-1 outn-2 out1 out0
......
Λ

Λ
Q Q Q Q
R R R R
In (n-1,0)
Load
Reset Reset
Load Reg n bits
outn-1

outn-2

outn-3

out0
Out (n-1,0)

2
 6 .1
1. Registers
OE output (Output Enable): connection to a bus.

𝑖𝑛𝑛−1 𝑖𝑛𝑛−2 …… 𝑖𝑛1 𝑖𝑛0

....

Reset
n-bit register
Load
....
𝑂𝐸

…. n-bit BUS

3
 6 .1
2. Shift registers
 Used to shift the stored data one bit to the right (to the left) at each clock pulse.
 Several applications. Examples: 0101110
 multiply by 2  shift to the left and input an lsb = 0, x2  1011100
 divide by 2  shift to the right and input an msb = 0. /2  0010111
in

Serial in

Shift Reg n bits

Reset
S S S (n) S CK
D Q D Q D Q .... D Q
_ _ _ _ ....
Q Q Q Q
Λ
Λ

Λ
Λ

R R R R out n- 1 out n -2 out 1 out 0

Shift
CK Serial in
Reset Reset Shift Reg n bits
CK
Outn-1

Outn-2

Outn-3

Out (n-1,0)

out0
4
 6 .1
2.1 Types of shift registers
1. Shift direction:
a) To the right or to the left, with or without serial input.
b) Cyclic, to the right or to the left.
c) Bidirectional.

EXAMPLE: 5-bit bidirectional shift register.

L/R = 0: left shift
E/D
L/R
L/R = 0: right shift
in

0 S 0 S 0 S 0 S 0 S
D Q 1 D Q D Q 1 D Q 1 D Q
1 _ _ 1 _ _ _
Q Q Q Q Q

Λ
Λ

Λ
R R R R R
CK
Shift

Reset

Out2

out0
Out4

Out3

out1
5
 6 .1
2.1 Types of shift registers

2. Inputs. Commercial chips (use to) have both parallel inputs and serial input.

EXAMPLE: Right shift register with serial input (inn-1), parallel inputs (inn-1, inn-2, ··· , in0) and serial output.

Synchronous load

inn-3
inn-1

inn-2

inn-4
L/S = 0: Load
L/S = 1: Right shift
D/C
L/S
S S S S
D Q
0
1 D Q
0
1 D Q
0
1
..... D Q
_ _ _ _ Serial
Q Q Q Q
Λ

Λ
out
R R R R
CK
Shift

Reset

6
 6 .1
2.2 Other control signals
Apart from L/S (Load/Shift, synchronous load):
 PL (Parallel Load). When active: input bits inn-1, inn-2, ··· , in0 are loaded within the
register independently of the synchronization signal (asynchronous load).
 CE (Clock Enable). When active, the clock signal CK is enabled; when non active, the
clock signal is disabled (in particular: no shift).
 (Output Enable): when = 0, all output buffers are enabled; when = 1 all parallel
outputs in high impedance.
𝑖𝑛𝑛−1 𝑖𝑛𝑛−2 …… 𝑖𝑛1 𝑖𝑛0
....
Reset Serial_Out Synchronous load:
PL or L/S Shift Register
CE (right) L/S: Load/Shift
CK
Asynchronous load:
....
𝑂𝐸 PL: Parallel Load
7
 6 .1
Question 1

Consider the right shift register shown in the figure and check the correct assertion(s):

 Wen L/S is in mode ”L” (Load), inputs inn-1,…,in1,in0

are immediately loaded into the flip-flops.
 Wen L/S is in mode ”L” (Load), inputs inn-1,…,in1,in0 𝑖𝑛𝑛−1 𝑖𝑛𝑛−2 …… 𝑖𝑛1 𝑖𝑛0
are loaded into the flip-flops on the next active clock ....
edge. Reset Serial_Out
 The flip-flop contents are shifted one position to the L/S Shift Register
right on every active clock edge, independently of the CE (right)
value of L/S. CK
 The flip-flop contents are shifted one position to the ....
right on every active clock edge if L/S is in mode ”S” 𝑂𝐸

8
 6 .1
Question 2

Consider the right shift register shown in the figure and check the correct assertion:

o When PL is active, inputs inn-1,…,in1,in0 are

immediately loaded into the flip-flops.
o When PL is active, inputs inn-1,…,in1,in0 are loaded into 𝑖𝑛𝑛−1 𝑖𝑛𝑛−2 …… 𝑖𝑛1 𝑖𝑛0
the flip-flops on the next active clock edge. ....
o The flip-flop contents are shifted one position to the Reset Serial_Out
right on every active clock edge if signal PL is active. PL Shift Register
o The flip-flop contents are shifted one position to the CE (right)
right on every active clock edge, independently of the CK
value of PL. ....
𝑂𝐸

9
 6 .1
2.3 Examples of use of shift registers
1. Arithmetic units: multiply and divide by 2
2. Signal transmission: serial-to–parallel and parallel-to–serial converters.
3. Sequence recognition.

Parallel-to-serial and serial-to-parallel converters:

SR parallel input / serial

SR serial input / parallel

output Shift-Reg

output Shift-Reg

…
…

Origin TRANSMISSION CHANNEL Destination

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 6 .1
2.3 Examples of use of shift registers
1-bit SEQUENCE RECOGNIZER

in
... 1001 ... D Q D Q D Q D Q
_ _ _ _
Q Q Q Q

CK

out

11
 6 .1
2.3 Examples of use of shift registers
3-bit SEQUENCE RECOGNIZER
in1
0001 D Q D Q D Q D Q
_ _ _ _
Q Q Q Q

in2
0011 D Q D Q D Q D Q
_ _ _ _
Q Q Q Q

out
in3
1000 D Q D Q D Q D Q
_ _ _ _
Q Q Q Q

1026
CK
12
 6 .1
SUMMARY
1. Registers: store n-bit data. Fundamental computer components .
2. Shift registers: main types and application examples.

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6 .1

14
6 .2 COUNTERS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 6 .2
1. Counters
 Sequential circuit whose internal states encode the set {0, 1, 2, ··· , m-1} for some m. At each clock
pulse the internal state is incremented (or decremented). Algorithmic definition:
q <= (q + 1) mod m (or q <= (q - 1) mod m).
In particular:
 Cyclic sequence.
 Output state = Current internal state = Flip-flop state.
 Some types:
 Up counter. Example (m = 23): 000, 001, 010, 011, 100, 101, 110, 111, 000, 001, 010, ···
 Down counter. Example (m = 23): 111, 110, 101, 100, 011, 010, 001, 000, 111, 110, 101, ···
 BCD up counter (m = 10): 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001,
0000, 0001, ···
 Gray counter. Example (m = 23): 000, 010, 110, 100, 101, 111, 011, 001, 000, 010, 110, ···
 Bidirectional counters (up/down).
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 6 .2
1. Counters

Counter structure. If m is an n-bit number, then an m-state up counter consists of

 an n-bit register,
 a mod m adder that computes (q + cyIN) mod m.
Comment: cyIN can be used as an EN (Enable) signal (EN = 1: count, EN = 0: don’t count).

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 6 .2
1. Counters
If m = 2n then q = (q + cyIN ) mod m is computed by the following circuit

Each HA (Half Adder) is a 1-bit adder with one operand instead of two. It computes
qi = qi  cyi , cyi+1 = qi · cyi .

Comment: cyOUT could be used to enable another counter so as to generate a 2n-bit

counter (22n = m2 states) with two n-bit counters.

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 6 .2
1. Counters
Example: 3-bit up counter.

Equations of the combinational circuit (q+1 mod 8):

q0 = q0  1 = NOT(q0),
q1 = q1  cy1 = q1  q0,
q2 = q2  cy2 = q2  q1· cy1 = q2  q1· q0.

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 6 .2
1. Counters: examples of control and state signals
 Reset : asynchronous reset.
 OE (Output Enable): when non active, outputs are in high impedance.
 TC (Terminal Count): TC = 1 when q = m-1. Used to connect counters in series.

Comment: if m = 2n, TC = cyOUT.

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 6 .2
1. Counters: examples of control and state signals
 Reset : asynchronous reset.
 OE (Output Enable): when non active, outputs are in high impedance.
 TC (Terminal Count): TC = 1 when q = m-1. Used to connect counters in series.

Comment: if m = 2n, TC = cyOUT.

Example: 3-bit up counter

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 6 .2
Question

Consider a circuit made up of two 4-bit up counters with enable input EN

and terminal count output TC. Check the correct assertion:

o It counts from 0 to 31
o It counts from 0 to 63
o It counts from 0 to 127
o It counts from 0 to 255

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 6 .2
2. Bidirectional counters
 Up counter or Down counter according to the value of U/D (0: Up, 1: Down)

U/D=1
000

U/D=1
U/D=0
001
U/D=1 U/D=0
010
U/D=1 U/D=0
…
U/D=1 U/D=0 Reset
111 𝑈/𝐷 n-bit counter
CK
U/D=0
𝑞𝑛−1 𝑞𝑛−2 …… 𝑞1 𝑞0 23
 6 .2
3. Parallel load
 Synchronous load when Load = 1.

𝑖𝑛𝑛−1 𝑖𝑛𝑛−2 …… 𝑖𝑛1 𝑖𝑛0

Reset
Load n-bit counter
CK
....
𝑞𝑛−1 𝑞𝑛−2 …… 𝑞1 𝑞0

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 6 .2
3. Parallel load
 Reset: asynchronous or synchronous

𝑖𝑛𝑛−1 𝑖𝑛𝑛−2 …… 𝑖𝑛1 𝑖𝑛0 Gnd

Reset Reset
Load
n-bit counter TC Load n-bit counter TC
𝑂𝐸 𝑂𝐸
CK CK
.... ....
𝑞𝑛−1 𝑞𝑛−2 …… 𝑞1 𝑞0 𝑞𝑛−1 𝑞𝑛−2 …… 𝑞1 𝑞0

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 6 .2
4. Most common applications
1. Counting of time intervals (timers)
2. Counting some events.
3. Frequency dividers.
4. Sequence generators.

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 6 .2
4. Most common applications
1. Timers.
Design a circuit that generates z=1 every 5 seconds.

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 6 .2
4. Most common applications
2. Counting of events.
Design a circuit that counts the number of 1’s in a synchronized input sequence.
Example:

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 6 .2
4. Most common applications
3. Frequency divider
Design a circuit that generates a signal whose frequency is half the value of the
frequency of the incoming signal:

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 6 .2
Question

Consider a 4-bit up counter with terminal count output TC. The frequency of CK1 is equal to
256KHz. What is the frequency of CK2 = TC?

o 16 Hz. Reset
o 1 KHz. CK1 > 4-bit counter TC (CK2)

o 128 KHz
o None of the preceding q0 q1 q2 q3

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 6 .2
4. Most common applications
4. Sequence generator:
a) Design a circuit that generates 10010101
b) Design a circuit that generates 100101

q out q out
0 1 0 1
1 0 1 0
2 0 2 0
3 1 3 1
4 0 4 0
5 1 5 1
6 0
7 1
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 6 .2
SUMMARY
 Definition of a particular type of sequential circuit: counters.
 Different types of counters.
 Examples of applications.

32
6 .3 MEMORIES
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 6 .3
1. Memories
 Sequential modules able to store a large number of data.

 Equivalent to a set of registers that can be individually accessed either to write new data or to
read the stored data.

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 6 .3
1. Memories Word lines

Bit
lines
0

Address decoder
Address Bus a1 1

a0
2
to
every
cell
3

Read/Write circuitry R/W

d5 d4 d3 d2 d1 d0
Data Bus
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 6 .3
1. Memory types

Memories

Volatile Non-volatile

Read/Write under
Read/Write Read only
special conditions

DRAM SRAM EPROM flash mask prog. OTP ROM

ROM
EEPROM

36
 6 .3
1. Memory types

37
 6 .3
2. Random Access Memories (RAM)

Bit line
 Volatile, Read and Write
 Static RAM’s (SRAM) R/W
 Dynamic RAM’s (DRAM) D Q
Word lines EN Q SRAM cell

Bit
lines
0
Word line
Address decoder
Address Bus

a1 1

Bit line
a0
2
to
DRAM cell
every
cell
3

Read/Write circuitry R/W

Word line
d5 d4 d3 d2 d1 d0
Data Bus 38
 6 .3
2.1 Static RAM (SRAM)

Bit line
Word lines

Bit
lines
R/W
0
D Q R/W:
Address decoder

EN Q Read (R/W = 1): Internal cell to Data Bus.

Address Bus

a1 1

a0 Write (R/W=0): Data Bus to internal cell.

2
to
every
cell
3 Word line
Read/Write circuitry R/W

d5 d4 d3 d2 d1 d0
Data Bus

 Up to 64 Mbits per chip (≠ memory bank).

 Read time:  10 ··· 100ns (size dependent).
 Power consumption: smaller than DRAM (frequency dependent).
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 6 .3
2.2 Dynamic RAM’s (DRAM)

Bit line
Bit line
Pre-charge +
comparison
Read/Write circuitry + refresh R/W
R/W
Word line

Bus de datos

di

 Refresh cycles.
 Destructive read.
 Up to 2 Gbits per memory chip (≠ memory bank).
 Slower than SRAM (refresh, precharge).
 Generally higher power consumption then DRAM.
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 6 .3
3. Read Only Memories (ROM)
 See lesson 1.3 (week 1)
 Mask programmable: predefined at manufacturing level; One Time Programmable (OTP): user
defined (field programmable).
Word lines

Bit lines
0

Address decoder
Address Bus a1 1

a0
2

Read circuitry R

d5 d4 d3 d2 d1 d0
Data Bus 41
 6 .3
4. Programmable ROM (PROM)
Write operation: particular conditions (voltages, internal configuration). Basic cell: floating
gate transistor.
 EPROM (Erasable Programmable ROM)
 Erase: UV exposition (removed from the board).
 Programming: external device (programmer).

 EEPROM (Electrically Erasable Programmable ROM)

 Erase: high voltage, selectively (1 byte at a time, on board).
 Programming circuits: within the chip.

 Flash memories
 EEPROM type, better performance (block operations instead of 1 byte at a time).
 Programming circuits: within the chip.
 Typical applications: pen drives, memory cards , solid state drives, ···
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 6 .3
Question

What memory type(s) are non-volatile and can be written thousands of times?
 SRAM
 DRAM
 OTP ROM
 EPROM
 Flash
 None of the preceding

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 6 .3
5. Memory bank

EXAMPLE
Memory specification: 1,024 words, 8 bits per word.
Available components: SRAM chips storing 256 words, 4 bits per word.

R/W ME R/W ME

1.024 x 8 256 x 4
OE A D OE A D
(10) (8) (8) (4)

44
 6 .3
5. Memory bank
EXAMPLE
Memory specification: 1,024 words, 8 bits per word.
Available components: SRAM chips storing 256 words, 4 bits per word.
bits
3 2 1 0
a9 a8 a7 a6 a5 a4 a3 a 2 a1 a0
MEMORY MAPPING 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1
… … Chip 1 R/W ME
0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 1
Chip 2
address
… … 256 x 4
0 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 OE A D
1 0 0 0 0 0 0 0 0 1
… …
Chip 3 (8) (4)

1 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 1
… …
Chip 4
1 1 1 1 1 1 1 1 1 1

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 6 .3
5. Memory bank
EXAMPLE
Memory specification: 1,024 words, 8 bits per word.
Available components: SRAM chips storing 256 words, 4 bits per word.
R/W
ME

Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 Chip 7 Chip 8

d7d6d5d4 d3d2d1d0

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 6 .3
5. Memory bank
EXAMPLE
Memory specification: 1,024 words, 8 bits per word.
Available components: SRAM chips storing 256 words, 4 bits per word.

Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Chip 6 Chip 7 Chip 8

d7d6d5d4 d3d2d1d0
47
 6 .3
Question 1

How many 256-word, 4 bits per word, memory blocks are necessary to implement a 1024-word, 4
bits per word, memory bank?
o 2
o 4
o 8
o 16

48
 6 .3
Question 2

How many 256-word, 4 bits per word, memory blocks are necessary to implement a 256-word, 64
bits per word, memory bank?
o 2
o 4
o 8
o 16

49
 6 .3
SUMMARY
 Main memory characteristics: volatility, storage permanence, maximum number of
write cycles.
 Memory organization: words and addresses.
 Memory types: SRAM, DRAM, ROM, EPROM, EEPROM and flash.
 An example of memory bank.

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