This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2019.2915814, IEEE
Transactions on Circuits and Systems II: Express Briefs
1

A New High Drive Class-AB FVF Based Second

Generation Voltage Conveyor
G. Barile Student Member, IEEE, G. Ferri, Senior Member, IEEE, L. Safari, V. Stornelli, Senior Member, IEEE

Abstract— A new low-voltage low-power class-AB

second generation voltage conveyor (VCII) is presented. The 𝑖𝑥 = ±𝛽𝑖𝑦 , 𝑉𝑧 = α𝑉𝑥 , 𝑉𝑦 = 0 (1)
proposed circuit is based on an improved class-AB flipped voltage
follower (FVF) designed by adding a simple negative feedback
loop to the conventional class-AB circuit. This modification
where VCII+ and VCII- are identified by +β and –β
ensures high current drive capability of at least 2mA for both respectively (where β should be close to 1). Ideally also α is
falling and rising edges of input signal along with very low 2mΩ unitary. There are three main features in voltage conveyors that
output impedance and high accuracy. Benefiting from the new can be advantageously used. First, Y input node is suitable for
class-AB FVF, the proposed VCII features a very simple current summing. Second, it is easy to design both a positive
implementation, extremely low impedance at Y and Z terminals and a negative gain between Y and X nodes. Finally, it has a
(2mΩ), high impedance at X terminal (370kΩ) and high accuracy low impedance voltage output port which is very useful in
in current and voltage conveying (99% and 98% respectively). applications requiring voltage output so that an extra output
Moreover, it exhibits current drive capability 117.6 times larger
buffer is not needed as in CCIIs. The most interesting feature of
than its bias current (17μA). The circuit occupies 381.5µm*197µm
area. The application of the proposed VCII as a voltage integrator
VCII, however, is that the impedance at Y terminal is very low
is also presented. Simulation results using PSpice and 0.35μm (ideally zero) which makes VCII ideal for both current input
CMOS technology with ±1.65V supply voltage are provided to and voltage input applications. In fact, due to very low
demonstrate the presented theory. A comparison with the impedance at Y terminal, it can be assumed at ground.
literature is also provided. Therefore, voltage signals connected to Y terminal through a
resistor are converted to a proportional current signal for further
Index Terms— Current Conveyor, Voltage Conveyor, processing. The current at Y terminal is transferred to the high
Integrated circuits, CMOS. impedance (ideally infinite) X terminal where it is converted to
a proportional voltage by the load connected to this terminal
I. INTRODUCTION and finally, the voltage produced at X terminal is transferred to
the Z terminal which is a low impedance voltage output port.
Since the introduction of current conveyors in 1968 [1], they Some papers based on VCII have presented its applications as
filters, gyrators and oscillators [3-5]. Recently, in [6-8], its
have been conceived to replace operational amplifiers (Op- applications in realizing analog signal processing circuits such
Amps) in some applications. Generally, in comparison to Op- as inverting and non-inverting voltage amplifiers, current to
Amp based circuits, those employing current conveyors benefit voltage converter, differentiator and integrator and readout
from current mode approach in terms of better frequency circuits are reported. In [6] it is shown that the circuits based
performance and simpler circuitry. Among the various types of on VCII show high frequency performance. In addition, as VCII
current conveyors, the second generation current conveyor has a low impedance voltage output port, extra voltage buffer is
(CCII)[2] is the most widely used active building block. Despite not required; therefore, it is preferable for voltage output
many benefits, CCIIs have limitations in those applications applications. These features make VCII a suitable candidate to
requiring a voltage output. In these cases, due to the lack of a replace CCII in such applications. Although there has been an
low impedance voltage output port in CCII, an extra voltage urgent need for low power circuits, a survey in the previously
buffer is needed, resulting in higher power consumption and reported VCII implementations [6-8] shows that they all
chip area. In 2001 [3], the idea of voltage conveyors (VCs) was operate in class-A. The trade-off between power consumption
introduced as the dual circuit of current conveyor (CC). and transient response in circuits operating in class A makes
Compared to CCs, a VC is more flexible and has a low them inappropriate for low power design, while circuits
impedance voltage output port. Fig.1 shows the internal operating in class-AB are characterized by low quiescent
structure of the second-generation voltage conveyor (VCII) current and high current drive capability [9-13]. The class-AB
which is the dual circuit of the second generation current circuits are biased with low current and have low power
conveyor (CCII). It consists of a current buffer between Y and consumption, but to preserve good transient response, they
X terminals and a voltage buffer between X and Z terminals. provide load current much larger than bias current for large
Unlike the CCII, Y terminal of a VCII is a low impedance input signals. This feature makes them highly suitable for low-
current input port, X is a high impedance current output port power analog design. To meet the requirements of low power
and Z is low impedance voltage output port. The relationship consumption, high drive capability and good transient
between port voltages and currents are expressed: performance, in this paper a new VCII operating in class AB is
This manuscript is resubmitted for review on March 20th, 2019. presented.
The authors are with the DIIIE, University of L'Aquila, Italy (emails:
[email protected], [email protected], [email protected],
[email protected]).

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[9,12], that can deliver load currents much larger than the bias
current. For example, in Fig.2-c, as the current at M1 is not
biased by a constant current source, it can provide a load current
much larger than its bias current. Unfortunately, in these
circuits, to deliver large currents, feedback loop is broken by
setting off the lower transistor M2, therefore, current drive
capability is achieved at the expense of increased output
(a) (b)
impedance which causes asymmetry and distortion. In other
Figure 1. VCII a) Internal structure b) Symbol words, for large load currents when M2 is turned off, the
buffering action is performed by common drain transistor M1
It is based on the modification of the known flipped voltage with high output impedance of 1/gm1. As a result, each of the
follower (FVF), performed by adding an extra local negative positive and negative parts of the output signal experience two
feedback loop consisting of only two transistors and two current different output impedances.
sources. As a result, a low output impedance is ensured for both
rising and falling edges of input signal. The proposed VCII is
composed of two class AB FVF circuits, one operating as
current buffer between its Y and X terminals and the other as a
voltage buffer between X and Z terminals. This ensures very
low impedances at Y and Z terminals, high impedance at X
terminal, current drive capability much larger than bias current,
high slew-rate, excellent transient performance, good linearity,
low power consumption and simple circuitry. As an application
example, the proposed VCII is here used to implement a high- a) b) c)
performance voltage integrator. The organization of this paper Figure 2. a) The FVF [13], b) Class AB FVF circuit proposed in [9],
is as follows. In Section II the proposed class AB FVF and VCII c) Class AB FVF circuit proposed in [12]
are presented. The simulation results are given in Section III,
where also a comparative analysis with other VCIIs presented B- The Proposed Class AB FVF
in the literature has been done. Finally, Section IV concludes
the paper. The proposed class-AB FVF circuit is shown in Fig.3. It is
based on the topology reported in Fig.2-c. Transistors M5-M6
II. THE PROPOSED CLASS-AB VCII are added so that, along with M1, establish a local negative
A- Overview on Conventional FVF Circuits feedback loop. The combination of M1, M5-M6 operate as a
super transistor and with a proper design, frequency
The conventional FVF circuit is shown in Fig.2-a [13]. In this compensation is not required for the local negative feedback
circuit, the input signal, Vin, applied to the gate of M1, is loop [14]. For low value load currents where the FVF negative
transferred to its source which is used as output terminal. The feedback loop formed by M2 -M4 is active, the output impedance
low output impedance is provided by means of negative is reduced by the added local negative feedback loop of M1, M5
feedback loop established by M2. In this circuit, M1 current is -M6 transistors and the FVF negative feedback loop formed
constant and equal to IB, while the load current is provided by with M2 -M4 transistors. A routing small signal analysis gives
changing M2 current. The operation can be divided in two the output resistance as (with usual meaning of symbols):
phases: 𝑔𝑚3
(1 +
⁄𝑔𝑚4 )
1- For rising edge of Vin, current must be injected to load. In this 𝑟𝑜𝑢𝑡 ≈ (2A)
𝑔𝑚1 𝑔𝑚5 𝑔𝑚6 𝑔𝑚2 (𝑟𝑜5 ‖𝑟𝑜𝐼𝐵2 )(𝑟𝑜6 ‖𝑟𝑜𝐼𝐵3 )𝑅𝑒𝑞
case as the drain current of M1 (IDM1) is fixed and equal to IB,
the current in M2 is reduced and the load is charged by a current
equal to IL=IB-ID(M1). When M2 is turned off, the maximum where Req is the equivalent resistance seen at gate of M2
current equal to IB can be delivered to load. expressed as:
2-For falling edge of Vin, current must be sunk from load. As 𝑔𝑚4
𝑅𝑒𝑞 = 𝑟𝑜𝐼𝐵1 ‖ [𝑟𝑜4 (1 + )] (2B)
the current in M1 is constant, this action is performed by 𝑔𝑚3
increasing M2 current. In this case negative feedback loop
increases the voltage at node A, and therefore, the gate voltage and gmi and roi denote, respectively the transconductance and
of M2 is increased. The current of M2 is equal to IL+IB and is not output resistance of the related transistor and roIBi also indicates
limited by IB, it is determined by the available supply voltage. the output resistance of the related current source. Even for
In both cases, the circuit provides low output impedance. The large load currents, where M2 is off and the FVF negative
reason is that the negative feedback loop is active in both phases feedback loop does not operate, the added local negative
and reduces the output impedance. However, the conventional feedback loop provides low output impedance. In this case, the
FVF circuit of Fig.2-a suffers a main drawback. Although it can output resistance still exhibits low value of:
sink load currents much larger than bias current, it can only
deliver a load current equal to IB. Therefore, for currents larger 1
𝑟𝑜𝑢𝑡 ≈ (2C)
than IB, the output signal experiences large distortions. Fig.2-b 𝑔𝑚1 𝑔𝑚5 𝑔𝑚6 (𝑟𝑜5 ‖𝑟𝑜𝐼𝐵2 )(𝑟𝑜6 ‖𝑟𝑜𝐼𝐵3 )
and Fig.2-c show two FVF topologies, taken from the literature

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Consequently, the circuit ensures high current drive capability VDD

M12
along with low output impedance for both current source and M3 M15

sink phases. As circuit includes two negative feedback loops, IB2 IB3 IB4 IB5
M4 M13
the overall voltage gain between input and output is very close IB0 Vbias1 Vbias2
M1 M11
to unity. Even in case of sourcing large current signal when the M6 M10
FVF negative feedback loop established by M2–M4 does not M0 M5
M8
M9

operate, the circuit enjoys a voltage gain close to unity provided Y X Z

by the local negative feedback loop formed by M5-M6

M14
transistors. In this case the voltage gain can be expressed as: M2
IB1
M7
IB6

𝑣𝑜𝑢𝑡 1 Vss

𝛼= ≈ (3) Figure 4. Proposed FVF based VCII circuit

𝑣𝑖𝑛 1 + (𝑔𝑚5 𝑔𝑚6 (𝑟𝑜5 ‖𝑟𝑜𝐼𝐵2 )(𝑟𝑜6 ‖𝑟𝑜𝐼𝐵3 ))−1

In the proposed circuit of Fig.3, the current swing at M1-M4 and gmi and roi denote, respectively the transconductance and
transistors is large indicating large gate-source voltage for these output resistance of the related transistor and roIBi also indicates
the output resistance of the related current source. The bias
transistors. Therefore, the minimum required supply voltage is
voltages Vbias1 and Vbias2 can be set equal to Vdd -2Vsg.
determined by these transistors and we have:
The voltage swing at X and Z terminals are respectively:
𝑉𝐷𝐷 − 𝑉𝑆𝑆 = 𝑉𝐺𝑆𝑀3 + 𝑉𝐷𝑆𝑀4 + 𝑉𝐺𝑆𝑀2 (4)
𝑉𝑆𝑆 + 𝑉𝑑𝑠𝑀7 < 𝑉𝑥 < 𝑉𝐷𝐷 − 𝑉𝑑𝑠𝑀15 − 𝑉𝑔𝑠𝑀8 (7)
C- The Proposed Class AB VCII Circuit 𝑉𝑆𝑆 + 𝑉𝑑𝑠𝑀14 < 𝑉𝑧 < 𝑉𝐷𝐷 − 𝑉𝑑𝑠𝑀11 − 𝑉𝑔𝑠𝑀12 (8)

The proposed class AB VCII is shown in Fig.4. Its internal The high drive capability and low impedance are two main
structure composed of two class-AB FVF circuits. Transistors advantages of the proposed VCII, while realizing VCII using
M0-M8 operate as current buffer which is formed by connecting conventional FVF circuit of Fig.2-a, the current source
the input port of the proposed FVF to ground. Transistor M0 is capability is limited to IB. Using the conventional high drive
added to set the DC offset voltage at Y terminal equal to zero. FVF circuits of Fig.2-b and Fig.2-c results in high output
Transistors M9-M14 form the voltage buffer between X and Z impedance when circuit is sourcing large currents resulting in
terminals employing another class AB FVF circuit. The diode an unequal value of output impedance for positive and negative
connected transistor M8 operates as level shifter to compensate halves of input signal. Finally, using conventional source
the effect of gate-source voltage of M12 at Z port. The proposed follower circuit will result in a very high output impedance and
VCII provides very low impedance at Y and Z terminals and a also very low drive capability due to its class A operation. One
high current drive capability. The small signal expression for of the applications that can benefit from high current drive
its Y terminal resistance (ry) is expressed by Eq.2A. The capability of the proposed VCII is the voltage integrator, shown
resistance at X and Z terminals are expressed as: in Fig.5. The VCII can charge and discharge capacitor C with
load currents much larger than bias current. Therefore, a high
𝑟𝑜15 + 𝑟𝑜8 + 𝑔𝑚8 𝑟𝑜8 𝑟𝑜15 transient response is resulted under low power consumption. In
𝑟𝑋 = ‖𝑟𝑜7 ≈ 𝑟𝑜15 ‖𝑟𝑜7 (5)
1 + 𝑔𝑚8 𝑟𝑜8 this circuit, due to the low value impedance (ideally zero) at Y
𝑔𝑚12 terminal, the voltage at Y terminal can be assumed at zero.
1+ (6A) Therefore, IY can be found as IY= Vin/R. Since the output voltage
𝑔𝑚13
𝑟𝑍 ≈ ′ (at Z node) is almost equal to the X node voltage, it can be found
𝑔𝑚9 𝑔𝑚10 𝑔𝑚11 𝑔𝑚14 (𝑟𝑜9 ‖𝑟𝑜𝐼𝐵4 )(𝑟𝑜10 ‖𝑟𝑜𝐼𝐵5 )𝑅𝑒𝑞
starting from the current at Y terminal, that is transferred to X
where: terminal with a unity gain, and then calculate the voltage that it
𝑔𝑚13
𝑅′𝑒𝑞 = 𝑟𝑜𝐼𝐵6 || [𝑟𝑜13 (1 + )] (6B) produces:
𝑔𝑚12 1 𝑉𝑖𝑛
𝑉𝑜𝑢𝑡 ≈ 𝑉𝑋 = 𝐼𝑌 = (9)
𝑠𝐶 𝑠𝐶𝑅

III. SIMULATION RESULTS

The proposed class-AB VCII circuit is simulated using PSpice
and 0.35μm CMOS parameters and supply voltage of ±1.65V.
The transistor aspect ratios are reported in Table-I. Biasing
currents are set as follows: IB0, IB1, IB5 = 10µA; IB1, IB2, IB4, IB6
= 5µA; IB3 = 17µA. Biasing voltages Vbias1,2 are equal to 315mV.

Figure 3. The proposed Class-AB FVF circuit Figure 5. VCII based voltage integrator [6]

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Table-I The used transistors aspect ratios bandwidth of only 0.5dB and 20MHz respectively. The static
Transistor W(μm), L(µm) Transistor W(μm), L(µm) power dissipation, including the biasing circuitry needed to
M1, M11 120.05, 0.35 M5 3.15, 0.7 generate Vbias1,2, is only 320μW. Fig.12 shows the input and
M2, M7, M8 70, 0.7 M6, M10 20.3, 0.35 output signals of the VCII based voltage integrator (see Fig.5).
M3, M12, M15 120.05, 0.7 M9 31.5, 0.7 The value of R and C is 5kΩ and 100pF respectively. The
M4, M13 21, 0.35 M0 21, 4.2 simulation results show that the circuit can operate up to a
frequency of 1MHz. The estimated area of the chip is about
381.5µm*197µm. A summary of the proposed VCII performance
To test the transient response of the proposed class-AB VCII, a
parameters is given in Table-II, which also shows a comparison
step input of ±2mA is applied to the Y terminal. The X terminal
between the presented work and other ones offered by the
is connected to a load of 1Ω. The resulted current at X terminal
literature. As clearly visible, the class AB biasing allows to
is shown in Fig.6. The positive and negative slew rates of the
maintain great performances with a reduced static power
circuit are 510mA/μs and 860mA/μs respectively. From these
consumption. Moreover, thanks to the addition of the super
results, the proposed circuit is able to source and sink a high
transistor architecture, Y input as well as Z output impedances
current of 2mA to and from the load. Since the bias current of
are much lower than ones in other works. Definitively, the
transistors M7, M8 is only 17μA, the current drive capability of
proposed circuit shows very good characteristics.
the proposed FVF is at least 117.6 times larger than bias current. y
4 4 y
The circuit also enjoys low settling time of 200ns worse. To test
the current transfer linearity between Y and X terminals, a 2 2
sinusoidal input current with peak-to-peak value of 1mA is
applied to the Y node. The resulted output at X node is shown 0 0
in Fig. 7. The current signal at X node shows a low THD of
2 2
1.68% (-35.5dB) determined at 1MHz considering 10
harmonics. The simulation is repeated by connecting two 4 4
different loads of 1KΩ and 0.5KΩ to the X terminal. Results 4 . 5 500 500.05 .8 1000 1000.2
Time ( s) Time ( s)
are again showed in Fig.7. In these cases, the maximum current
Fig.6. Y to X current transient response to a step input: focus on
drive capability is slightly reduced due to the limitation caused
by the available supply voltages. The achieved THDs are 2.48% rising (left side) and falling (right side) edges
(-32.11dB) and 1.96% (-34.15dB) for 1KΩ and 0.5KΩ loads 0.8 y 1
500 1k
respectively. Then, to test the performance of the proposed
0.4
VCII in transferring voltage signals between X and Z terminals,
a step input of ±500mV is applied to X node. The Z node is 0.0
connected to a load of 5nF. The resulted output at Z node is
shown in Fig.8. The positive and negative slew rates are 0.4
0.56V/μs and 1.8V/μs respectively. The settling time is also 0.8
540ns. Linearity of the voltage buffering is also investigated. A 0.00 0.40 0.80 1.20 1.60 2.00
1V peak-to-peak sinusoidal voltage is applied to the X terminal Time ( s)
and the voltage at Z is measured. The analisys is performed Fig.7. Y to X current transient response to a sinusoidal input
600 V Vz 600 V Vz
connecting to the Z node 1MΩ, 10kΩ and 5kΩ resistor loads.
Results, depicted in Fig.9, show that there is a negligible 300 300
difference between traces at different load levels. The voltage
signals at Z terminal show a THD of 2.32% (-33dB), 2.95% (- 0 0
30.6dB) and 3.36% (-29.47dB) for each of the aforementioned
resistor value. The noise performance at X and Z nodes is 300 300
shown in Fig.10 which are achieved by terminating these nodes
600 600
to 5KΩ load. The impedances at Y, X and Z terminals are 1 000 1 001
4 5 500 505
estimated as 2mΩ, 370kΩ and 2mΩ respectively (at 1kHz Time ( s) Time ( s)
reference frequency). The frequency performance of voltage Fig.8. X to Z voltage transient response to a step input: focus on
transfer gain between X and Z terminals and current transfer rising (left side) and falling (right side) edges
gain between Y and X terminals are shown in Fig.11. For this 800 V Vz 5k
simulation, the X and Z terminals are connected to a load of V 10k Vz 1M
5pF||1kΩ. For current transferring between Y and X terminals, 400
the DC gain and -3dB bandwidth are -0.115dB and 22.4MHz, 0
respectively. For voltage transferring between X and Z
terminals, the DC gain and -3dB bandwidth are -0.068dB and 400
220MHz, respectively. Due to the presence of PMOS current
800
mirror in the current buffer section, the current transfer 0.0 0.5 1.0 1.5 2.0
bandwidth is smaller than the voltage transfer bandwidth. These Time ( s)
two parameters were also analysed at different PVT conditions, Fig.9. X to Z voltage transient response to a sinusoidal input
showing an overall maximum variation in the magnitude and

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5

1. 00 IV. CONCLUSIONS
oise X
1. 02 oise Z VCII can constitute a valid alternative to traditional analog
blocks. A new internal topology, at transistor level, has been
1. 04
here proposed. It takes the advantages of the use of flipped
1. 06 voltage followers to perform good characteristics as accuracy,
1. 08 impedance level, current drive capability. We believe that the
1. 10
proposed VCII can be used as building block in many analog
1. 03 1. 03 1. 0 applications.
Frequency (Hz)
Fig.10. Noise performance of the proposed VCII at a) X b) Z REFERENCES
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