EE479

Class Project Phase I

Opamp Supply-Independent Bias Current Generator

1. Introduction
This purpose of the final project is to design a state-of-the-art Low-Voltage, Low-Power,
High-Speed, High-Gain CMOS operational amplifier in the TSMC 180nm CMOS technology
process.

2. Required Performance
Table 1 summarizes the required performance for your designed final CMOS operational

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amplifier. It also indicates the priorities of performance parameters.

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Note: we want the CMOS operational amplifier to be compatible to P-Well, N-Well, or
twin-Well processes, all the pMOS body (substrate) terminals must be connected to VDD and all

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the nMOS body (substrate) terminals must be connected to VSS (ground).
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Parameter Description Required Achieved Value Priority
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Power Supply Voltage (Vdd) 2 2 V --------

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Temperature (Room) 25 25 °C --------

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TSMC 0.18um Process Corner Typical Typical ----- --------

Output Load Capacitor 1 1 pF --------
Opamp Open Loop DC Gain (Avo) > 100 dB 1
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Opamp Unity Gain-Bandwidth Product (UGBW) >1 GHz 1

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Phase Margin > 60 Degree 1

Settling Time (0.01% for 1V output step) < 10 ns 1
Input Voltage Range >1 V 2
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Supply Current Consumption (Idd) < 25 mA 2

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Power Consumption (Vdd X Idd) < 50 mW 2

Positive Slew Rate (SR+) >5 V/ns 3
Negative Slew Rate (SR-) >5 V/ns 3
Common Mode Rejection Ratio (at 100Hz) > 80 dB 3
Positive Power Supply Rejection Ratio (at 100Hz) > 60 dB 3
Negative Power Supply Rejection Ratio (at 100Hz) > 60 dB 3

Table 1: CMOS Operational Amplifier Performance and Priorities.

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 3. Phase I of the Project
(A) The first step is to find the basic nMOS size and pMOS size.
a. Input common mode range of the project opamp is 1Volt. The supply Vdd is 2V.
b. If we have 4xVdsat at the output. Thus the maximum Vdsat=250mV
c. Assume the Vdsat for each device is 200mV.
d. The opamp unity-gain-bandwidth is 1GHz range. Thus, we need bias current in
the mA’s range in the main devices and amplifier circuits.
e. We select (arbitrary) to have 0.1mA (100uA) as a unit reference current source.
Why not higher? Why not lower?
f. We select the channel length (L) for unit reference MOS device is 0.25um.
Why not higher? Why not lower?

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(B) Use a single pMOS and nMOS circuit similar to Figure 1, to find the size for unit
reference MOS devices that gives us Vdsat=200mV with 100uA dc bias current.

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Figure 1. Diode connected pMOS and nMOS

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 (C) Figure 2 shows how to generate a supply-independent the 100uA bias current. A
startup circuit is required.

The channel length is chosen to be 1um because we don’t have any cascade current
source. Higher channel length (L=1um) improves power supply rejection because the
Rds for devices will increase as L increases. Furthermore, the matching between
transistors will improve with larger device.

Visink and Visource voltage sources are only test voltage sources in order to monitor
the source and the sink output currents.

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Figure 2. Supply-Independent Bias Current Generator

(D) Figure 3 shows how to generate a four-level high-swing bias current generator. In this
circuit you use the minimum reference to create the four-level high-swing bias
generator

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Figure 3. Four-Level High-Swing (Low-Voltage) Bias Current Generator

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 Process Parameters Symbols nMOS pMOS Units
Minimum Drawn Channel Length Lmin 0.2 0.2 μm

Intrinsic Carrier Concenteration ni 1.45E+10 1.45E+10 cm-3

Permitivity of Silicon εSi 1.045E-12 1.045E-12 F/cm

Permitivity of Oxide εOX 3.5E-13 3.5E-13 F/cm

Electron Charge q 1.6E-19 1.6E-19 C

Thermal Voltage (@ Room Temp) Vth 25.85 25.85 mV

Substrate Doping Concentration NA, ND 8E+16 8E+16 cm-3

Gate Oxide thickness Tox 42 42 AO
Channel Mobility µN, µP 300 80 cm2 / V-s
Drain or Source Junction Depth XJ 0.16 0.16 μm

Drain or Source Lateral Diffusion Ld 0.01 0.015 μm

Drain Depletion-Layer Width Xd 0.00 0.00 μm

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Overlap Capacitance per unit Gate Width Cov 0.36 0.33 fF/um

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Nominal Threshold Voltage Vtn0, Vtp0 0.5 0.45 V

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Channel Length Modulation Parameters | d Xd / dVds | 0.028 0.023 um / V

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Drain or Source-Body bottom-side junction Capacitance Cjb0 1.0 1.1 f F/ um

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Drain or Source-Body bottom-side junction Capacitance Grading Coefficient mjb 0.36 0.45
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Drain or Source-Body side-wall junction Capacitance Cjsw0 0.2 0.25 f F/ um

Drain or Source-Body side-wall junction Capacitance Grading Coefficient mjsw 0.2 0.24

Drain or Source Junction Build-in potential ψ0 0.68 0.74 V

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Table 2: Hand-Calculation Parameters for 180nm TSMC CMOS Process.

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4. Project Phase I Assignment

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a. Use Hand calculation table for your hand analysis.

b. One or two people can work on the same project. If two people work in the same project,
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they will both receive the same grade.

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c. Using Figure 1, find the unit-reference MOS device sizes that generate overdrive-voltage
Vdsat=200mV both for pMOS and nMOS. Print the LTSpice operating point for the
devices.

d. Using Figure 2, design a supply-independent bias current generator. First do the hand-
calculation to find the value of external Resistor, Rext. Then, use LTspice to find-tune the
value of Rext value.

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 e. In Figure 2, you need to include the Start-up circuit.

f. Change the value of Vdd by 10% (2V±10%, from 1.8V to 2.2V) using 1mv-step, show
how much Isource and Isink change. Compute Sensitivity = (ΔI/I ) / (ΔVdd / Vdd).

g. Prove the operation of the startup circuit by LTspice simulation.

h. Connect the Supply-Independent Bias Current Generator to the four-level high-swing

bias current generator circuit.

i. Show your entire circuit schematic.

j. Create a table similar to Table 3 and show the performance of each device in your
complete bias generator circuit.

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W L m Ids Gm Ro Vgs Vds Vdsat Vdsat-Margin

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Device Type (um) (um) (#) (uA) (uA/V) (mV) (mV) (mV) (mV)
M1 nMOS

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M2 pMOS
M3 nMOS
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M4 nMOS
M5 pMOS
M6 nMOS
M7 nMOS
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M8 pMOS
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M9 nMOS
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Table 3: DC Bias and Operating condition of the devices

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