CMOS

1. Question 1. What Is Latch Up?

Answer :
Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a
parasitic silicon controlled rectifier, or SCR) is inadvertently created within a
circuit, causing a high amount of current to continuously flow through it once it is
accidentally triggered or turned on. Depending on the circuits involved, the
amount of current flow produced by this mechanism can be large enough to result
in permanent destruction of the device due to electrical overstress (EOS).
2. Question 2. Why Is Nand Gate Preferred Over Nor Gate For Fabrication?
Answer :
NAND is a better gate for design than NOR because at the transistor level the
mobility of electrons is normally three times that of holes compared to NOR and
thus the NAND is a faster gate.
Additionally, the gate-leakage in NAND structures is much lower. If you consider
t_phl and t_plh delays you will find that it is more symmetric in case of NAND ( the
delay profile), but for NOR, one delay is much higher than the other(obviously t_plh
is higher since the higher resistance p mos's are in series connection which again
increases the resistance).

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3. Question 3. What Is Noise Margin? Explain The Procedure To Determine
Noise Margin?
Answer :
The minimum amount of noise that can be allowed on the input stage for which
the output will not be effected.
4. Question 4. Explain Sizing Of The Inverter?
Answer :
In order to drive the desired load capacitance we have to increase the size (width)
of the inverters to get an optimized performance.

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5. Question 5. What Happens To Delay If You Increase Load Capacitance?
Answer :
delay increases.

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6. Question 6. What Happens To Delay If We Include A Resistance At The
Output Of A Cmos Circuit?
Answer :
Increases. (RC delay)
7. Question 7. What Are The Limitations In Increasing The Power Supply To
Reduce Delay?
Answer :
The delay can be reduced by increasing the power supply but if we do so the
heating effect comes because of excessive power, to compensate this we have to
increase the die size which is not practical.

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8. Question 8. For Cmos Logic, Give The Various Techniques You Know To
Minimize Power Consumption?
Answer :
Power dissipation=CV2f ,from this minimize the load capacitance, dc voltage and
the operating frequency.
9. Question 9. What Is Charge Sharing? Explain The Charge Sharing Problem
While Sampling Data From A Bus?
Answer :
In the serially connected NMOS logic the input capacitance of each gate shares
the charge with the load capacitance by which the logical levels drastically
mismatched than that of the desired once. To eliminate this load capacitance
must be very high compared to the input capacitance of the gates (approximately
10 times).

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10. Question 10. Why Do We Gradually Increase The Size Of Inverters In Buffer
Design? Why Not Give The Output Of A Circuit To One Large Inverter?
Answer :
Because it can not drive the output load straight away, so we gradually increase
the size to get an optimized performance.
11. Question 11. What Is Latch Up? Explain Latch Up With Cross Section Of A
Cmos Inverter. How Do You Avoid Latch Up?
Answer :
Latch-up is a condition in which the parasitic components give rise to the
Establishment of low resistance conducting path between VDD and VSS with
Disastrous results.

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12. Question 12. Give The Expression For Cmos Switching Power Dissipation?
Answer :
CV2

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13. Question 13. What Is Body Effect?
 Answer :
In general multiple MOS devices are made on a common substrate. As a result,
the substrate voltage of all devices is normally equal. However while connecting
the devices serially this may result in an increase in source-to-substrate voltage
as we proceed vertically along the series chain (Vsb1=0, Vsb2 0).Which results
Vth2>Vth1.
14. Question 14. Why Is The Substrate In Nmos Connected To Ground And In
Pmos To Vdd?
Answer :
we try to reverse bias not the channel and the substrate but we try to maintain the
drain,source junctions reverse biased with respect to the substrate so that we
dont loose our current into the substrate.
15. Question 15. What Is The Fundamental Difference Between A Mosfet And
Bjt?
Answer :
In MOSFET, current flow is either due to electrons(n-channel MOS) or due to
holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons
and holes. BJT is a current controlled device and MOSFET is a voltage controlled
device.

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16. Question 16. Which Transistor Has Higher Gain. Bjt Or Mos And Why?
Answer :
BJT has higher gain because it has higher transconductance.This is because the
current in BJT is exponentially dependent on input where as in MOSFET it is
square law.
17. Question 17. In Cmos Technology, In Digital Design, Why Do We Design The
Size Of Pmos To Be Higher Than The Nmos.what Determines The Size Of Pmos
Wrt Nmos. Though This Is A Simple Question Try To List All The Reasons
Possible?
Answer :
In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the
electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In
CMOS technology, nmos helps in pulling down the output to ground ann PMOS
helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the
same, then PMOS takes long time to charge up the output node. If we have a
larger PMOS than there will be more carriers to charge the node quickly and
overcome the slow nature of PMOS . Basically we do all this to get equal rise and
fall times for the output node.

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18. Question 18. Why Pmos And Nmos Are Sized Equally In A Transmission
Gates?
Answer :
In Transmission Gate, PMOS and NMOS aid each other rather competing with
each other. That's the reason why we need not size them like in CMOS. In CMOS
design we have NMOS and PMOS competing which is the reason we try to size
them proportional to their mobility.

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19. Question 19. All Of Us Know How An Inverter Works. What Happens When
The Pmos And Nmos Are Interchanged With One Another In An Inverter?
Answer :
I have seen similar Qs in some of the discussions. If the source & drain also
connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be
degraded 1 Similarly degraded 0;
20. Question 20. Give 5 Important Design Techniques You Would Follow When
Doing A Layout For Digital Circuits?
Answer :
o In digital design, decide the height of standard cells you want to
layout.It depends upon how big your transistors will be.Have reasonable
width for VDD and GND metal paths.Maintaining uniform Height for all
the cell is very important since this will help you use place route tool
easily and also incase you want to do manual connection of all the
blocks it saves on lot of area.
o Use one metal in one direction only, This does not apply for metal 1.
Say you are using metal 2 to do horizontal connections, then use metal 3
for vertical connections, metal4 for horizontal, metal 5 vertical etc...
o Place as many substrate contact as possible in the empty spaces of
the layout.
o Do not use poly over long distances as it has huge resistances unless
you have no other choice.
o Use fingered transistors as and when you feel necessary.
o Try maintaining symmetry in your design. Try to get the design in BIT
Sliced manner.
21. Question 21. What Is Metastability? When/why It Will Occur?different Ways
To Avoid This?
Answer :
Metastable state: A un-known state in between the two logical known states.This
will happen if the O/P cap is not allowed to charge/discharge fully to the required
logical levels.
One of the cases is: If there is a setup time violation, metastability will occur,To
avoid this, a series of FFs is used (normally 2 or 3) which will remove the
intermediate states.
22. Question 22. Let A And B Be Two Inputs Of The Nand Gate. Say Signal A
Arrives At The Nand Gate Later Than Signal B. To Optimize Delay Of The Two
Series Nmos Inputs A And B Which One Would You Place Near To The Output?
Answer :
The late coming signals are to be placed closer to the output node ie A should go
to the nmos that is closer to the output.