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DRV8847
SLVSE65A – JULY 2018 – REVISED AUGUST 2018

DRV8847 Dual H-Bridge Motor Driver

1 Features 3 Description
1• Dual H-Bridge Motor Driver The DRV8847 device is a dual H-bridge motor driver
for industrial applications, home appliances, ePOS
– Single or Dual Brushed DC Motors printers, and other mechatronic applications. This
– One Bipolar Stepper Motor device can be used for driving two DC motors, a
– Solenoid Loads bipolar stepper motor, or other loads such as relays.
A simple PWM interface allows easy interface with
• 2.7-V to 18-V Operating Voltage Range
the controller. The DRV8847 device operates off a
• High Output Current per H-bridge single power supply and supports a wide input supply
– 1-A RMS Driver Current at TA = 25°C range from 2.7 to 18 V.
– 2-A RMS Driver Current in Parallel Mode at TA The output stage of the driver consists of N-channel
= 25°C power MOSFETs configured as two full H-bridges to
• Low On-State Resistance drive motor windings or four independent half bridges
(in independent bridge interface). A fixed off time
– 1000 mΩ RDS(ON) (HS + LS) at TA = 25°C controls the peak current in the bridge which can
• Multiple Control Interface Options drive a 1-A load (2-A in parallel mode with proper
– 4-Pin Interface heat sinking, at 25°C TA).
– 2-Pin Interface A low-power sleep mode is provided to achieve a low
– Parallel Bridge Interface quiescent current draw by shutting down much of the
internal circuitry. Additionally, a torque scalar is
– Independent Bridge Interface provided which dynamically scales the output current
• Current Regulation With 20-μs Fixed Off Time through a digital input pin. This feature lets the
• Torque Scalar for Scaling Output Current to 50% controller decrease the current required for lower
• Supports 1.8-V, 3.3-V, 5-V Logic Inputs power consumption.
• Low-Power Sleep Mode Internal protection functions are provided for
undervoltage-lockout, overcurrent protection on each
– 1.7-µA Sleep Mode Supply Current at VVM =
FET, short circuit protection, open-load detection, and
12-V, TA = 25°C overtemperature. Fault conditions are indicated by on
• I2C Device Variant Available (DRV8847S) the nFAULT pin. The I2C device variant (DRV8847S)
– Detailed Diagnostics on I2C Registers has detailed diagnostics.
– Multi-Slave Operation Support
Device Information(1)
– Supports Standard and Fast I2C Mode PART NUMBER PACKAGE BODY SIZE (NOM)
• Small Packages and Footprints HTSSOP (16) 5.00 mm × 4.40 mm
– 16 Pin TSSOP (No Thermal Pad) DRV8847 TSSOP (16) 5.00 mm × 4.40 mm
– 16 Pin HTSSOP PowerPAD™ Package WQFN (16) 3.00 mm × 3.00 mm
– 16 Pin WQFN Thermal Package DRV8847S TSSOP (16) 5.00 mm × 4.40 mm
• Built-In Protection Features (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– VM Undervoltage Lockout
– Overcurrent Protection Simplified Schematic
– Open Load Detection 2.7 to 18 V
– Thermal Shutdown
– Fault Condition Indication Pin (nFAULT) INx DRV8847
1A
nSLEEP Dual H-Bridge Driver
2 Applications
Controller nFAULT
• Refrigerator Damper and Ice Maker Stepper
TRQ
• Washers, Dryers and Dishwashers Current Regulation
MODE 1A
• Electronic Point-of-Sale (ePOS) Printers
Built-in Protection
• Stage Lighting Equipment
•
1
Miniature Circuit Breakers and Smart Meters

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.6 Register Map........................................................... 43
2 Applications ........................................................... 1 8 Application and Implementation ........................ 48
3 Description ............................................................. 1 8.1 Application Information............................................ 48
4 Revision History..................................................... 3 8.2 Typical Application ................................................. 48
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 54
9.1 Bulk Capacitance Sizing ......................................... 54
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6 10 Layout................................................................... 55
6.2 ESD Ratings.............................................................. 6 10.1 Layout Guidelines ................................................. 55
6.3 Recommended Operating Conditions....................... 6 10.2 Layout Example .................................................... 55
6.4 Thermal Information .................................................. 6 10.3 Thermal Considerations ........................................ 56
6.5 Electrical Characteristics........................................... 7 10.4 Power Dissipation ................................................. 56
6.6 I2C Timing Requirements ......................................... 8 11 Device and Documentation Support ................. 57
6.7 Typical Characteristics ............................................ 11 11.1 Documentation Support ........................................ 57
7 Detailed Description ............................................ 14 11.2 Receiving Notification of Documentation Updates 57
7.1 Overview ................................................................. 14 11.3 Community Resources.......................................... 57
7.2 Functional Block Diagram ....................................... 15 11.4 Trademarks ........................................................... 57
7.3 Feature Description................................................. 17 11.5 Electrostatic Discharge Caution ............................ 57
7.4 Device Functional Modes........................................ 39 11.6 Glossary ................................................................ 57
7.5 Programming........................................................... 41 12 Mechanical, Packaging, and Orderable
Information ........................................................... 57

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4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE REVISION NOTES

July 2018 * Initial release.

Changes from Original (July 2018) to Revision A Page

• Changed the data sheet status from Advance Information to Production Data ..................................................................... 1

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5 Pin Configuration and Functions

DRV8847 PW Package DRV8847 PWP PowerPAD™ Package

16-Pin TSSOP 16-Pin HTSSOP
Top View Top View

nSLEEP 1 16 IN1 nSLEEP 1 16 IN1

OUT1 2 15 IN2 OUT1 2 15 IN2

ISEN12 3 14 MODE ISEN12 3 14 MODE

OUT2 4 13 GND OUT2 4 13 GND

Thermal
OUT4 5 12 VM OUT4 5 Pad 12 VM

ISEN34 6 11 TRQ ISEN34 6 11 TRQ

OUT3 7 10 IN4 OUT3 7 10 IN4

nFAULT 8 9 IN3 nFAULT 8 9 IN3

Not to scale Not to scale

DRV8847 RTE Package DRV8847S PW Package

16-Pin WQFN With Exposed Thermal Pad 16-Pin TSSOP
Top View Top View
nSLEEP
OUT1

IN1

IN2

nSLEEP 1 16 IN1

OUT1 2 15 IN2
16

15

14

13

ISEN12 3 14 SDA

ISEN12 1 12 MODE OUT2 4 13 GND

OUT2 2 11 GND OUT4 5 12 VM

Thermal
OUT4 3 Pad 10 VM ISEN34 6 11 SCL

ISEN34 4 9 TRQ OUT3 7 10 IN4

5

nFAULT 8 9 IN3

Not to scale
OUT3

nFAULT

IN3

IN4

Not to scale

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Pin Functions
PIN
DRV8847 DRV8847S
TYPE (1) DESCRIPTION
NAME TSSOP
WQFN TSSOP
HTSSOP
Device ground. Recommended to connect the GND pin and device
GND 13 11 13 PWR
thermal pad (HTSSOP and WQFN packages) to ground
IN1 16 14 16 I Half-bridge input 1
IN2 15 13 15 I Half-bridge input 2
IN3 9 7 9 I Half-bridge input 3
IN4 10 8 10 I Half-bridge input 4
Full-bridge-12 sense. Connect this pin to the current sense resistor for full-
ISEN12 3 1 3 O bridge-12. Connect this pin to the GND pin if current regulation is not
required.
Full-bridge-34 sense. Connect this pin to the to current sense resistor for
ISEN34 6 4 6 O full-bridge-34. Connect this pin to the GND pin if current regulation is not
required.
MODE 14 12 — I Tri-state pin for selection of driver operating mode
Fault indication pin. This pin is pulled logic low with a fault condition. This
nFAULT 8 6 8 OD
open-drain output requires an external pullup resistor.
Sleep mode input. Set this pin to logic high to enable the device. Set this
nSLEEP 1 15 1 I
pin to logic low to go to low-power sleep mode
OUT1 2 16 2 O Half-bridge output 1
OUT2 4 2 4 O Half-bridge output 2
OUT3 7 5 7 O Half-bridge output 3
OUT4 5 3 5 O Half-bridge output 4
SCL — — 11 I I2C clock signal.
SDA — — 14 OD I2C data signal. The SDA pin requires a pullup resistor.
TRQ 11 9 — I Torque current scalar
Power supply. Connect the VM pin to the motor power supply. Bypass this
VM 12 10 12 PWR pin to ground with a VM-rated 0.1-µF and 10-μF (minimum) ceramic
capacitor.

(1) I = input, O = output, OD = open-drain output, PWR = power

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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Power supply pin voltage (VM) -0.3 20 V
Power supply voltage ramp rate (VM) 0 2 V/µs
Digital pin voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, nFAULT, SCL, SDA) -0.3 5.5 V
Phase node pin voltage (OUT1, OUT2, OUT3, OUT4) -0.7 VM + 0.6 V
Shunt amplifier input pin voltage (ISEN12, ISEN34) -0.6 0.6 V
Peak drive current (OUT1, OUT2, OUT3, OUT4), VVM <= 16.5 V Internally Limited A
Peak drive current (OUT1, OUT2, OUT3, OUT4), VVM > 16.5 V 0 4 A
Ambient temperature, TA -40 125 °C
Junction temperature, TJ -40 150 °C
Storage temperature, Tstg -65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±500
specification JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted). Typical limits apply for TA = 25°C and VVM = 12 V.
MIN NOM MAX UNIT
VVM Power supply voltage (VM) 2.7 18 V
VIN Logic input voltage (IN1, IN2, IN3, IN4, TRQ, nSLEEP, SCL, SDA) 0 5 V
IRMS Motor RMS current per bridge (OUT1, OUT2, OUT3, OUT4) 0 1 (1) A
fPWM PWM frequency (IN1, IN2, IN3, IN4) 0 250 (1) kHz
VOD Open drain pullup voltage (nFAULT) 0 5 V
IOD Open drain output current (nFAULT) 0 5 mA
TA Operating Ambient Temperature -40 85 °C
TJ Operating Junction Temperature -40 150 °C

(1) Power dissipation and thermal limits must be observed. Dependent on the package thermal performance.

6.4 Thermal Information

DRV8847, DRV8847S DRV8847 DRV8847
THERMAL METRIC (1) PW (TSSOP) PWP (HTSSOP) RTE (QFN) UNIT
16 PINS 16 PINS 16 PINS
Rθ JA Junction-to-ambient thermal resistance 107.9 46.5 46.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.5 40.1 47.5 °C/W
RθJB Junction-to-board thermal resistance 54.2 18.8 21.2 °C/W
ΨJT Junction-to-top characterization parameter 3.1 1.3 0.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Thermal Information (continued)

DRV8847, DRV8847S DRV8847 DRV8847
THERMAL METRIC (1) PW (TSSOP) PWP (HTSSOP) RTE (QFN) UNIT
16 PINS 16 PINS 16 PINS
ΨJB Junction-to-board characterization parameter 53.6 19.0 21.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 5.9 6.1 °C/W

6.5 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM)
VM = 2.7 V; nSLEEP = 1; INX = 0 2 2.5 mA
IVM VM operating supply current VM = 5 V; nSLEEP = 1; INX = 0 3 3.5 mA
VM = 12 V; nSLEEP = 1; INX = 0 3 3.5 mA
VM = 2.7 V; nSLEEP = 0; TA = 25°C 0.1 µA
VM = 2.7 V; nSLEEP = 0; TA = 85°C 0.5 µA
VM = 5 V; nSLEEP = 0; TA = 25°C 0.2 µA
IVMQ VM sleep mode current
VM = 5 V; nSLEEP = 0; TA = 85°C 1 µA
VM = 12 V; nSLEEP = 0; TA = 25°C 1.7 µA
VM = 12 V; nSLEEP = 0; TA = 85°C 2.5 µA
tSLEEP Sleep time nSLEEP = 0 to sleep mode 2 µs
tWAKE Wake-up time nSLEEP = 1 to output transition 1.5 ms
VM > UVLO to output transition
tON Turnon-time 1.5 ms
(nSLEEP = 1)
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, NSLEEP, TRQ, SCL, SDA)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.6 5.5 V
VHYS Input logic hysteresis nSLEEP pin 40 mV
VHYS Input logic hysteresis IN1, IN2, IN3, IN4, TRQ, SCL pins 100 mV
IIL Input logic low current VIN = 0 V -1 1 µA
IN1, IN2, IN3, IN4, TRQ, VIN = 5 V 1 35 µA
IIH Input logic high current
nSLEEP, VIN = 5 V 1 25 µA
tPD Propagation Delay INx edge to output 100 400 600 ns
TRI-LEVEL INPUTS (MODE)
VIL Tri-level input logic low voltage 0 0.6 V
VIZ Tri-level input hi-Z voltage 1.2 V
VIH Tri-level input logic high voltage 1.6 5.5 V
IIL Tri-level input logic low current VIN = 0 V 1 35 µA
IIH Tri-level input logic high current VIN = 5 V 1 35 µA
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = 5 mA 0.5 V
IOH Output logic high current VOD = 3.3 V -1 1 µA
OPEN-DRAIN OUTPUTS (SDA)
VOL Output logic low voltage IOD = 5 mA 0.5 V
IOH Output logic high current VOD = 3.3 V -1 1 µA
CB Capacitive load for each bus line 400 pF
DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)

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Electrical Characteristics (continued)

Over recommended operating conditions unless otherwise noted. Typical limits apply for TA = 25°C and VVM = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVM = 2.7 V; IOUT = 0.5 A; TA = 25°C 690 mΩ
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C 950 mΩ
VVM = 5 V; IOUT = 0.5 A; TA = 25°C 530 mΩ
RDS(ON)_HS High-side MOSFET on resistance
VVM = 5 V; IOUT = 0.5 A; TA = 85°C 740 mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 25°C 520 mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 85°C 700 mΩ
VVM = 2.7 V; IOUT = 0.5 A; TA = 25°C 570 mΩ
VVM = 2.7 V; IOUT = 0.5 A; TA = 85°C 900 mΩ
VVM = 5 V; IOUT = 0.5 A; TA = 25°C 460 mΩ
RDS(ON)_LS Low-side MOSFET on resistance
VVM = 5 V; IOUT = 0.5 A; TA = 85°C 690 mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 25°C 450 mΩ
VVM = 12 V; IOUT = 0.5 A; TA = 85°C 680 mΩ
IOFF Off-state leakage current VVM = 5 V; TJ = 25 °C; VOUT = 0 V -1 1 µA
tRISE Output rise time VVM = 12 V; IOUT = 0.5 A 150 ns
tFALL Output fall time VVM = 12 V, IOUT = 0.5 A 150 ns
tDEAD Output dead time Internal dead time 200 ns
VSD Body diode forward voltage IOUT = 0.5 A 1.1 V
PWM CURRENT CONTROL (ISEN12, SEN34)
Torque at 100% (TRQ = 0) 140 150 160 mV
VTRIP ISENxx trip voltage
Torque at 50% (TRQ = 1) 63.75 75 86.25 mV
tBLANK Current sense blanking time 1.8 µs
tOFF Current control constant off time 20 µs
PROTECTION CIRCUITS
Supply rising 2.7 V
VUVLO Supply undervoltage lockout
Supply falling 2.4 V
VUVLO_HYS Supply undervoltage hysteresis Rising to falling theshold 50 mV
tUVLO Supply undervoltage deglitch time VM falling; UVLO report 10 µs
(1)
IOCP Overcurrent protection trip point 2 A
VVM < 15 V 3 µs
tOCP Overcurrent protection deglitch time
VVM >= 15 V 1 µs
tRETRY Overcurrent protection retry time 1 ms
IOL_PU Open load pull-up current < 15 nF on OUTx Pin 200 µA
IOL_PD Open load pull-down current < 15 nF on OUTx Pin 230 µA
VOL_HS Open load detect threshold (high side) 2.3 V
VOL_LS Open load detect threshold (low side) 1.2 V
TTSD Thermal shutdown temperature 150 160 180 °C
THYS Thermal shutdown hysteresis 40 °C

(1) For VM > 16.5 V, the output current on OUTx must be limited to 4 A

6.6 I2C Timing Requirements

MIN NOM MAX UNIT
STANDARD MODE
fSCL SCL Clock frequency 0 100 kHz
Hold time (repeated) START condition. After this period, the first
tHD,STA 4 µs
clock pulse is generated
tLOW LOW period of the SCL clock 4.7 µs

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I2C Timing Requirements (continued)

MIN NOM MAX UNIT
tHIGH HIGH period of the SCL clock 4 µs
tSU,STA Setup time for a repeated START condition 4.7 µs
tHD,DAT Data hold time: For I2C bus devices 0 3.45 µs
tSU,DAT Data set-up time 250 ns
tR SDA and SCL rise time 1000 ns
tF SDA and SCL fall time 300 ns
tSU,STO Set-up time for STOP condition 4 µs
tBUF Bus free time between a STOP and START condition 4.7 µs
FAST MODE
fSCL SCL Clock frequency 0 400 kHz
Hold time (repeated) START condition. After this period, the first
tHD,STA 0.6 µs
clock pulse is generated
tLOW LOW period of the SCL clock 1.3 µs
tHIGH HIGH period of the SCL clock 0.6 µs
tSU,STA Setup time for a repeated START condition 0.6 µs
tHD,DAT Data hold time: For I2C bus devices 0 0.9 µs
tSU,DAT Data set-up time 250 ns
tR SDA and SCL rise time 300 ns
tF SDA and SCL fall time 300 ns
tSU,STO Set-up time for STOP condition 0.6 µs
tBUF Bus free time between a STOP and START condition 1.3 µs
tSP Pulse width of spikes to be supressed by input noise filter 50 ns

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xIN1

xIN2 tpd
tpd
tpd
xOUT1 Z Z

tpd

xOUT2 Z Z

90% 90%

10%
10%

trise tfall

Figure 1. Timing Diagram

STO STA STA STO

SDA tBUF

tr

SCL

tHD,STA
tf
tSU,STO
tHD,DAT tHIGH tSU,DAT tSU,STA
tLOW
tHD,STA

Figure 2. I2C Timing Diagram

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6.7 Typical Characteristics

5 4

4
3
Supply Current (mA)

Supply Current (mA)

3
2
2

VVM = 2.7 V
1 VVM = 5 V
1 TA = -40°C VVM = 12 V
TA = 25°C VVM = 15 V
TA = 85°C VVM = 18 V
0 0
2 4 6 8 10 12 14 16 18 -40 -20 0 20 40 60 80 100
Supply Voltage (V) D001
Temperature (°C) D002

Figure 3. Operating Supply Current (IVM) vs Supply Voltage Figure 4. Operating Supply Current (IVM) vs Ambient
(VVM) Temperature (TA)
5 7
VVM = 2.7 V
6 VVM = 5 V
4 VVM = 12 V
VVM = 15 V
5 VVM = 18 V
Sleep Current (PA)

Sleep Current (PA)

3
4

3
2

2
1 TA = -40°C
TA = 25°C 1
TA = 85°C
0 0
2 4 6 8 10 12 14 16 18 -40 -20 0 20 40 60 80 100
Supply Voltage (V) D003
Temperature (°C) D004

Figure 5. Sleep Mode Supply Current (IVMQ) vs Supply Figure 6. Sleep Mode Supply Current (IVMQ) vs Ambient
Voltage (VVM) Temperature (TA)

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Typical Characteristics (continued)

1 1
TA = -40°C
0.9 TA = 25°C 0.9
0.8 TA = 85°C 0.8
0.7 0.7
Resistance (:)

Resistance (:)
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3 VVM = 2.7 V
VVM = 5 V
0.2 0.2 VVM = 12 V
0.1 0.1 VVM = 15 V
VVM = 18 V
0 0
2 4 6 8 10 12 14 16 18 -40 -20 0 20 40 60 80 100
Supply Voltage (V) D005
Temperature (qC) D006

Figure 7. High Side On-State Resistance (RDS(ON)_HS) vs Figure 8. High Side On-State Resistance (RDS(ON)_HS) vs
Supply Voltage (VVM) Ambient Temperature (TA)
1 1
TA = -40°C
0.9 TA = 25°C 0.9
0.8 TA = 85°C 0.8
0.7 0.7
Resistance (:)

Resistance (:)

0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3 VVM = 2.7 V
VVM = 5 V
0.2 0.2 VVM = 12 V
0.1 0.1 VVM = 15 V
VVM = 18 V
0 0
2 4 6 8 10 12 14 16 18 -40 -20 0 20 40 60 80 100
Supply Voltage (V) D007
Temperature (qC) D008

Figure 9. Low Side On-State Resistance (RDS(ON)_LS) vs Figure 10. Low Side On-State Resistance (RDS(ON)_LS) vs
Supply Voltage (VVM) Ambient Temperature (TA)

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Typical Characteristics (continued)

225 250

Open Load Pull-Down Current (PA)

Open Load Pull-Up Current (PA)

225
200

200
175
175
150
150

125 TA = -40°C TA = -40°C

125
TA = 25°C TA = 25°C
TA = 85°C TA = 85°C
100 100
2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18
Supply Voltage (V) D009
Supply Voltage (V) D001

Figure 11. Open Load Pull-Up Current (IOL_PU) vs Supply Figure 12. Open Load Pull-Down Current (IOL_PD) vs Supply
Voltage (VVM) Voltage (VVM)
2.6 1.3
Open Load High-Side Threshold Voltage (V)

Open Load Low-Side Threshold Voltage (V)

2.4 1.2

2.2 1.1

2 1

1.8 0.9

1.6 0.8

TA = -40°C TA = -40°C
1.4 TA = 25°C 0.7 TA = 25°C
TA = 85°C TA = 85°C
1.2 0.6
2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 14 16 18
Supply Voltage (V) D001
Supply Voltage (V) D001

Figure 13. Open Load High-Side Threshold Voltage (VOL_HS) Figure 14. Open Load Low-Side Threshold Voltage (VOL_LS)
vs Supply Voltage (VVM) vs Supply Voltage (VVM)

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7 Detailed Description

7.1 Overview
The DRV8847 device is an integrated 2.7-V to 18-V dual motor driver for industrial brushed and stepper motor
applications. This driver can drive two DC motors, a bipolar stepper motor, or the solenoid loads. The device
integrates two H-bridges that use NMOS low-side and high-side drivers and current-sense regulation circuitry.
The DRV8847 device supports a high output current of 1-A RMS per H-bridge using low-RDS(ON) integrated
MOSFETs.
A simple PWM interface option allows easy interfacing to the H-bridge outputs. The interface options can be
configured using the MODE and IN3 pins in the DRV8847 device. The interface options can be configured
through a I2C interface in the I2C device variant (DRV8847S).
The current regulation uses a fixed off-time (tOFF) PWM scheme. The trip point for current regulation is controlled
by the value of the sense resistor and fixed internal VTRIP value.
A low-power sleep mode is included which lets the system save power when not driving the motor.
The DRV8847 device is available in three different packages:
• 16-pin TSSOP (no thermal pad)
• 16 pin HTSSOP (PowerPAD)
• 16 pin WQFN (thermal pad)
The I2C variant of the DRV8847 device is also available for a detailed diagnostics requirement and multi-slave
operation with multi-slave operation control over I2C bus.
The DRV8847S device variant is available in one package which is the 16-pin TSSOP (no thermal pad).
The DRV8847 device has a broad range of integrated protection features. These features include power supply
undervoltage lockout, open-load detection, overcurrent faults, and thermal shutdown.

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7.2 Functional Block Diagram

VM Charge Pump
VM Power
VM
0.1 µF bulk Internal
CVM2 CVM1 Reference
and
Regulators
OUT1

MODE
DC
Gate Stepper
Motor
Drive VM Motor
and
TRQ OCP

OUT2
nSLEEP

RSENSE12
(Optional)
ISENS12
IN1 ISEN
VM
Logic

IN2

OUT3

IN3

DC
IN4 Gate Motor
Drive VM
VEXT and
OCP
RnFAULT
Output OUT4
nFAULT

RSENSE34
ISENS34 (Optional)
ISEN
Overtemperature

GND PPAD

Figure 15. Block Diagram for DRV8847

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Functional Block Diagram (continued)

VM Charge Pump
VM Power
VM
0.1 µF bulk Internal
CVM2 CVM1 Reference
and
Regulators
AOUT1

nSLEEP

DC
Gate Stepper
IN1 Motor
Drive VM Motor
and
OCP

IN2
AOUT2

IN3
RSENSE12
(Optional)
ISENS12
ISEN
IN4 VM
VEXT Logic

RnFAULT

Output BOUT1
nFAULT

DC
Gate Motor
SCL Drive VM
VEXT and
I 2C OCP
Registers
RSDA
BOUT2
SDA

RSENSE34
ISENS34 (Optional)
ISEN
Overtemperature

GND PPAD

Figure 16. Block Diagram for DRV8847S

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7.3 Feature Description

Table 1 lists the recommended values of the external components for the gate driver.

Table 1. DRV8847 External Components

COMPONENT PIN 1 PIN 2 RECOMMENDED
CVM1 VM GND 10-µF (minimum) VM-rated ceramic capacitor
CVM2 VM GND 0.1-µF VM-rated ceramic capacitor
(1)
RnFAULT VEXT nFAULT >1 kΩ
RISEN12 ISEN12 GND Sense resistor, see the Typical Application for sizing
RISEN34 ISEN34 GND Sense resistor, see the Typical Application for sizing

(1) VEXT is not a pin on the DRV8847 device, but a pullup resistor on the VEXT external supply voltage is required for the open-drain
output, nFAULT.

7.3.1 PWM Motor Drivers

The DRV8847 device has two identical H-bridge motor drivers with current-control PWM circuitry. Figure 17
shows a block diagram of the circuitry.
The two H-bridges can also be used as four independent half-bridges depending upon the interface option. The
ISENxx pin can be only used together with two half-bridges.

VM

IN1
OUT1
IN2

Stepper
VM Motor
PWM Predrive

OUT2

ISEN12

±
RSENSE12

REF (VTRIP)

Figure 17. PWM Motor Driver Circuitry

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7.3.2 Bridge Operation

The full-bridge can operate in four different operating modes: forward, reverse, coast (fast decay), and brake
(slow decay) operation.

7.3.2.1 Forward Operation

This operating mode refers to the forward rotation of the motor such that the current flows from terminal A (OUT1
or OUT3) to terminal B (OUT2 or OUT4) as shown in Figure 18. In this mode, terminal A is connected to VM and
terminal B is connected to ground.

VM

A B

Figure 18. Forward Operation

7.3.2.2 Reverse Operation

This operating mode refers to the reverse rotation of the motor such that the current flows from terminal B (OUT2
or OUT4) to terminal A (OUT1 or OUT3) as shown in Figure 19. In this mode, terminal A is connected to ground
and terminal B is connected to VM.

VM

B
A

Figure 19. Reverse Operation

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7.3.2.3 Coast Operation (Fast Decay)

In this operating mode, all the FETs of the full-bridges are in the high impedance (Hi-Z) state. The motor also
goes to the Hi-Z state, and the motor starts coasting. This operating mode also helps to decay the motor current
faster and is therefore also referred to as a fast decay mode. If the motor was initially connected in forward
operation (current flows from terminal A to terminal B) and if the coast operation is applied, then, because of the
inductive nature of motor load, the current continues to flow in the same direction (A to B), and the anti-parallel
diodes of the alternate FETs starts conducting as shown in Figure 20. This flow of current through anti-parallel
diodes lets the current decrease rapidly because of the higher negative potential created by the supply voltage,
VM.

VM

A
B

Figure 20. Coast Operation (Fast Decay)

7.3.2.4 Brake Operation (Slow Decay)

This operating mode is realized by switching on both of the low-side FETs of the full-bridge as shown in
Figure 21. A current circulation path is provided when both low-side FETs are turned on. Due to this circulation
path, the current decays to ground using the resistance of the motor and of the low-side FET. Because this
current decay is less when compared to the coast operation because of the low potential difference, this mode is
also referred to the slow decay mode.

VM

A B

Figure 21. Brake Operation (Slow Decay)

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7.3.3 Bridge Control

The DRV8847 device can be configured in four different operating modes depending on user requirements. The
MODE and IN3 pins are used to configure the DRV8847 in one of the four different interfaces: 4-pin interface, 2-
pin interface, a parallel bridge interface, and the independent bridge interface. Mode selection is done using the
I2C registers in the DRV8847S device variant (see the Programming section). Table 2 lists the configurations to
select the operating mode of the bridges.

Table 2. Bridge Mode Selection (DRV8847 Hardware Device Variant)

nSLEEP MODE IN3 INTERFACE
0 X X Sleep mode
1 0 X 4-pin interface
1 1 0 2-pin interface
1 1 1 Parallel bridge interface
1 Z X Independent bridge interface

NOTE
The MODE pin is not latched during driver operation. Therefore, TI does not recommend
connecting this pin to a controller to use at any time.

7.3.3.1 4-Pin Interface

In the 4-pin interface, the DRV8847 device is configured to drive a stepper motor or two BDC motors with fully
functional modes. To configure 4-pin interface operation, connect the MODE pin to ground and use the IN1, IN2,
IN3, and IN4 pins to control the drivers. In this mode, the stepper or brushed DC motor can operate with all four
modes (forward, reverse, coast, and brake mode) and the stepper motor can operate in either full-stepping mode
or the non-circulating half-stepping mode. Sense resistors can be connected to the ISEN12 and ISEN34 pins for
independent current regulation in bridge-12 and bridge-34 respectively.
Use this interface option for the following loads:
• Stepper motor in full-stepping mode (with or without current regulation)
• Stepper motor in half-stepping mode (with or without current regulation)
• Single or dual BDC motor (with or without current regulation) with full functional BDC modes (forward,
reverse, brake, and coast mode)
Table 3 lists the configurations for 4-pin interface operation and Figure 22 shows the application diagram for 4-
pin interface operation.

Table 3. 4-Pin Interface (MODE = 0)

nSLEEP IN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 FUNCTION (DC MOTOR)
0 X X X X Z Z Z Z Sleep mode
1 0 0 Z Z Motor coast (fast decay)
1 0 1 L H Reverse direction
1 1 0 H L Forward direction
1 1 1 L L Motor brake (slow decay)
1 0 0 Z Z Motor coast (fast decay)
1 0 1 L H Reverse direction
1 1 0 H L Forward direction
1 1 1 L L Motor brake (slow decay)

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VM

OUT1

Gate DC
Stepper
Drive Motor
VM Motor
and
OCP

OUT2

IN1 RSENSE
(Optional)
ISEN12
IN2 ISEN

VM
IN3 Logic

Controller
IN4

OUT3

nSLEEP

Gate DC
Drive VM Motor
and
OCP

MODE
OUT4
GND

RSENSE
ISEN34 (Optional)
ISEN

Figure 22. 4-Pin Interface Operation

7.3.3.2 2-Pin Interface

In the 2-pin interface, the DRV8847 device is configured to drive a stepper motor or two BDC motors with lower
number of control inputs from microcontroller. To configure 2-pin interface operation, connect the MODE pin to
the external supply (3.3 V or 5 V), connect the IN3 pin to ground, and use the IN1 and IN2 pins to control the
driver. In this mode, the stepper or brushed DC motor operate in only two modes (forward mode and reverse
mode) i.e. only full-step operation is supported for stepper motor. This 2-pin interface is very useful for low GPIO
applications such as refrigerator dampers. Sense resistors can be connected to the ISEN12 and ISEN34 pins for
current regulation.
Use this interface option for the following loads:
• Stepper motor in full stepping mode (with or without current regulation)
• Single or dual BDC motor (with or without current regulation) with reduced functional BDC modes (forward
and reverse mode only)

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Table 4 lists the configurations for 2-pin interface operation and Figure 23 shows the application diagram for 2-
pin interface operation.

Table 4. 2-Pin Interface (MODE = 1, IN3 = 0)

nSLEEP IN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 FUNCTION (DC MOTOR)
0 X X X X Z Z Z Z Sleep mode
1 0 0 X L H Reverse direction
1 1 0 X H L Forward direction
1 0 0 X L H Reverse direction
1 1 0 X H L Forward direction

VM

OUT1
VEXT
MODE

Gate DC
Stepper
Drive Motor
VM Motor
and
IN3
OCP

GND
OUT2

IN4
'RQ¶W &DUH
RSENSE
(Optional)
ISEN12
ISEN

VM
Logic

OUT3

IN1

IN2 Gate DC
Controller Drive VM Motor
and
OCP

nSLEEP
OUT4

RSENSE
ISEN34 (Optional)
ISEN

Figure 23. 2-Pin Interface Operation

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NOTE
In this mode, two of the OUTx pins are always 'ON' if the device is in non-sleep state
(nSLEEP = HIGH). Therefore, to completely de-energize the motor-coils connected to
OUTx pins, the user has to pull-down nSLEEP pin.

7.3.3.3 Parallel Bridge Interface

In the parallel bridge interface, the DRV8847 device is configured to drive a higher current BDC motor by using
the driver in parallel to deliver twice the motor current. To go to parallel bridge interface operation, connect the
MODE and IN3 pins to the external supply (3.3 V or 5 V) and use the IN1 and IN2 pins to control the driver. This
mode can deliver the full functionality of the BDC motor control with all four modes (forward, reverse, coast, and
brake mode).
Use this interface option for the following loads:
• One high current BDC motor (with or without current regulation) with full functional BDC modes (forward,
reverse, brake, and coast mode)
• Two independent BDC motors operating together (with or without current regulation) with full functional BDC
modes (forward, reverse, brake, and coast mode)
Table 5 lists the configurations for parallel bridge interface operation, and Figure 24 shows the application
diagram for parallel bridge interface operation.

Table 5. Parallel Interface (MODE = 1, IN3 = 1)

nSLEEP IN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 FUNCTION (DC MOTOR)
0 X X X X Z Z Z Z Sleep mode
1 0 0 1 X Z Z Z Z Motor coast (fast decay)
1 0 1 1 X L H L H Reverse direction
1 1 0 1 X H L H L Forward direction
1 1 1 1 X L L L L Motor brake (slow decay)

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VM

VEXT

MODE OUT1

IN3 Gate
Drive VM
and
OCP

IN4
'RQ¶W &DUH OUT2

ISEN12
ISEN

VM
Logic

IN1
OUT3

IN2
Controller
Gate DC
Drive VM Motor
and
nSLEEP
OCP

OUT4

RSENSE
(Optional)
ISEN34
ISEN

Figure 24. Parallel Mode Operation

7.3.3.4 Independent Bridge Interface

In the independent bridge interface, the DRV8847 device is configured for independent half-bridge operation. To
configure independent bridge interface operation, leave the MODE pin unconnected (Hi-Z state) and use the IN1,
IN2, IN3, and IN4 pins to independently control the OUT1, OUT2, OUT3, and OUT4 pins respectively. Only two
output states of the OUTx pin can be controlled (either connected to VM or connected to GND). This mode is
used to drive independent loads such as relays and solenoids.
Use this interface option for the following loads:
• Relay or solenoid coils connected to the VM pin or ground without current regulation
• Single or dual BDC motor (with or without current regulation) with three functional BDC modes (forward,
reverse, and braking mode only)
• Stepper motor in full-stepping mode (with or without current regulation)
• Stepper motor in half-stepping mode (with or without current regulation) using brake mode

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Table 6 lists the configurations for independent bridge interface operation and Figure 25 shows the application
diagram for independent bridge interface operation.

Table 6. Independent Bridge Interface (MODE = Hi-Z)

nSLEEP IN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 FUNCTION (DC MOTOR)
0 X X X X Z Z Z Z Sleep mode
1 0 L OUT1 connected to GND
1 1 H OUT1 connected to VM
1 0 L OUT2 connected to GND
1 1 H OUT2 connected to VM
1 0 L OUT3 connected to GND
1 1 H OUT3 connected to VM
1 0 L OUT4 connected to GND
1 1 H OUT4 connected to VM

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VM

OUT1

Gate
Drive VM
and
OCP

IN1 OUT2

IN2

IN3 ISEN12
ISEN
Controller
IN4 VM
Logic

nSLEEP
OUT3

Gate
Drive VM
and
OCP
MODE
Not Connected
OUT4

ISEN34
ISEN

Figure 25. Independent Bridge Interface

7.3.4 Current Regulation

The current through the motor windings is regulated by a fixed off-time PWM current regulation circuit. With
brushed DC motors, current regulation can be used to limit the stall current (which is also the start-up current) of
the motor.
Current regulation works as follows: When an H-bridge is enabled, current rises through the winding at a rate
dependent on the supply voltage and inductance of the winding. If the current reaches the current trip threshold,
the bridge disables the current for a time tOFF before starting the next PWM cycle.

NOTE
Immediately after the current is enabled, the voltage on the ISENxx pin is ignored for a
period of time (tBLANK) before enabling the current sense circuitry. This blanking time also
sets the minimum on-time of the PWM cycle.

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The PWM trip current is set by a comparator which compares the voltage across a current sense resistor
connected to the ISENxx pin with a reference voltage. This reference voltage (VTRIP) is generated on-chip and
decides the current trip level.
The full-scale trip current in a winding is calculated as shown in Equation 1.
VTRIP
ITRIP Torque
RSENSExx

where
• ITRIP is the regulated current.
• VTRIP is the internally generated trip voltage.
• RSENSExx is the resistance of the sense resistor.
• Torque is the torque scalar, the value of which depends on the input on TRQ pin. TRQ = 100% for TRQ pin
connected to GND (DRV8847) or TRQ bit set to 0 (DRV8847S) and TRQ = 50% connected to VEXT (DRV8847)
or TRQ bit set to 1 (DRV8847S). (1)
For example, if the VTRIP voltage is 150 mV and the value of the sense resistor is 150 mΩ, the full-scale trip
current is 1 A (150 mV / (150 mΩ) = 1 A).

NOTE
If current control is not needed, connect the ISENxx pins directly to ground.

7.3.5 Current Recirculation and Decay Modes

During PWM current trip operation, the H-bridge is enabled to drive current through the motor winding until the
trip threshold of the current regulation is reached. After the trip current threshold is reached, the drive current is
interrupted, but, because of the inductive nature of the motor, current must continue to flow for some time. This
continuous flow of current is called recirculation current. A mixed decay allows a better current regulation by
optimizing the current ripple by using fast and slow decay.
Mixed decay is a combination of fast and slow decay modes. In fast decay mode, the anti-parallel diodes of the
opposite FETs are conducting on to let the current decay faster as shown in Figure 26 (see case 2). In slow
decay mode, winding current is recirculated by enabling both low-side FETs in the bridge (see case 3 in
Figure 26). Mixed decay starts with fast decay, then goes to slow decay. In the DRV8847 device, the mixed
decay ratio is 25% fast decay and 75% slow decay as shown in Figure 27.

VM

1 Drive Current

2 Fast Decay

3 Slow Decay

1
2

Figure 26. Decay Modes

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Fast Decay
ITRIP

Motor Slow Decay

Current

25% of tOFF

Time
tON tOFF
Mixed Decay (25% Fast Decay)

Figure 27. Mixed Decay

NOTE
The current regulation scheme uses a single sense resistor and hence always works for
two half bridges even when used in "Independent Bridge Interface". It is recommended
that current regulation not be used for loads using independent half bridges.

7.3.6 Torque Scalar

The torque scalar is used to dynamically adjust the output current through a digital input pin, TRQ. This torque
scalar decreases the trip reference value of the output current to 50% (whenever the TRQ pin is pulled-high).
Torque scalar can be used to scale the holding torque of the stepper motor. For the I2C device variant
(DRV8847S), this feature is implemented through an I2C register.
When the TRQ pin is pulled-low (or the TRQ bit is reset in the DRV8847S device variant), then trip current is
calculated using Equation 2.
Torque u VTRIP
ITRIP
RSENSExx
(2)
When the TRQ pin is pulled-high (or the TRQ bit is set in the DRV8847S device variant), then trip current is
calculated using Equation 3.
VTRIP
ITRIP 0.5
RSENSExx (3)

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7.3.7 Stepping Modes

The DRV8847 device is used to drive a stepper motor in full-stepping mode or non-circulating half-stepping mode
using the following bridge configurations:
• Full-stepping mode (with or without current regulation)
– Using 4-pin interface configuration
– Using 2-pin interface configuration
• Half-stepping mode (with or without current regulation)
– Using 4-pin interface configuration

7.3.7.1 Full-Stepping Mode (4-Pin Interface)

In full-stepping mode, the full-bridge operates in either of two modes (forward or reverse mode) with a phase shift
of 90° between the two windings.
In 4-pin interface, the PWM input is applied to the IN1, IN2, IN3, and IN4 pins as shown in Figure 28 and the
driver operates only in forward (FRW) and reverse (REV) mode.

90o
Phase

IN1

IN2

IN3

IN4

OUT12 FRW OUT12 FRW

OUT12
OUT12 REV OUT12 REV

OUT34 FRW OUT34 FRW

OUT34
OUT34 REV OUT34 REV

Time

Figure 28. Full-Stepping Mode Using 4-Pin Interface

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7.3.7.2 Full-Stepping Mode (2-Pin Interface)

In full-stepping using the 2-pin interface, the PWM input is only applied to the IN1 and IN2 pins, and the IN3 is
connected to ground (see the Figure 23 section). Figure 29 shows the full-stepping mode of stepper motor using
the 2-pin interface

90o
Phase

IN1

IN2

OUT12 FRW OUT12 FRW

OUT12
OUT12 REV OUT12 REV

OUT34 FRW OUT34 FRW

OUT34
OUT34 REV OUT34 REV

Time

Figure 29. Full-Stepping Mode Using 2-Pin Interface

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7.3.7.3 Half-Stepping Mode (With Non-Driving Fast Decay)

In half-stepping mode, the full-bridge operates in one of the three modes (forward, reverse, or coast mode) with a
phase shift of 45° between the two windings.
In 4-pin interface, the PWM input is connected to the IN1, IN2, IN3, and IN4 pins as shown in Figure 30, and the
driver operates in forward, reverse, and coast mode.

45o
Phase

IN1

IN2

IN3

IN4

COAST
COAST

COAST

COAST
COAST

OUT12 FRW OUT12 FRW

OUT12
OUT12 REV OUT12 REV

OUT34 FRW OUT34 FRW

OUT34
COAST
COAST

COAST

COAST
OUT34 REV OUT34 REV

Time

Figure 30. Half-Stepping Mode Using 4-Pin Interface (With Non-Driving Fast Decay)

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7.3.7.4 Half-Stepping Mode (With Non-Driving Slow Decay)

In this half-stepping mode, the non-driving state is slow decay (braking mode). Therefore, the full-bridge operates
in one of the three modes (forward, reverse, or brake mode) with a phase shift of 45° between the two windings.
In 4-pin interface, the PWM input is connected to the IN1, IN2, IN3, and IN4 pins as shown in Figure 31, and the
driver operates in forward, reverse, and brake mode.

45o
Phase
IN1

IN2

IN3

IN4

BRAKE
BRAKE

BRAKE

BRAKE
BRAKE

OUT12 FRW OUT12 FRW

OUT12
OUT12 REV OUT12 REV

OUT34 FRW OUT34 FRW

OUT34
BRAKE
BRAKE

BRAKE

BRAKE
OUT34 REV OUT34 REV

Time

Figure 31. Half-Stepping Mode Using 4-Pin Interface (With Non-Driving Slow Decay)

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7.3.8 Motor Driver Protection Circuits

The DRV8847 device is protected against VM undervoltage, overcurrent, open load, and over temperature
events.

7.3.8.1 Overcurrent Protection (OCP)

The DRV8847 is protected against overcurrent by overcurrent protection trip. The OCP circuit on each FET
disables the current flow through the FET by removing the gate drive. If this overcurrent detection continues for
longer than the OCP deglitch time (tOCP), all FETs in the H-bridge (or half-bridge in the independent interface) are
disabled and the nFAULT pin is driven low. The DRV8847 device stays disabled until the retry time tRETRY occurs
whereas the DRV8847S device has a programmable option for auto-retry or the latch mode.

7.3.8.1.1 OCP Automatic Retry (Hardware Device and Software Device (OCPR = 0b))
After an OCP event in this mode, the corresponding half-bridges, full-bridge, or both bridges (depending on the
MODE bits) are disabled and the nFAULT pin is driven low (see Table 13 and Table 14). The OCP and
corresponding OCPx bits are latched high in the I2C registers (see the Register Map section). Normal operation
resumes automatically (motor driver operation and the nFAULT pin is released) after the tRETRY time elapses as
shown in Figure 32. The OCP and OCPx bits remain latched until the tRETRY period expires.
Overshoot due to OCP
deglitch time (tOCP)
IOCP

Motor
Current

tOCP Time
tRETRY

Figure 32. OCP Operation

7.3.8.1.2 OCP Latch Mode (Software Device (OCPR = 1b))

OCP latch mode is only available in the DRV8847S device. After an OCP event, the corresponding half-bridges,
full-bridge, or both bridges (depending on the MODE bits) are disabled and the nFAULT pin is driven low. The
OCP and corresponding OCPx bits are latched high in the I2C registers (see the Register Map section). Normal
operation continues (motor driver operation and the nFAULT pin is released) when the OCP condition is removed
and a clear faults command is issued through the CLR_FLT bit.

NOTE
For supply voltage, VVM > 16.5-V, if the OUTx current (FET current) exceeds 4-A, then the
device operation is pushed beyond the safe operating area (SOA) of the device. User has
to ensure that the FET-current is below 4-A for device safe operation for supply voltage
above 16.5-V.

7.3.8.2 Thermal Shutdown (TSD)

If the die temperature exceeds thermal shutdown limits (TTSD), all FETs in the H-bridge are disabled and the
nFAULT pin is driven low. After the die temperature decreases to a value within the specified limits, normal
operation resumes automatically. The nFAULT pin is released after operation starts again.

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7.3.8.3 VM Undervoltage Lockout (VM_UVLO)

Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the
device is disabled, and all internal logic is reset. Operation continues when the VVM voltage rises above the
UVLO rising threshold as shown in Figure 33. The nFAULT pin is driven low during an undervoltage condition
and is released after operation starts again.

VUVLO (max) rising

VUVLO (min) rising

VUVLO (max) falling

VUVLO (min) falling VVM

DEVICE ON DEVICE OFF DEVICE ON

nFAULT
Time

Figure 33. VM UVLO Operation

7.3.8.4 Open Load Detection (OLD)

An open load detection feature is also implemented in this device. This diagnostic test runs at device power up or
when the DRV8847 device comes out from sleep mode (rising edge on the nSLEEP pin). The OLD diagnostic
test can run any time in the I2C variant device (DRV8847S) using the OLDOD (OLD On Demand) bit.
The OLD implementation is done on the full-bridge and the half-bridge. In the DRV8847 device, during an open-
load condition, the half-bridges, full-bridge, or both bridges (depending on the MODE pin) are always operating
and the nFAULT pin is pulled-low. The user must reset the power to release the nFAULT pin by doing the OLD
sequence again. Table 7 lists the different OLD scenarios for the DRV8847 device.
In the DRV8847S device, the user can program the full-bridge or half-bridge to be in the operating mode or the
Hi-Z state, whenever an open-load condition is detected by using the OLDBO (OLD Bridge Operation) bit.
Moreover, the nFAULT signaling on the OLD bit can be disabled using the OLDFD (OLD Fault Disable) bit. For
detailed I2C register settings, see the Register Map section. Table 8 lists the different OLD scenarios for the
DRV8847S device.

NOTE
For accurate OLD operation, the user must ensure that the motor is stationary (or current
in connected load becomes zero) before the open load on-demand command is executed.

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Table 7. Open Load Detection in DRV8847

BRIDGE
INTERFACE LOAD TYPE OLD nFAULT
OPERATION
Full-Bridge Connected NO YES NO
4-pin Half-Bridge Connected NO YES NO
2-pin Bridge Open YES YES YES
One Half-Bridge Open YES YES YES
Full-Bridge Connected NO YES NO
Half-Bridge Connected NO YES NO
Parallel bridge
Bridge Open YES YES YES
One Half-Bridge Open YES YES YES
Full-Bridge Connected NO YES NO
Independent Half-Bridge Connected NO YES NO
bridge Bridge Open YES YES YES
One Half-Bridge Open YES YES YES

Table 8. Open Load Detection in DRV8847S (Full-bridge-12)

BRIDGE OPERATION (1) OLD BITS
INTERFACE LOAD TYPE OLD nFAULT
OLDBO = 0b OLDBO = 1b OLD1 OLD2 OLD3 OLD4
Full-bridge connected NO YES YES NO 0b 0b X X
Half-bridge connected NO YES YES NO 0b 0b X X
4-pin
2-pin Bridge open YES YES NO YES 1b 1b X X
1b or 0b or
One half-bridge open YES YES NO YES X X
0b (2) 1b
Full-bridge connected NO YES YES NO 0b 0b X X
Half-bridge connected NO YES YES NO 0b 0b X X
Parallel bridge Bridge open YES YES NO YES 1b 1b X X
1b or 0b or
One half-Bridge Open YES YES NO YES X X
0b 1b
Full-Bridge Connected NO YES YES NO 0b 0b X X
Half-Bridge Connected NO YES YES NO 0b 0b X X
Independent
bridge Bridge Open YES YES NO YES 1b 1b X X
1b or 0b or
One Half-Bridge Open YES YES NO YES X X
0b 1b

(1) The operation of the bridge is subjected to the selected mode type:
(a) In 4-pin or 2-pin interface, the corresponding bridge is in the operating or Hi-Z state.
(b) In parallel bridge (BDC) interface, both bridges are in the operating or Hi-Z state.
(c) In independent bridge interface, the corresponding half-bridge is in the operating or Hi-Z state.
(2) Depending on which half-bridge is open, the corresponding bit in the I2C register is set.

The open-load detect sequence comprise of three detection states in which the driver ensures that any of the
load is either connected or open as follows.

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7.3.8.4.1 Full-Bridge Open Load Detection

As shown in Figure 34, during device wakeup, a constant current source pulls the OUT1 pin to the AVDD
(internal) fixed voltage which allows current flow from OUT1 to OUT2 terminal. The current drawn is completely
dependent on the motor resistance between OUT1 and OUT2. Depending on this current and the comparator
threshold voltage (VOL_HS and VOL_LS), the comparator output OL1_HS and OL2_LS are either set or reset which
determines the open load status. Table 9 shows the states of OL1_HS and OL2_LS for the open load detect.
This test executes before the tWAKE or tON time has elapsed. When an open load is detected, the nFAULT pin is
latched low until the device is power cycled. A similar implementation is done for the OUT3 and OUT4 pins.

Table 9. Open Load Detection for Full-Bridge Connection

OL1_HS OL2_LS OLD STATUS
0 0 NO OLD
0 1
1 0
1 1 OLD

AVDD VM
SW1_HS

± 12 kŸ
VOL_HS

OL1_HS +

IOL_PU
X
OUT1

OLD1 SW1_LS

±
IOL_PD
X
OL1_LS +
VOL_LS 15 kŸ
DC
Stepper
Motor
Motor

AVDD VM
SW2_HS

± 12 kŸ
VOL_HS
OL2_HS +

IOL_PU
X
OUT2

OLD2 SW2_LS

±
IOL_PD
X To OUT3 and OUT4

OL2_LS +
VOL_LS 15 kŸ

Figure 34. Open Load Detect Circuit for Full-Bridge Connection

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NOTE
AVDD voltage is the internal regulator voltage and is determined as min (VVM, 4.2 V).
Hence, for supply voltage (VVM) higher than 4.2 V, this voltage is fixed at 4.2 V else it is
equal to supply voltage ( VVM).

7.3.8.4.2 Load Connected to VM

For detection of the VM connected load, a constant current source pull-down the OUT1 node as shown in
Figure 35. This allows the current to flow from VM to OUT1 depending upon the value of load resistor (RL)
connected between OUT1 and VM. Higher current (not open load) will allow the OL1_LS comparator to set and
higher current resets the comparator output as shown in Table 10 for open load detection.

Table 10. Open Load Detection for VM Connected Load

OL1_LS OLD STATUS
0 NO OLD
1 OLD

VM

AVDD VM
SW1_HS

± 12 kŸ
VOL_HS RL
OL1_HS +
X
OLD1
IOL_PU

SW1_LS
X OUT1

±
IOL_PD
X
OL1_LS +
VOL_LS 15 kŸ

Figure 35. Open Load Detect Circuit for Load Connected to VM

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7.3.8.4.3 Load Connected to GND

For detection of the GND connected load, the OUT1 node is pulled-up by the internal current source and the
internal (4.2-V) fixed voltage as shown in Figure 36. This allows the current to flow from OUT1 to GND
depending upon the value of load resistor (RL) connected between OUT1 and GND. Higher current (not open
load) will allow the OL1_HS comparator to set and higher current resets the comparator output as shown in
Table 11.

Table 11. Open Load Detection for GND Connected

Load
OL1_HS OLD STATUS
0 NO OLD
1 OLD

AVDD VM
SW1_HS

± 12 kŸ
VOL_HS

OL1_HS +

IOL_PU
X
OUT1

OLD1 SW1_LS

±
IOL_PD
X X RL

OL1_LS +
VOL_LS 15 kŸ

Figure 36. Open Load Detect Circuit for Load Connected to GND

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7.4 Device Functional Modes

The DRV8847 device is active until the nSLEEP pin is pulled logic low. In sleep mode, the internal circuitry
(charge pump and regulators) is disabled and all internal FETs are disabled (Hi-Z state).
The device goes to operating mode automatically if the nSLEEP pin is pulled logic high. tWAKE must elapse
before the device is ready for inputs. Various functional modes are described in Table 12.
The DRV8847 device goes to a fault mode in the event of VM undervoltage (UVLO), overcurrent (OCP), open-
load detection (OLD), and thermal shutdown (TSD). The functionality of each fault depends on the type of fault
listed in Table 13 for the DRV8847 device and Table 14 for the DRV8847S device.

NOTE
The tSLEEP time must elapse before the device goes to sleep mode.

Table 12. Functional Modes

MODE CONDITION H-BRIDGE INTERNAL CIRCUITS
2.7 V < VVM < 18 V
Operating Operating Operating
nSLEEP pin = 1
2.7 V < VVM < 18 V
Sleep Disabled Disabled
nSLEEP pin = 0
Fault Any fault condition met Depends on fault Depends on fault

Table 13. Fault Support for DRV8847

INTERNAL
FAULT INTERFACE CONDITION REPORT H-BRIDGE RECOVERY
CIRCUITS
VM undervoltage Both H-bridges in Automatic:
All interfaces VM < VUVLO nFAULT Shutdown
(VM_UVLO) Hi-Z state VM > VUVLO

4-pin Corresponding H-
bridges in Hi-Z
2-pin state
Overcurrent Both H-bridges in Automatic:
Parallel bridge I > IOCP nFAULT Operating
(OCP) Hi-Z state tRETRY
Corresponding
Independent
half-bridges in Hi-
bridge
Z state
H-bridge in
4-pin Full-bridge open nFAULT
operating mode
Power cycle
Open load detect 2-pin Both H-bridges in
Full-bridges open nFAULT Operating /RESET: OUTx
(OLD) Parallel bridge operating mode
Connected
Independent Half-bridge in
Half-bridge open nFAULT
bridge operating mode
Thermal shutdown TJ > TTSD Both H-bridges in TJ < TTSD
All interfaces nFAULT Operating
(TSD) (min 150°C) Hi-Z state (THYS typ 40°C)

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Table 14. Fault Support for DRV8847S

INTERNAL
FAULT MODE CONDITION REPORT H-BRIDGE RECOVERY
CIRCUITS
VM undervoltage Both H-bridges in Automatic:
All interfaces VM < VUVLO nFAULT Shutdown
(VM_UVLO) Hi-Z state VM > VUVLO

4-pin Corresponding H-
bridges in Hi-Z
2-pin state
Overcurrent Both H-bridges in Automatic:
Parallel bridge I > IOCP nFAULT Operating
(OCP) Hi-Z state tRETRY
Corresponding
Independent
half-bridges in Hi-
bridge Interface
Z state
H-bridge in
4-pin Full-bridge open nFAULT operating or Hi-Z
state (1)

2-pin Both H-bridges in Power cycle /

Open load detect
Full-bridges open nFAULT operating or Hi-Z Operating RESET: OUTx
(OLD) Parallel bridge state Connected
Half-bridge in
Independent
Half-bridge open nFAULT operating or Hi-Z
bridge
state
Thermal shutdown TJ > TTSD Both H-bridges in TJ < TTSD
All interfaces nFAULT Operating
(TSD) (min 150°C) Hi-Z state (THYS typ 40°C)

(1) The state of the bridge in OLD is dependent on the OLDBO bit as listed in Table 19.

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7.5 Programming
This section applies only to the DRV8847S device (I2C variant).

7.5.1 I2C Communication

7.5.1.1 I2C Write

To write on the I2C bus, the master device sends a START condition on the bus with the address of the 7-bit
slave device. Also, the last bit (the R/W bit) is set to 0b, which signifies a write. After the slave sends the
acknowledge bit, the master device then sends the register address of the register to be written. The slave
device sends an acknowledge (ACK) signal again which notifies the master device that the slave device is ready.
After this process, the master device sends 8-bit write data and terminates the transmission with a STOP
condition.

START 7-bit Slave Address R/W=0 ACK 8-bit Register Address ACK 8-bit Data ACK STOP

Write to Memory

Figure 37. I2C Write Sequence

7.5.1.2 I2C Read

To read from a slave device, the master device must first communicate to the slave device which register will be
read from. This communication is done by the master starting the transmission similarly to the write process
which is by setting the address with the R/W bit equal to 0b (signifying a write). The master device then sends
the register address of the register to be read from. When the slave device acknowledges this register address,
the master device sends a START condition again, followed by the slave address with the R/W bit set to 1b
(signifying a read). After this process, the slave device acknowledges the read request and the master device
releases the SDA bus, but continues supplying the clock to the slave device.
During this part of the transaction, the master device becomes the master-receiver, and the slave device
becomes the slave-transmitter. The master device continues sending out the clock pulses, but releases the SDA
line so that the slave device can transmit data. At the end of the byte, the master device send a negative-
acknowledge (NACK) signal, signaling to the slave device to stop communications and release the bus. The
master device then sends a STOP condition.

Repeated Start

START 7-bit Slave Address R/W=0 ACK 8-bit Register Address ACK RSTRT 7-bit Slave Address R/W=1

STOP NACK 8-bit Data ACK

Figure 38. I2C Read Sequence

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Programming (continued)
7.5.2 Multi-Slave Operation
Multi-slave operation is used to control multiple DRV8847S devices through one I2C line as shown in Figure 39.
The default device address of the DRV8847 device is 0x60 (7-bit address). Therefore, any DRV8847S device
can be accessed using this address. The steps for multi-slave configuration for programming device-1 out of 4
connected devices (as shown in Figure 39) are as follows:

nFAULT1 nFAULT4
Microcontroller
(Master)

nFAULT2 nFAULT3

SCL SDA

nFAULT (3)

nFAULT (4)
nFAULT (1)

nFAULT (2)

SDA

SDA
SCL

SCL
SDA

SDA
SCL

SCL

DRV8847S (1) DRV8847S (2) DRV8847S (3) DRV8847S (4)

(Slave 1) (Slave 2) (Slave 3) (Slave 4)

Figure 39. Multi-Slave Operation of DRV8847S

• The DRV8847S device variant is configured for multi-slave operation by writing the DISFLT bit (IC2_CON
register) of all connected devices to 1b. This step will disable the nFAULT output pin of all DRV8847S, to
avoid any race condition between master and slave I2C device.
• Pull the nFAULT pins (nFAULT2, nFAULT3, and nFAULT4 pins) of three devices (2, 3, and 4) to low to
release the I2C buses of the slave device (device-2, device-3 and device-4). Now only device-1 is connected
to master.
• Since, only one device, DRV8847S (1), is connected to the controller, and, therefore, its slave address can be
reprogrammed from default 0x60 (7-bit address) to another unique address.
• Similarly, the slave address (SLAVE_ADDR) of the other three devices (device-2, device-3 and device-4) can
be reprogrammed sequentially to unique addresses by a combination of nFAULT pins.
• When all slave addresses are reprogrammed, resume the DISFLT bit to 0b (IC2_CON register). This will
enable the nFAULT output pin for fault flagging.
• All the nFAULT pins are released and a multi-slave setup is complete. Now all connected slave devices can
be accessed using the newly reprogrammed address.
• The above steps should be repeated for any device in case of a power reset (nSLEEP). .

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7.6 Register Map

Table 15 lists the memory-mapped I2c registers for the DRV8847 device. The I2C registers are used to configure the DRV8847S device and for device
diagnostics.

NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 15). Writing to these registers may have
unintended effects. For all reserved bits, the default value is 0b.

Table 15. I2C Registers

Address Acronym Register Name 7 6 5 4 3 2 1 0 Access Section
0x00 SLAVE_ADDR Slave Address RSVD SLAVE_ADDR RW Go
0x01 IC1_CON IC1 Control TRQ IN4 IN3 IN2 IN1 I2CBC MODE RW Go
0x02 IC2_CON IC2 Control CLRFLT DISFLT RSVD DECAY OCPR OLDOD OLDFD OLDBO RW Go
0x03 SLR_STATUS1 Slew Rate and Fault Status-1 RSVD SLR RSVD nFAULT OCP OLD TSDF UVLOF RW Go
0x04 STATUS2 Fault Status-2 OLD4 OLD3 OLD2 OLD1 OCP4 OCP3 OCP2 OCP1 R Go

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Complex bit access types are encoded to fit into small table cells. Table 16 shows the codes that are used for
access types in this section.

Table 16. Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

7.6.1 Slave Address Register (Address = 0x00) [reset = 0x60]

Slave Address is shown in Figure 40 and described in Table 17.

Figure 40. Slave Address Register

7 6 5 4 3 2 1 0
RSVD SLAVE_ADDR
R-0b R/W-1100000b

Table 17. Slave Address Register Field Descriptions

Bit Field Type Reset Description
7 RSVD R 0b Reserved
6-0 SLAVE_ADDR R/W 1100000b Slave address (8 bit)
The default value is 0x60

7.6.2 IC1 Control Register (Address = 0x01) [reset = 0x00]

IC1 Control is shown in Figure 41 and described in Table 18.
Figure 41. IC1 Control Register
7 6 5 4 3 2 1 0
TRQ IN4 IN3 IN2 IN1 I2CBC MODE
R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-00b

Table 18. IC1 Control Register Field Descriptions

Bit Field Type Reset Description
7 TRQ R/W 0b 0b = Torque scalar set to 100%
1b = Torque scalar set to 50%
6 IN4 R/W 0b The INx bits are used to control the bridge operation.
5 IN3 R/W 0b The INx bits are used to control the bridge operation.
4 IN2 R/W 0b The INx bits are used to control the bridge operation.
3 IN1 R/W 0b The INx bits are used to control the bridge operation.
2 I2CBC R/W 0b 0b = Bridge control configured by using the INx pins
1b = Bridge control configured by using the INx bits
1-0 MODE R/W 00b 00b = 4-pin interface
01b = 2-pin interface
10b = Parallel interface
11b = Independent mode

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7.6.3 IC2 Control Register (Address = 0x02) [reset = 0x00]

IC2 Control is shown in Figure 42 and described in Table 19.
Figure 42. IC2 Control Register
7 6 5 4 3 2 1 0
CLRFLT DISFLT RSVD DECAY OCPR OLDOD OLDFD OLDBO
R/W-0b R/W-0b R-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 19. IC2 Control Register Field Descriptions

Bit Field Type Reset Description
7 CLRFLT R/W 0b Set this bit to issue a clear FAULT command. This command
clears all FAULT bits other than the OLD and OLDx bits. This bit
reset to 0b after clearing all the faults.
0b = No clear FAULT command issued
1b = Clear FAULT command issued
6 DISFLT R/W 0b 0b = nFAULT pin not disable
1b = nFAULT pin is disabled
5 RSVD R 0b Reserved
4 DECAY R/W 0b 0b = 25% fast decay
1b = 100% slow decay
3 OCPR R/W 0b 0b = OCP auto retry mode
1b = OCP latch mode
2 OLDOD R/W 0b 0b = Idle
1b = OLD on-demand is activated
1 OLDFD R/W 0b 0b = Fault signaling on OLD
1b = No fault signaling on OLD
0 OLDBO R/W 0b 0b = Bridge operating on OLD
1b = Bridge Hi-Z on OLD

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7.6.4 Slew-Rate and Fault Status-1 Register (Address = 0x03) [reset = 0x40]
Fault Status-1 is shown in Figure 43 and described in Table 20.

Figure 43. Fault Status-1 Register

7 6 5 4 3 2 1 0
RSVD SLR RSVD nFAULT OCP OLD TSDF UVLOF
R-0b R/W-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 20. Fault Status-1 Register Field Descriptions

Bit Field Type Reset Description
7 RSVD R 0b Reserved
6 SLR R/W 0b 0b = 150 ns
1b = 300 ns
5 RSVD R 0b Reserved
4 nFAULT R 0b 0b = No FAULT detected (mirrors the nFAULT pin)
1b = FAULT detected
3 OCP R 0b 0b = No OCP detected
1b = OCP detected
2 OLD R 0b 0b = No open load detected
1b = Open load detected
1 TSDF R 0b 0b = No TSD fault detected
1b = TSD fault detected
0 UVLOF R 0b 0b = No UVLO fault detected
1b = UVLO fault detected

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7.6.5 Fault Status-2 Register (Address = 0x04) [reset = 0x00]

Fault Status-2 is shown in Figure 44 and described in Table 21.
Figure 44. Fault Status-2 Register
7 6 5 4 3 2 1 0
OLD4 OLD3 OLD2 OLD1 OCP4 OCP3 OCP2 OCP1
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 21. Fault Status-2 Register Field Descriptions

Bit Field Type Reset Description
7 OLD4 R 0b 0b = No open load detected on OUT4
1b = Open load detected on OUT4
6 OLD3 R 0b 0b = No open load detected on OUT3
1b = Open load detected on OUT3
5 OLD2 R 0b 0b = No open load detected on OUT2
1b = Open load detected on OUT2
4 OLD1 R 0b 0b = No open load detected on OUT1
1b = Open load detected on OUT1
3 OCP4 R 0b 0b = No OCP detected on OUT4
1b = OCP detected on OUT4
2 OCP3 R 0b 0b = No OCP detected on OUT3
1b = OCP detected on OUT3
1 OCP2 R 0b 0b = No OCP detected on OUT2
1b = OCP detected on OUT2
0 OCP1 R 0b 0b = No OCP detected on OUT1
1b = OCP detected on OUT1

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8847 device is used in applications for stepper or brushed DC motor control.

8.2 Typical Application

The user can configure the DRV8847 for stepper motor and dual BDC motor applications as described in this
section.

8.2.1 Stepper Motor Application

Figure 45 shows the typical application of the DRV8847 device to drive a stepper motor.

1 16
nSLEEP IN1

2 15
OUT1 IN2

330 m 3 14
ISEN12 MODE

4 13
OUT2 GND
10 µF 0.1 µF
DRV8847 12
Stepper 5
OUT4 VM
Motor
330 m 6 11
ISEN34 TRQ

7 10
OUT3 IN4

8 9
VEXT nFAULT IN3
(Logic Supply)

To Controller

Figure 45. Typical Application Schematic of Device Driving Stepper Motor

8.2.1.1 Design Requirements

Table 22 lists design input parameters for system design.

Table 22. Design Parameters

DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Motor supply voltage VM 12 V
Motor winding resistance RL 34 Ω/phase
Motor winding inductance LL 33 mH/phase
Motor RMS current IRMS 350 mA
Target trip current ITRIP 350 mA
Trip current reference voltage (internal voltage) VTRIP 150 mV

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8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Current Regulation

The trip current (ITRIP) is the maximum current driven through either winding. The amount of this current depends
on the sense resistor value (RSENSExx) as shown in Equation 4 (Considering torque setting (TRQ) as 100%).
Torque u VTRIP
ITRIP
RSENSExx
(4)
The ITRIP current is set by a comparator which compares the voltage across the RSENSExx resistor to a reference
voltage. To avoid saturation of the motor, the ITRIP current must be calculated as shown in Equation 5.
VVM
ITRIP
RL (:) RDS(ON) _ HS (:) RDS(ON) _ LS (:) RSENSExx (:)

where
• VVM is the motor supply voltage.
• RL is the motor winding resistance.
• RDS(ON)_HS and RDS(ON)_LS are the high-side and low-side on-state resistance of the FET. (5)
For an ITRIP value of 350 mA, the value of the sense resistor (RSENSExx) is calculated as shown in Equation 6.
VTRIP 150 mV
RSENSE12 RSENSE34 428.6 m:
ITRIP 350 mA (6)
Select the closest available value of 440 mΩ for the sense resistors. Selecting this value will effect the current
accuracy by 2.8%.

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8.2.1.3 Application Curves

Figure 46. Device Power-up with Supply Voltage (VM) Figure 47. Device Power-up with nSLEEP

Figure 48. Stepper Motor Full-Step Operation Figure 49. Stepper Motor Half-Step Operation With Off-
State as Hi-Z

Figure 50. Stepper Motor Half-Step Operation With Off- Figure 51. Brushed DC Motor Operation in Parallel Mode
State as Brake Showing Current Regulation at 2-A

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Figure 52. Zoomed Waveform Showing Current Regulation Figure 53. Torque Pin Functionality for Current Scaling

Figure 54. Undervoltage Lockout Operation Figure 55. Open Load Detect Operation

Figure 56. Over Current Protection and Recovery Figure 57. Zoomed Waveform of Over Current Protection

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DRV8847
SLVSE65A – JULY 2018 – REVISED AUGUST 2018 www.ti.com

8.2.2 Dual BDC Motor Application

Figure 58 shows the typical application of DRV8847 device to drive dual BDC motors.

1 16
nSLEEP IN1

2 15
OUT1 IN2

330 m 3 14
BDC ISEN12 MODE

4 13
OUT2 GND
10 µF 0.1 µF
DRV8847 12
5
OUT4 VM

330 m 6 11
BDC ISEN34 TRQ

7 10
OUT3 IN4

8 9
VEXT nFAULT IN3
(Logic Supply)

To Controller

Figure 58. Typical Application Schematic of Device Driving Two BDC Motors

8.2.2.1 Design Requirements

Table 23 lists the design input parameters for system design.

Table 23. Design Parameters

DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Motor supply voltage VM 12 V
Motor winding resistance RL 13.2 Ω
Motor winding inductance LL 500 µH
Motor RMS current IRMS 490 mA
Motor start-up current ISTART 900 mA
Target trip current ITRIP 1.2 A
Trip current reference voltage (internal voltage) VTRIP 150 mV

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Motor Voltage

The motor voltage used in an application depends on the rating of the selected motor and the desired revolutions
per minute (RPM). A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to
the power FETs. A higher voltage also increases the rate of current change through the inductive motor
windings.

8.2.2.2.2 Current Regulation

The trip current (ITRIP) is the maximum current driven through either winding. Because the peak current (start
current) of the motor is 900 mA, the ITRIP current level is selected to be just greater than the peak current. The
selected ITRIP value for this example is 1.2 A. Therefore, use Equation 7 to select the value of the sense resistors
(RSENSE12 and RSENSE34) connected to the ISEN12 and ISEN34 pins.
VTRIP 150 mV
RSENSE12 RSENSE34 125 m:
ITRIP 1.2 A (7)

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 DRV8847
www.ti.com SLVSE65A – JULY 2018 – REVISED AUGUST 2018

8.2.2.2.3 Sense Resistor

For optimal performance, the sense resistor must:
• Be a surface mount component
• Have low inductance
• Be rated for high enough power
• Be placed closely to the motor driver
The power dissipated by the sense resistor equals IRMS2 × R. In this example, the peak current is 900 mA, the
RMS motor current is 490 mA, and the sense resistor value is 125 mΩ. Therefore, the sense resistors (RSENSE12
and RSENSE34) dissipate 30 mW (490 mA2 × 125 mΩ = 30 mW). The power quickly increases with higher current
levels.
Resistors typically have a rated power within some ambient temperature range, along with a derated power curve
for high ambient temperatures. When a printed circuit board (PCB) is shared with other components generating
heat, margin should be added. For best practice, measure the actual sense resistor temperature in a final
system, along with the power MOSFETs, because those components are often the hottest.
Because power resistors are larger and more expensive than standard resistors, the common practice is to use
multiple standard resistors in parallel, between the sense node and ground. This practice distributes the current
and heat dissipation.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 53

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DRV8847
SLVSE65A – JULY 2018 – REVISED AUGUST 2018 www.ti.com

9 Power Supply Recommendations

The DRV8847 device is designed to operate from an input voltage supply (VVM) range from 2.7 V to 18 V. Place
a 0.1-µF ceramic capacitor rated for VM as close to the DRV8847 device as possible. In addition, a bulk
capacitor with a value of at least 10 µF must be included on the VM pin.

9.1 Bulk Capacitance Sizing

Bulk capacitance sizing is an important factor in motor drive system design. The amount of bulk capacitance
depends on a variety of factors including:
• Type of power supply
• Acceptable supply voltage ripple
• Parasitic inductance in the power supply wiring
• Type of motor (brushed DC, brushless DC, stepper)
• Motor start-up current
• Motor braking method
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. Size the bulk capacitance to meet acceptable voltage ripple
levels.
The data sheet provides a recommended minimum value, but system-level testing is required to determine the
appropriate-sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ +
Motor Driver
±

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 59. Setup of Motor Drive System With External Power Supply

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 DRV8847
www.ti.com SLVSE65A – JULY 2018 – REVISED AUGUST 2018

10 Layout

10.1 Layout Guidelines

Bypass the VM pin to ground using a low-ESR ceramic bypass capacitor with a recommended value of 10 μF
and rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.

10.2 Layout Example

nSLEEP
nSLEEP IN1
16

AOUT1
OUT1 IN2
15

ISEN12
AISEN MODE
14

4
AOUT2
OUT2 GND
13

5
BOUT2
OUT4 VM
12

6
ISEN34
BISEN TRQ
11

7
BOUT1
OUT3 IN4
10

8
nFAULT
nFAULT IN3
9

Figure 60. Layout Recommendation of 16-Pin TSSOP Package for Single-Layer Board

nSLEEP IN116

OUT1 IN215

ISEN12 MODE
14

4
OUT2 GND
13

5
OUT4 VM12

6
SEN34 TRQ
11

7
BOUT3 IN410

8
nFAULT IN3IN3

Figure 61. Layout Recommendation of 16-Pin HTSSOP Package for Double-Layer Board

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SLVSE65A – JULY 2018 – REVISED AUGUST 2018 www.ti.com

10.3 Thermal Considerations

10.3.1 Maximum Output Current
In actual operation, the maximum output current that is achievable with a motor driver is a function of the die
temperature. This die temperature is greatly affected by ambient temperature and PCB design. Essentially, the
maximum motor current is the amount of current that results in a power dissipation level that, along with the
thermal resistance of the package and PCB, keeps the die at a low enough temperature to avoid thermal
shutdown.
The dissipation ratings given in the data sheet can be used as a guide to calculate the approximate maximum
power dissipation that can be expected without putting the device in thermal shutdown for several different PCB
constructions. However, for accurate data, the actual PCB design must be analyzed through measurement or
thermal simulation.

10.3.2 Thermal Protection

The DRV8847 device has thermal shutdown (TSD) as described in the Maximum Output Current section. If the
die temperature exceeds approximately 150°C, the device is disabled until the temperature decreases 40°C.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heat-
sinking, or too high an ambient temperature.

10.4 Power Dissipation

Power dissipation in the DRV8847 device is dominated by the DC power dissipated in the output FET resistance
(RDS(ON)_HS and RDS(ON)_LS). Additional power is dissipated because of PWM switching losses. These losses are
dependent on the PWM frequency, rise and fall times, and VM supply voltages. These switching losses are
typically on the order of 10% to 30% of the DC power dissipation.
Use Equation 8 to estimate the DC power dissipation of one H-bridge.
PTOT RDS(ON) _ LS u IOUT(RMS)2 RDS(ON) _ HS u IOUT(rms)2

where
• PTOT is the total power dissipation
• IOUT(RMS) is the RMS output current being applied to motor
• RDS(ON)_HS and RDS(ON)_LS are the high-side and low-side on-state resistance of the FET (8)

NOTE
The value of RDS(ON)_HS and RDS(ON)_LS increases with temperature. Therefore, as the
device heats, the power dissipation increases. This relationship must be considered when
sizing the heat-sink.

56 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

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 DRV8847
www.ti.com SLVSE65A – JULY 2018 – REVISED AUGUST 2018

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, DRV8847EVM User's Guide
• Texas Instruments, DRV8847EVM and DRV8847SEVM Software User's Guide
• Texas Instruments, Small Motors in Large Appliances TI TechNote

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2018, Texas Instruments Incorporated Submit Documentation Feedback 57

Product Folder Links: DRV8847
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

DRV8847PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8847PWP
& no Sb/Br)
DRV8847PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8847PW
& no Sb/Br)
DRV8847RTER ACTIVE WQFN RTE 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8847
& no Sb/Br)
DRV8847RTET ACTIVE WQFN RTE 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8847
& no Sb/Br)
DRV8847SPWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 8847SPW
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2019

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Apr-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8847PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DRV8847PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
DRV8847RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
DRV8847RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
DRV8847SPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Apr-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8847PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
DRV8847PWR TSSOP PW 16 2000 367.0 367.0 35.0
DRV8847RTER WQFN RTE 16 3000 367.0 367.0 35.0
DRV8847RTET WQFN RTE 16 250 210.0 185.0 35.0
DRV8847SPWR TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PWP0016C SCALE 2.500
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C
AREA 14X 0.65 SEATING
16 PLANE
1

2X
5.1
4.55
4.9
NOTE 3

8
9
0.30
4.5 16X
B 0.19
4.3
0.1 C A B
SEE DETAIL A

(0.15) TYP

2X 0.95 MAX
NOTE 5 4X (0.3)
8 9
2X 0.23 MAX
NOTE 5

2.31 17
0.25
1.75
GAGE PLANE 1.2 MAX

0.75 0.15
1 16 0 -8 0.50 0.05
DETAIL A
A 20

THERMAL 2.46 TYPICAL

PAD 1.75

4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0016C TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
(2.46)
16X (1.5)
SYMM METAL COVERED
BY SOLDER MASK
1
16X (0.45) 16 (1.2) TYP

(R0.05) TYP

SYMM 17 (2.31)
(5)
(0.6) NOTE 9
14X (0.65)

( 0.2) TYP
VIA 8 9

SOLDER MASK (1) TYP

DEFINED PAD SEE DETAILS
(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4224559/B 01/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0016C TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.46)
BASED ON
16X (1.5) METAL COVERED
0.125 THICK
STENCIL BY SOLDER MASK
1
16X (0.45) 16

(R0.05) TYP

(2.31)
SYMM 17 BASED ON
0.125 THICK
STENCIL
14X (0.65)

8 9

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.75 X 2.58
0.125 2.46 X 2.31 (SHOWN)
0.15 2.25 X 2.11
0.175 2.08 X 1.95

4224559/B 01/2019
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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