Important Points in SystemVerilog and UVM
Important Points in SystemVerilog and UVM
1 Assertions Ok Ok.
Good diagram
2 Coverage Ok ok
&&
Scoreboard Ok. ok
4 uvm_config_db task ok ok
5 Scoreboard ok ok
Project: lrm_fkj_issue
7 Clocking block: Ok. Ok.
Definition of clone
constraints
$timeformat
22. Values of rand and randc variable after failed Ok. Ok.
randomization
Will be “0”
23. Randomization of real number: Ok. Ok.
https://www.quora.com/How-can-we-randomize-real-
numbers-in-SystemVerilog-and-Verilog-HDL
25. Randc not seems cyclic, and prefer not to use Ok Ok.
in UVM
post_randomize()
29. Checkout more details of inout direction and Ok. Must read Ok.
Article and
ref
important