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Important Points in SystemVerilog and UVM

The document contains 30 topics related to UVM and verification. The topics range from assertions, coverage, TLM, scoreboarding, randomization, sequences, polymorphism, factory pattern, and more. Most topics are marked as "Ok" or "ok" for both Status1 and Status2, indicating they have been reviewed.

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sunil
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62 views

Important Points in SystemVerilog and UVM

The document contains 30 topics related to UVM and verification. The topics range from assertions, coverage, TLM, scoreboarding, randomization, sequences, polymorphism, factory pattern, and more. Most topics are marked as "Ok" or "ok" for both Status1 and Status2, indicating they have been reviewed.

Uploaded by

sunil
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 4

Sr.

No Topics Status1 Status2

1 Assertions Ok Ok.

1.1 Interrupts Handling in UVM

Good diagram

2 Coverage Ok ok

FOR reg coverage and apb monitor and


general monitor creation use :

UART Project with name uart_mgc

And creation of sequence and assigning the


value to reg in sequence.

&&

sending from the sequence and writing from


the seq_lib in the reg, note this difference
from the SPI project.
3 TLM ok Ok.

Scoreboard Ok. ok

3.1 RAL based Scoreboarding Ok. Ok.

Try to understand from SPI example.

For QuestaSim compile and run options use below link:

4 uvm_config_db task ok ok
5 Scoreboard ok ok

6 Ref formal argument in fork join any Ok. Ok.

Project: lrm_fkj_issue
7 Clocking block: Ok. Ok.

8 fork/join_none inside function call Ok. Ok.

9. Assigning value to Inout variable: Ok. Ok.

10. Automatic variable(all variables in the class ok Ok.

are automatic by default)

11. Fork-join-none inside for loop Ok. Ok.

12. What is the difference between a mailbox and a Ok Ok.


queue in SystemVerilog?

13. Range operator can be given in case statement ok Ok.


like
Case(xyz) inside

[1:0] : $display("In range");

[3:4 : $display(“In the range given”);


14. RAL, Adapter context ooooook
kkkkkaaa
ayyyyy

15. Frequency division circuit Ok. Ok.

Toggle flip flop is used for frequency division


circuit.

16. Randc from rand variable Ok Ok.

17. ADVANCE Sequences


One dut provides APB as well as AHB interface to access its
registers. Based on requirement we can access single
register or bulk access of registers.

Accessing multiple registers at once

a. Passing type as an argument to functions Ok. Ok.

18. Polymorphism: ok Ok.

Definition of clone

19. Generate five transaction with some ok ok

constraints

20. Factory pattern Ok Ok.

21. Timeunit and timeprecision Ok Ok.

$timeformat

22. Values of rand and randc variable after failed Ok. Ok.
randomization

Will be “0”
23. Randomization of real number: Ok. Ok.

https://www.quora.com/How-can-we-randomize-real-
numbers-in-SystemVerilog-and-Verilog-HDL

24. Stratified event queue in verilog Ok Ok.

25. Randc not seems cyclic, and prefer not to use Ok Ok.

in UVM

26. Sv interview questions Ok. Ok.

27. Example of pre_randomize and Ok. Ok.

post_randomize()

28. Deep copy , shallow copy and Clone Ok. Ok.

29. Checkout more details of inout direction and Ok. Must read Ok.
Article and
ref
important

30. P_sequencer usage, no need to use instead Ok. Ok.

use “uvm_config_db” or m_sequencer


handle.

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