The University of The South Pacific: EE326 Embedded Systems
The University of The South Pacific: EE326 Embedded Systems
Question 1 A 40-MHz processor was used to execute a benchmark program with the
following instruction mix and clock cycle counts:
Determine the effective CPI, MIPS rate, and execution time for this program.
Question 2 Explain how instruction set, compiler technology, CPU implementation and
control, and cache and memory hierarchy affect the CPU performance and justify the effects in
terms of program length, clock rate, and effective CPI.
Question 3 Consider the execution of an object code with 200,000 instructions on a 40-MHz
processor. The program consists of four major types of instructions. The instruction mix and
the number of cycles (CPI) needed for each instruction type given below based on the result of
a program trace experiment:
(a) Calculate the average CPI when the program is executed on a single processor with the
above trace results.
(b) Calculate the corresponding MIPS rate based on the CPI obtained in part (a).
1|Page
The University of the South Pacific
Question 4 The following code segment, consisting of six instructions, needs to be execute
64 times for the evaluation of vector arithmetic expression: D(I) = A(I) + B(I) x C(I) for 0 < I < 63.
where R1, R2, and R3 are CPU registers, (R1) is the content of R1, α, β, γ, and θ are the
starting memory addresses of arrays B(I), C(I), A(I), and D(I), respectively. Assume four clock
cycles for each Load or Store, two cycles for the Add, and eight cycles for the Multiply on either
a single processor machine. Calculate the total number of CPU cycles to execute the above
code segment repeatedly 64 times on a single processor computer sequentially, ignoring all
other time delays.
2|Page