Building an ALU (Part 1):

Announcements:
Honor’s section survey closing
CATME survey for discussion section
Lab 2 part 1 due Thursday
An Arithmetic Logic Unit (ALU) is the primary
manipulator of state information in computers
Computer can do 2 things
1) Store state
2) Manipulate state (Combine arithmetic and logical operations into
one unit)

State
State Manipulations
Storage
233 in one slide!
Today we will introduce
how we use control bits
to manipulate data

 The class consists roughly of 4 quarters: (Bolded words are the big
ideas of the course, pay attention when you hear these words)
1. You will build a simple computer processor
Build and create state machines with data, control, and indirection
2. You will learn how high-level language code executes on a processor
Time limitations create dependencies in the state of the processor
3. You will learn why computers perform the way they do
Physical limitations require locality and indirection in how we access state
4. You will learn about hardware mechanisms for parallelism
Locality, dependencies, and indirection on performance enhancing drugs

 We will have a SPIMbot contest!

Today’s lecture
 We start building our computer!
 We’ll start with the arithmetic/logic unit (ALU)

 Adding single bits

 Half Adders and Full Adder
 Multi-bit Arithmetic
 Hierarchical design
 Subtraction
 Building a Logic Unit
 Multiplexors
The computation in a computer processor takes
place in the arithmetic logic unit (ALU)
 Arithmetic Unit (AU) performs arithmetic operations
Put ‘em together and
 e.g., addition and subtraction
what do you get?
 Logic Unit (LU) performs bit-wise logical operations
 e.g., AND, OR, NOR, XOR

 Typically these operations are performed on multi-bit words

 The MIPS-subset processor we will build uses 32-bit words

In Lab 3 you will build a 32-bit ALU with the above operations
Binary Addition Review

1 1 1 0 0 Carries
1 0 1 1 Augend
+ 1 1 1 0 Addend
1 1 0 0 1 Sum
First bit position receives two input bits to
produce two output bits

Two input bits:

We’ll call them x, y

1 1 1 0 Carries
1 0 1 1 Augend
+ 1 1 1 0 Addend
1 1 0 0 1 Sum

Two output bits: c = carry out s = Sum

(from first column)
Specify the first bit position’s behavior with a
truth table

X Y C S
0 0 Two input bits:
0 1 We’ll call them x, y
1 0
1 1 1 1 1 0 Carries
1 0 1 1 Augend
+ 1 1 1 0 Addend
1 1 0 0 1 Sum

c = carry out s = Sum

(from first column)
This truth table specifies a circuit we call a half
adder
 Adds two input bits to produce a sum and carry out.
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

C = XY
S = X’Y + XY’
=X⊕Y

XOR

 The carry-out bit has twice the magnitude of the sum bit
Second bit position receives three input bits to
produce two output bits
 (and every subsequent position)

Three input bits;

x, y, carry_in

1 1 1 0 Carries
1 0 1 1 Augend
+ 1 1 1 0 Addend
1 1 0 0 1 Sum

Still two output bits: c = carry out s = Sum

(from first column)
Proximity
sensor
Specify the remaining bit positions’ behaviors
with a truth table
 Adding 3 bits together to get a two bit number

X Y Cin Cout S
0 + 0+ 0= 00 0 0 0
0 + 0+ 1= 01 0 0 1
0 + 1+ 0= 01 0 1 0
0 + 1+ 1= 10 0 1 1
1 + 0+ 0= 01 1 0 0
1 + 0+ 1= 10 1 0 1
1 + 1+ 0= 10 1 1 0
1 + 1+ 1= 11 1 1 1
This truth table specifies a circuit we call a Full
Adder
 Adds three input bits to produce a sum and carry out.

X Y Cin Cout S
S = X ⊕ Y ⊕ Cin 0 0 0 0 0
Cout = XY + (X ⊕ Y)Cin 0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
We can use hierarchical design to build a full
adder from a half adder
Half Adder
Equations
S = X ⊕ Y ⊕ Cin C = XY
Cout = XY + (X ⊕ Y)Cin S =X⊕Y
We can use hierarchical design to build multi-
bit adders
 Recall our discussion about hierarchical design
 (The stop lights to prevent train collisions…)

CO C3 C2 C1 CI Carries
A3 A2 A1 A0 Augend
+ B3 B2 B1 B0 Addend
S3 S2 S1 S0 Sum
 Example: 4-bit adder
An example of 4-bit addition
 Let’s try our initial example: A=1011 (eleven), B=1110 (fourteen).

a) 0
What is the value of S1?
b) 1
Implementing Subtraction
 Subtraction is technically negating the second input and then adding
A - B = A + (-B)

 Negating in 2’s complement is inverting the bits and adding one

-B = ~B + 1

 Substituting in:
A: A – ~B + 1
A - B = A + (-B) = .
B: A + ~B + 1
C: A – (~B + 1)
D: A + ~B – 1
E: none of the above
Implementing Subtraction, cont.
 Let’s try an example: A=0011 (three), B=1110 (negative 2).

a) 0
What is the value of S3?
b) 1
Use XOR gates to implement Addition +
Subtraction in one circuit
 XOR gates let us selectively complement the B input.
Control bit
X⊕0=X X ⊕ 1 = X’
Data bit
 When Sub = 0, Y = B and Cin = 0. Result = A + B + 0 = A + B.
 When Sub = 1, Y = ~B and Cin = 1. Result = A + ~B + 1 = A – B.
We conceptually distinguish two types of signal
in hardware: Data and Control

 Datapath
 These generally carry the numbers we’re crunching
 E.g., the X and Y inputs and the output S

 Control
 These generally control how data flows and what operations are performed
 E.g., the SUB signal.
Logical Operations
 In addition to ADD and SUBTRACT, we want our ALU to perform bit-
wise AND, OR, NOR, and XOR.
 This should be straight forward.
 We have gates that perform each of these operations.

Y
Selecting the desired logical operation
 We need a control signal to specify the desired operation:
 We’ll call that signal R
 4 operations means R is 2 bits

 We need a circuit to perform the selection:

Multiplexors use control bits to select data
 A multiplexor is a circuit that (logically) selects one of its data inputs
to connect to its data output

 Consider a 2-to-1 multiplexor. It has:

 2 data input bits (I0,I1)
 a 1-bit control input bit (S)
 1 data output bit (Y)

 The control input selects which data input is output:

Y = S’I0 + SI1
Multiplexors, cont.
 In general, a multiplexor (mux) has:
 2N data input bits (I0–I2N-1)
A: S1S0
 an N-bit control input (S)
 1 data output bit (Y) B: S2S0
C: S1S0’
 If S = K then Y = IK
D: S2S0’
E: S1’S0
 Examples:
 4-to-1 mux: 4 data input bits, 2-bit control input
 Y = S1’S0’I0 + S1’S0I1 + ____I2 + S1S0I3

 16-to-1 mux: 16 data input bits, 4-bit control input

Complete 1-bit Logic Unit
Mux Hierarchical Design (operand width)
2
 What if we want to mux 2 2bit numbers? 2
2
Mux Hierarchical Design (more inputs)
 How do we build a mux with 4 inputs?

A: S0
B: S1
C: Either