VHDL BASICS

Data Objects and Data Types

• VHDL provides a number of basic, or scalar, types,
and a means of forming composite types. The
scalar types include numbers, physical quantities,
and enumerations (including enumerations of
characters), and there are a number of standard
predefined basic types. The composite types
provided are arrays and records. VHDL also
provides access types(pointers) and files,
although these will not be fully described in this
booklet.
 VHDL Objects
An object is a named item in a VHDL model that has a value of a
specific type. There are four classes of objects:
- Constants
- Signals
- Variables
- Files

 File declarations make a file available for use to a design

 Files can be opened for reading and writing

 Files provide a way for a VHDL design to communicate

with the host environment
 Constants and Variables

 The use of constants and variables in VHDL is similar to what you

are already familiar with from other programming languages.

 Constant: An object whose value is specified at compile time and

cannot be changed by VHDL statements. Like C.

 Variable: A data object whose current value can be changed by

VHDL statements. Like C.
 VHDL Objects
Constants

 Improve the readability of the code

 Allow for easy updating

CONSTANT <constant_name> : <type_name> := <value>;

CONSTANT PI : REAL := 3.14;

CONSTANT WIDTH : INTEGER := 8;
 Variables
 Only defined within processes or subprograms (subprograms are
functions and/or procedures)
– Within a process, the variable is LOCAL and STATIC to the process
– Local means that it is not visible outside the process (like C)
– Static means that the value is kept until the next process call (like C)
– Initialized once at the beginning of the simulation (like C)
– A variable can be declared as shared to be shared between processes
 Within a subprogram, the variable is DYNAMIC
– Dynamic means that the values are not kept until the next call (like C)
– Initialized every time the subprogram is called
 Variables are VERY EFFICIENT and are assigned immediately after the variable
statement! We use := to assign them (NOT <= )
 VHDL Objects
Variables

 Variables are used only in processes and subprograms

(functions and procedures)

 Variables are generally not available to multiple components

and processes

 All variable assignments take place immediately

VARIABLE <variable_name> : <type_name> [:= <value>];

VARIABLE opcode : BIT_VECTOR (3 DOWNTO 0) := "0000";

VARIABLE freq : INTEGER;
 Signals
• Signal: A data object that represents an actual physical data line (wire,
gate or circuit input/output) ,UNLIKE C variables!
– It cannot change instantaneously ,It changes at a later time (after
assignment).
– Signals of type bit take on values of 0 and 1.
– A signal change is called an event.
– The effect of an event is delayed by the propagation delay through
the component. VHDL allows for associating a delay with a signal.
Z <= X and Y after 2 ns;
– Signals may propagate through several components concurrently.
Z <= X and Y after 2 ns;
V <= (Z xor not W) and X after 3 ns;
W <= X or Y after 1 ns;
• Signals are initialized using :=, but they are assigned using <= (NOT :=).
• SIGNALS and VARIABLES are interchangeable!
 VHDL Objects
Signals

 Signals are used for communication between components

 Signals can be seen as real, physical wires

SIGNAL <signal_name> : <type_name> [:= <value>];

SIGNAL enable : BIT;

SIGNAL output : bit_vector(3 downto 0);
SIGNAL output : bit_vector(3 downto 0) := "0111";
 Signals versus Variables
 A key difference between variables and signals is the
assignment delay
ARCHITECTURE signals OF test IS
SIGNAL a, b, c, out_1, out_2 : BIT;
BEGIN
PROCESS (a, b, c)
BEGIN
out_1 <= a NAND b;
out_2 <= out_1 XOR c;
END PROCESS;
END signals;
Time a b c out_1 out_2

0 0 1 1 1 0
1 1 1 1 1 0
1+d 1 1 1 0 0
(1+d)+d 1 1 1 0 1
Signals versus Variables (cont. 1)
ARCHITECTURE variables OF test IS
SIGNAL a, b, c: BIT;
VARIABLE out_3, out_4 : BIT;
BEGIN
PROCESS (a, b, c)
BEGIN
out_3 := a NAND b;
out_4 := out_3 XOR c;
END PROCESS;
END variables;

Time a b c out_3 out_4

0 0 1 1 1 0
1 1 1 1 0 1
 VHDL Objects
Scoping Rules
 VHDL limits the visibility of the objects, depending on where
they are declared

 The scope of the object is as follows

• Objects declared in a package are global to all entities that
use that package o Objects declared in an entity are global to all
architecture that use that entity
• Objects declared in an architecture are available to all
statements in that architecture
• Objects declared in a process are available to only that
process

 Scoping rules apply to constants, variables, signals and files

 VHDL type classification

10 ns
125

“101110001110001”
FALSE ‘1’ ‘A’ 13
 Scalar Types
 Integer Types
- Minimum range for any implementation as defined
by standard:
- 2,147,483,647 (i.e. -(231-1)) to 2,147,483,647 (i.e. 231-1).

ARCHITECTURE test_int OF test IS

BEGIN
PROCESS (X)
VARIABLE a: INTEGER;
BEGIN
a := 1; -- OK
a := -1; -- OK
a := 1.0; -- bad
END PROCESS;
END TEST;
 Scalar Types (cntd.)
 Real Types
- Minimum range for any implementation as defined by
standard: -1.0E38 to 1.0E38

ARCHITECTURE test_real OF test IS

BEGIN
PROCESS (X)
VARIABLE a: REAL;
BEGIN
a := 1.3; -- OK
a := -7.5; -- OK
a := 1; -- bad
a := 1.7E13; -- OK
a := 5.3 ns; -- bad
END PROCESS;
END TEST;
 Scalar Types (cntd.)
 Enumerated Types
An enumeration type is an ordered set of identifiers or characters. The
identifiers and characters within a single enumeration type must be
distinct, however they may be reused in several different enumeration
types.
- User defined range TYPE binary IS ( ON, OFF );
...some statements ...
ARCHITECTURE test_enum OF test IS
BEGIN
PROCESS (X)
VARIABLE a: binary;
BEGIN
a := ON; -- OK
... more statements ...
a := OFF; -- OK
... more statements ...
END PROCESS;
END TEST;
 Scalar Types (cntd.)
 Physical Types:
A physical type is a numeric type for representing some physical
quantity, such as mass, length, time or voltage. The declaration of a
physical type includes the specification of a base unit, and possibly a
number of secondary units, being multiples of the base unit
- Can be user defined range
TYPE resistence IS RANGE 0 to 1000000
UNITS
ohm; -- ohm
Kohm = 1000 ohm; -- 1 K
Mohm = 1000 kohm; -- 1 M
END UNITS;
- Time units are the only predefined physical type in
VHDL
 Scalar Types (cntd.)
 The predefined time units are as follows

TYPE TIME IS RANGE -2147483647 to 2147483647

UNITS
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour
END UNITS;
 Composite Types
 Array Types:
- Used to collect one or more elements of a similar type
in a single construct
- Elements can be any VHDL data type

TYPE data_bus IS ARRAY (0 TO 31) OF BIT;

0 ...element numbers...31
0 ...array values...1

SIGNAL X: data_bus;
SIGNAL Y: BIT;
Y <= X(12); -- Y gets value of 12th element
 Composite Types (cntd.)
 Another sample one-dimensional array
(using the DOWNTO order)

TYPE register IS ARRAY (15 DOWNTO 0) OF BIT;

15 ...element numbers... 0
0 ...array values... 1

Signal X: register;
SIGNAL Y: BIT;
Y <= X(4); -- Y gets value of 4th element

 DOWNTO keyword orders elements from left to right,

with decreasing element indices
 Composite Types (cntd.)
 Two-dimensional arrays are useful for describing truth tables.

TYPE truth_table IS ARRAY(0 TO 7, 0 TO 4) OF BIT;

CONSTANT full_adder: truth_table := (
"000_00",
"001_01",
"010_01",
"011_10",
"100_01",
"101_10",
"110_10",
"111_11");
 Composite Types (cntd.)
 Record Types
- Used to collect one or more elements of a different types in
single construct
- Elements can be any VHDL data type
- Elements are accessed through field name

TYPE binary IS ( ON, OFF );

TYPE switch_info IS
RECORD
status : binary;
IDnumber : integer;
END RECORD;
VARIABLE switch : switch_info;
switch.status := on; -- status of the switch
switch.IDnumber := 30; -- number of the switch
 Access Types

 Access

- Similar to pointers in other languages

- Allows for dynamic allocation of storage

- Useful for implementing queues, fifos, etc.

 Subtypes
 Subtype

- Allows for user defined constraints on a data type

- May include entire range of base type

- Assignments that are out of the subtype range result

in an error

SUBTYPE <name> IS <base type> RANGE <user range>;

SUBTYPE first_ten IS integer RANGE 1 to 10;

 Summary
* VHDL has several different data types available to the
designer
* Enumerated types are user defined
* Physical types represent physical quantities
* Arrays contain a number of elements of the same type or
subtypes
* Records may contain a number of elements of different
types or subtypes
* Access types are basically pointers
* Subtypes are user defined restrictions on the base type