Concurrent Statements

Concurrent and Sequential Statements

* VHDL provides two different types of execution: sequential

and concurrent

* Different types of execution are useful for modeling of real

hardware

* Sequential statements view hardware from a programmer

approach

* Concurrent statements are order-independent and

asynchronous
 Concurrent Versus Sequential
Statements
Sequential Statements Concurrent Statements

•Used Within Process Bodies or •Used Within Architectural Bodies or

SubPrograms Blocks
•Order Dependent •Order Independent
•Executed When Control is Transferred to •Executed Once At the Beginning of
the Sequential Body Simulation or Upon Some Triggered Event
–Assert –Assert
–Signal Assignment –Signal Assignment
–Procedure Call –Procedure Call (None of Formal
Parameters May be of Type Variable)
–Variable Assignment
–Process
–IF Statements
–Block Statement
–Case Statement
–Component Statement
–Loops
–Generate Statement
–Wait, Null, Next, Exit, Return
–Instantiation Statement
VHDL Examples
 VHDL code for AND Gate (Structural)
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity E_AND is
port(
A: in std_logic;
B: in std_logic;
F: out std_logic
);
end E_AND;
-------------------------------------------------
Architecture AND_G of E_AND is
begin
F <= A AND B;
end AND_G;
 VHDL code for AND Gate (Behavioral )
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity 4_AND is
Port (
A: in std_logic;
B: in std_logic;
F: out std_logic
);
end 4_AND;
-------------------------------------------------
architecture Nibble_AND of 4_AND is
Begin

IF A== ‘0’ THEN F<= ‘0’ ;

IFELSE B== ‘0’ THEN F<= ‘0’ ;
ELSE F<= ‘1’ ;
END IF;

end Nibble_AND;
 VHDL code for Nibble AND Gate
(Structural)
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity 4_AND is
port(
A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end 4_AND;
-------------------------------------------------
architecture Nibble_AND of 4_AND is
begin
F <= A AND B;
end Nibble_AND;
 VHDL code for Nibble AND Gate
(Behavioral )
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------
entity 4_AND is
port(
A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
F: out std_logic_vector(3 downto 0)
);
end 4_AND;
-------------------------------------------------
architecture Nibble_AND of 4_AND is
begin
F <= ?????????????????????????????????????;
end Nibble_AND;
And Or gate in VHDL example
A 2
1 X 2
B 3 1 F
3
C

entity ABorC is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
F : out std_logic);
end ABorC;
-------------------------------------------------------
architecture arch of ABorC is
signal X : std_logic;
begin
X := A and B after 1 ns;
F <= X or C after 1 ns;
End arch ;
VHDL code Examples
VHDL code for Mux 4X3
VHDL code for Mux 4X3(Structural)
entity Mux is
Port ( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
-------------------------------------------------
architecture Method1 of Mux is
Begin
O <= I0 AND (NOT S0) AND (NOT S1)
O <= I1 AND ( S0) AND (NOT S1)
O <= I2 AND (NOT S0) AND (S1)
O <= I3 AND (S0) AND (S1)
end Method1;
VHDL code for entity Mux is
Port ( I3: in std_logic_vector(2 downto 0);
Mux 4X3 I2:
I1:
in std_logic_vector(2 downto 0);
in std_logic_vector(2 downto 0);
(Behavioral ) I0:
S:
in std_logic_vector(2 downto 0);
in std_logic_vector(1 downto 0);

case );
O: out std_logic_vector(2 downto 0)

end Mux;
-------------------------------------------------
architecture Method2 of Mux is
begin
process (I3,I2,I1,I0,S)
begin
-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;
end process;
end Method2;
VHDL code for Mux 4X3(Behavioral )
when.. else
entity Mux is
Port ( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;
-------------------------------------------------
architecture Method3 of Mux is
begin
-- use when.. else statement
O <= I0 when S="00" else
I1 when S="01" else
I2 when S="10" else
I3 when S="11" else
"ZZZ";
end Method3;
VHDL code for 2/4 Decoder
VHDL code for
2/4 Decoder entity DECODER is
Port ( B: in std_logic_vector(1 downto 0);

case );
O: out std_logic_vector(3 downto 0)

end DECODER;
-------------------------------------------------
architecture behv of DECODER is
begin
-- process statement
process (I)
begin
-- use case statement
case B is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;
end process;
end behv;
VHDL code for 2/4 Decoder when..else
entity DECODER is
Port ( B: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;
-------------------------------------------------
architecture when_else of DECODER is
begin
-- use when..else statement
O <= "0001" when B= "00"
else "0010" when B = "01"
else "0100" when B = "10"
else "1000" when B = "11"
else "XXXX";
end when_else;
std_logic_1164 multi-value logic
system

'U‘ : -- Uninitialized
'X‘ : -- Forcing Unknown
'0‘ : -- Forcing 0
'1‘ : -- Forcing 1
'Z‘: -- High Impedance
'W‘ : -- Weak Unknown
'L‘ : -- Weak 0
'H‘ : -- Weak 1
'-' : -- Don't care
18
VHDL code for FULL ADDER
 VHDL code for FULL ADDER
(Structural)
entity FULL_ADDER is
Port( x :in istd_logc;
y : in std_logic;
cin: in std_logic;
s : outstd_logic;
cout : out std_logic
);
End FULL_ADDER;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
architecture struct of FULL_ADDER is
begin
s<= (x xor y) xor cin; --summing of two bit in carry also included
cout<=(x and y)or(x and cin)or(y and cin); --output carry
End struct;
 VHDL code for FULL ADDER
(Behavioral)
entity FULL_ADDER is
Port( x :in istd_logc;
y : in std_logic;
cin: in std_logic;
s : outstd_logic;
cout : out std_logic
);
End FULL_ADDER;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
architecture struct of FULL_ADDER is
begin
SUM <= ??????????????????????
CARRY <= ?????????????????????
End struct;
 VHDL code for DFF
Entity dff_G is

Port ( data : in STD_LOGIC; --data input

clk : in STD_LOGIC; --clock input
q : out std_logic -- output
);
End dff_G;
------------------------------------------------------------------------
Architecture dff_Eof dff_Gis
Begin
process (clk,reset)
begin
if (clk'event and clk = '1')then
q <= '0';
else
q <= data;
end if;
end process;
end dff_E;
Set and Rest inputs
 Synchronous with reset
Entity dff_sync_reset is

Port ( data : in STD_LOGIC; --data input

clk : in STD_LOGIC; --clock input
reset : in std_logic; --reset input
q : out std_logic -- output
);
End dff_sync_reset;
------------------------------------------------------------------------
Architecture dff_sync_reset of dff_sync_reset is
Begin
process (clk,reset)
begin
if (clk'event and clk = '1')then
if (reset = '0')then
q <= '0';
else
q <= data;
end if;
end if;
end process;
end dff_sync_reset;
Asynchronous with reset
Entity D_FF is
Port ( d : in STD_LOGIC; --data input
clk : in STD_LOGIC; --latch input
reset : in std_logic; --reset input
q : out std_logic –output
);
End D_FF;
----------------------------------------------------
Architecture D_FF of D_FF is
Begin
Process (Clk, reset)
begin
if (reset = '1')then
q <= '0';
elsif (clk'event and clk = '0')then
q <= d;
end if;
End process;
End D_FF;