Spruh73q PDF
Spruh73q PDF
21.3.8 I2C Clock Generation and I2C Clock Synchronization ................................................... 4592
21.3.9 Prescaler (SCLK/ICLK) ....................................................................................... 4593
21.3.10 Noise Filter ................................................................................................... 4593
21.3.11 I2C Interrupts ................................................................................................. 4593
21.3.12 DMA Events .................................................................................................. 4594
21.3.13 Interrupt and DMA Events .................................................................................. 4594
21.3.14 FIFO Management .......................................................................................... 4594
21.3.15 How to Program I2C......................................................................................... 4599
21.3.16 I2C Behavior During Emulation ............................................................................ 4600
21.4 I2C Registers ............................................................................................................ 4601
21.4.1 I2C Registers .................................................................................................. 4601
22 Multichannel Audio Serial Port (McASP) ............................................................................ 4652
22.1 Introduction ............................................................................................................... 4653
22.1.1 Purpose of the Peripheral .................................................................................... 4653
22.1.2 Features ........................................................................................................ 4653
22.1.3 Protocols Supported ......................................................................................... 4654
22.1.4 Unsupported McASP Features .............................................................................. 4654
22.2 Integration ................................................................................................................ 4655
22.2.1 McASP Connectivity Attributes .............................................................................. 4655
22.2.2 McASP Clock and Reset Management .................................................................... 4656
22.2.3 McASP Pin List ................................................................................................ 4656
22.3 Functional Description .................................................................................................. 4657
22.3.1 Overview ....................................................................................................... 4657
22.3.2 Functional Block Diagram .................................................................................... 4658
22.3.3 Industry Standard Compliance Statement ................................................................. 4661
22.3.4 Definition of Terms ............................................................................................ 4665
22.3.5 Clock and Frame Sync Generators ......................................................................... 4667
22.3.6 Signal Descriptions............................................................................................ 4671
22.3.7 Pin Multiplexing ................................................................................................ 4671
22.3.8 Transfer Modes ................................................................................................ 4672
22.3.9 General Architecture .......................................................................................... 4679
22.3.10 Operation ..................................................................................................... 4683
22.3.11 Reset Considerations ....................................................................................... 4700
22.3.12 Setup and Initialization ...................................................................................... 4700
22.3.13 Interrupts ...................................................................................................... 4705
22.3.14 EDMA Event Support ....................................................................................... 4707
22.3.15 Power Management ......................................................................................... 4709
22.3.16 Emulation Considerations .................................................................................. 4709
22.4 Registers ................................................................................................................. 4710
22.4.1 MCASP Registers ............................................................................................. 4710
23 Controller Area Network (CAN) ......................................................................................... 4772
23.1 Introduction ............................................................................................................... 4773
23.1.1 DCAN Features ................................................................................................ 4773
23.1.2 Unsupported DCAN Features ............................................................................... 4773
23.2 Integration ................................................................................................................ 4774
23.2.1 DCAN Connectivity Attributes ............................................................................... 4774
23.2.2 DCAN Clock and Reset Management ...................................................................... 4775
23.2.3 DCAN Pin List ................................................................................................. 4775
23.3 Functional Description .................................................................................................. 4776
23.3.1 CAN Core ...................................................................................................... 4776
23.3.2 Message Handler ............................................................................................. 4777
23.3.3 Message RAM ................................................................................................. 4777
23.3.4 Message RAM Interface ...................................................................................... 4777
List of Figures
3-1. Microprocessor Unit (MPU) Subsystem ............................................................................... 187
3-2. Microprocessor Unit (MPU) Subsystem Signal Interface ............................................................ 189
3-3. MPU Subsystem Clocking Scheme .................................................................................... 190
3-4. Reset Scheme of the MPU Subsystem ................................................................................ 191
3-5. MPU Subsystem Power Domain Overview............................................................................ 194
4-1. PRU-ICSS Block Diagram ............................................................................................... 199
4-2. PRU-ICSS Integration .................................................................................................... 201
4-3. PRU-ICSS Internal Signal Muxing: pin_mux_sel[0] .................................................................. 204
4-4. PRU-ICSS Internal Signal Muxing: pin_mux_sel[1] .................................................................. 205
4-5. PRU Block Diagram ...................................................................................................... 209
4-6. PRU Module Interface .................................................................................................... 211
4-7. Event Interface Mapping (R31) ......................................................................................... 212
4-8. PRU R31 (GPI) Direct Input Mode Block Diagram ................................................................... 215
4-9. PRU R31 (GPI) 16-Bit Parallel Capture Mode Block Diagram...................................................... 215
4-10. PRU R31 (GPI) 28-Bit Shift In Mode ................................................................................... 216
4-11. PRU R30 (GPO) Direct Output Mode Block Diagram ............................................................... 218
4-12. PRU R30 (GPO) Shift Out Mode Block Diagram ..................................................................... 219
4-13. Integration of the PRU and MPY/MAC ................................................................................. 220
4-14. Multiply-Only Mode Functional Diagram ............................................................................... 221
4-15. Multiply and Accumulate Mode Functional Diagram ................................................................. 222
4-16. Integration of PRU and Scratch Pad ................................................................................... 223
4-17. Interrupt Controller Block Diagram ..................................................................................... 226
4-18. Flow of System Events to Host ......................................................................................... 229
4-19. Industrial Ethernet Peripheral Block Diagram ......................................................................... 233
4-20. Sync Signal Generation Mode .......................................................................................... 236
4-21. Examples of the Dependent Mode of SYNC1 ........................................................................ 237
4-22. IEP DIGIO Data In ........................................................................................................ 239
4-23. IEP DIGIO Data Out ...................................................................................................... 240
4-24. UART Block Diagram..................................................................................................... 242
4-25. UART Clock Generation Diagram ...................................................................................... 243
4-26. Relationships Between Data Bit, BCLK, and UART Input Clock ................................................... 244
4-27. UART Protocol Formats.................................................................................................. 246
4-28. UART Interface Using Autoflow Diagram .............................................................................. 249
4-29. Autoflow Functional Timing Waveforms for UARTn_RTS .......................................................... 250
4-30. Autoflow Functional Timing Waveforms for UARTn_CTS .......................................................... 250
4-31. UART Interrupt Request Enable Paths ................................................................................ 252
4-32. MII_RT Block Diagram ................................................................................................... 255
4-33. Auto-forward ............................................................................................................... 255
4-34. Auto-forward with PRU Snoop .......................................................................................... 256
4-35. 8- or 16-bit Processing with On-the-Fly Modifications ............................................................... 256
4-36. 32-byte Double Buffer or Ping-Pong Processing .................................................................... 256
4-37. Data Nibble Structure .................................................................................................... 257
4-38. PRU R30, R31 Operations .............................................................................................. 257
4-39. Reading and Writing FIFO Data ........................................................................................ 258
4-40. RX Data Latch ............................................................................................................. 259
4-41. Start of Frame Detection ................................................................................................. 260
4-42. CRC Error Detection ..................................................................................................... 260
7-245. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0))............................................................... 975
7-246. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) ...................................................................... 976
7-247. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) ..................................................................... 977
7-248. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) .................................................................... 977
7-249. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) .................................................................. 978
7-250. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) ..................................................... 978
7-251. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) ............................................................. 979
7-252. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS) ....... 980
7-253. DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) ............. 980
7-254. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1 _REG_PHY_DQ_OFFSET_0) ..... 981
7-255. ELM Integration ........................................................................................................... 983
7-256. ELM_REVISION Register ............................................................................................... 997
7-257. ELM_SYSCONFIG Register ............................................................................................ 998
7-258. ELM_SYSSTATUS Register ............................................................................................ 999
7-259. ELM_IRQSTATUS Register ........................................................................................... 1000
7-260. ELM_IRQENABLE Register ........................................................................................... 1002
7-261. ELM_LOCATION_CONFIG Register ................................................................................. 1003
7-262. ELM_PAGE_CTRL Register ........................................................................................... 1004
7-263. ELM_SYNDROME_FRAGMENT_0_0 Register ..................................................................... 1005
7-264. ELM_SYNDROME_FRAGMENT_1_0 Register ..................................................................... 1006
7-265. ELM_SYNDROME_FRAGMENT_2_0 Register ..................................................................... 1007
7-266. ELM_SYNDROME_FRAGMENT_3_0 Register ..................................................................... 1008
7-267. ELM_SYNDROME_FRAGMENT_4_0 Register ..................................................................... 1009
7-268. ELM_SYNDROME_FRAGMENT_5_0 Register ..................................................................... 1010
7-269. ELM_SYNDROME_FRAGMENT_6_0 Register ..................................................................... 1011
7-270. ELM_SYNDROME_FRAGMENT_0_1 Register ..................................................................... 1012
7-271. ELM_SYNDROME_FRAGMENT_1_1 Register ..................................................................... 1013
7-272. ELM_SYNDROME_FRAGMENT_2_1 Register ..................................................................... 1014
7-273. ELM_SYNDROME_FRAGMENT_3_1 Register ..................................................................... 1015
7-274. ELM_SYNDROME_FRAGMENT_4_1 Register ..................................................................... 1016
7-275. ELM_SYNDROME_FRAGMENT_5_1 Register ..................................................................... 1017
7-276. ELM_SYNDROME_FRAGMENT_6_1 Register ..................................................................... 1018
7-277. ELM_SYNDROME_FRAGMENT_0_2 Register ..................................................................... 1019
7-278. ELM_SYNDROME_FRAGMENT_1_2 Register ..................................................................... 1020
7-279. ELM_SYNDROME_FRAGMENT_2_2 Register ..................................................................... 1021
7-280. ELM_SYNDROME_FRAGMENT_3_2 Register ..................................................................... 1022
7-281. ELM_SYNDROME_FRAGMENT_4_2 Register ..................................................................... 1023
7-282. ELM_SYNDROME_FRAGMENT_5_2 Register ..................................................................... 1024
7-283. ELM_SYNDROME_FRAGMENT_6_2 Register ..................................................................... 1025
7-284. ELM_SYNDROME_FRAGMENT_0_3 Register ..................................................................... 1026
7-285. ELM_SYNDROME_FRAGMENT_1_3 Register ..................................................................... 1027
7-286. ELM_SYNDROME_FRAGMENT_2_3 Register ..................................................................... 1028
7-287. ELM_SYNDROME_FRAGMENT_3_3 Register ..................................................................... 1029
7-288. ELM_SYNDROME_FRAGMENT_4_3 Register ..................................................................... 1030
11-35. Ping-Pong Buffering for McASP Example Pong PaRAM Configuration ......................................... 1631
11-36. Ping-Pong Buffering for McASP Example Ping PaRAM Configuration .......................................... 1632
11-37. Intermediate Transfer Completion Chaining Example .............................................................. 1633
11-38. Single Large Block Transfer Example ................................................................................ 1634
11-39. Smaller Packet Data Transfers Example............................................................................. 1634
11-40. PID Register ............................................................................................................. 1641
11-41. CCCFG Register ........................................................................................................ 1642
11-42. SYSCONFIG Register .................................................................................................. 1644
11-43. DCHMAP_0 to DCHMAP_63 Register ............................................................................... 1645
11-44. QCHMAP_0 to QCHMAP_7 Register ................................................................................ 1646
11-45. DMAQNUM_0 to DMAQNUM_7 Register............................................................................ 1647
11-46. QDMAQNUM Register.................................................................................................. 1652
11-47. QUEPRI Register........................................................................................................ 1655
11-48. EMR Register ............................................................................................................ 1656
11-49. EMRH Register .......................................................................................................... 1657
11-50. EMCR Register .......................................................................................................... 1658
11-51. EMCRH Register ........................................................................................................ 1659
11-52. QEMR Register .......................................................................................................... 1660
11-53. QEMCR Register ........................................................................................................ 1661
11-54. CCERR Register ........................................................................................................ 1662
11-55. CCERRCLR Register ................................................................................................... 1663
11-56. EEVAL Register ......................................................................................................... 1664
11-57. DRAE0 Register ......................................................................................................... 1665
11-58. DRAEH0 Register ....................................................................................................... 1666
11-59. DRAE1 Register ......................................................................................................... 1667
11-60. DRAEH1 Register ....................................................................................................... 1668
11-61. DRAE2 Register ......................................................................................................... 1669
11-62. DRAEH2 Register ....................................................................................................... 1670
11-63. DRAE3 Register ......................................................................................................... 1671
11-64. DRAEH3 Register ....................................................................................................... 1672
11-65. DRAE4 Register ......................................................................................................... 1673
11-66. DRAEH4 Register ....................................................................................................... 1674
11-67. DRAE5 Register ......................................................................................................... 1675
11-68. DRAEH5 Register ....................................................................................................... 1676
11-69. DRAE6 Register ......................................................................................................... 1677
11-70. DRAEH6 Register ....................................................................................................... 1678
11-71. DRAE7 Register ......................................................................................................... 1679
11-72. DRAEH7 Register ....................................................................................................... 1680
11-73. QRAE_0 to QRAE_7 Register ......................................................................................... 1681
11-74. Q0E0 Register ........................................................................................................... 1682
11-75. Q0E1 Register ........................................................................................................... 1683
11-76. Q0E2 Register ........................................................................................................... 1684
11-77. Q0E3 Register ........................................................................................................... 1685
11-78. Q0E4 Register ........................................................................................................... 1686
11-79. Q0E5 Register ........................................................................................................... 1687
11-80. Q0E6 Register ........................................................................................................... 1688
11-81. Q0E7 Register ........................................................................................................... 1689
11-82. Q0E8 Register ........................................................................................................... 1690
11-83. Q0E9 Register ........................................................................................................... 1691
18-8. Multiple Block Read Operation (MMC Cards Only) ................................................................ 4226
18-9. Multiple Block Write Operation (MMC Cards Only) ................................................................ 4226
18-10. Command Token Format ............................................................................................... 4227
18-11. 48-Bit Response Packet (R1, R3, R4, R5, R6) ...................................................................... 4227
18-12. 136-Bit Response Packet (R2) ........................................................................................ 4227
18-13. Data Packet for Sequential Transfer (1-Bit) ......................................................................... 4228
18-14. Data Packet for Block Transfer (1-Bit) ............................................................................... 4228
18-15. Data Packet for Block Transfer (4-Bit) ................................................................................ 4228
18-16. Data Packet for Block Transfer (8-Bit) ................................................................................ 4229
18-17. DMA Receive Mode ..................................................................................................... 4236
18-18. DMA Transmit Mode .................................................................................................... 4237
18-19. Buffer Management for a Write ........................................................................................ 4239
18-20. Buffer Management for a Read ....................................................................................... 4240
18-21. Busy Timeout for R1b, R5b Responses .............................................................................. 4243
18-22. Write CRC Status Timeout ............................................................................................. 4244
18-23. Read Data Timeout ..................................................................................................... 4244
18-24. Boot Acknowledge Timeout When Using CMD0 .................................................................... 4245
18-25. Boot Acknowledge Timeout When CMD Held Low ................................................................. 4245
18-26. Auto CMD12 Timing During Write Transfer .......................................................................... 4247
18-27. Auto Command 12 Timings During Read Transfer ................................................................. 4248
18-28. Output Driven on Falling Edge ........................................................................................ 4250
18-29. Output Driven on Rising Edge ......................................................................................... 4251
18-30. Boot Mode With CMD0 ................................................................................................. 4252
18-31. Boot Mode With CMD Line Tied to 0 ................................................................................. 4253
18-32. MMC/SD/SDIO Controller Software Reset Flow .................................................................... 4257
18-33. MMC/SD/SDIO Controller Bus Configuration Flow ................................................................. 4258
18-34. MMC/SD/SDIO Controller Card Identification and Selection - Part 1 ............................................ 4259
18-35. MMC/SD/SDIO Controller Card Identification and Selection - Part 2 ............................................ 4260
18-36. SD_SYSCONFIG Register ............................................................................................. 4262
18-37. SD_SYSSTATUS Register ............................................................................................. 4264
18-38. SD_CSRE Register ..................................................................................................... 4265
18-39. SD_SYSTEST Register ................................................................................................ 4266
18-40. SD_CON Register ....................................................................................................... 4270
18-41. SD_PWCNT Register ................................................................................................... 4274
18-42. SD_SDMASA Register ................................................................................................. 4275
18-43. SD_BLK Register........................................................................................................ 4276
18-44. SD_ARG Register ....................................................................................................... 4277
18-45. SD_CMD Register....................................................................................................... 4278
18-46. SD_RSP10 Register .................................................................................................... 4283
18-47. SD_RSP32 Register .................................................................................................... 4284
18-48. SD_RSP54 Register .................................................................................................... 4285
18-49. SD_RSP76 Register .................................................................................................... 4286
18-50. SD_DATA Register ..................................................................................................... 4287
18-51. SD_PSTATE Register .................................................................................................. 4288
18-52. SD_HCTL Register ...................................................................................................... 4291
18-53. SD_SYSCTL Register .................................................................................................. 4294
18-54. SD_STAT Register ...................................................................................................... 4296
18-55. SD_IE Register .......................................................................................................... 4301
18-56. SD_ISE Register ........................................................................................................ 4304
List of Tables
1-1. Device_ID (Address 0x44E10600) Bit Field Descriptions ........................................................... 174
2-1. L3 Memory Map ........................................................................................................... 177
2-2. L4_WKUP Peripheral Memory Map .................................................................................... 179
2-3. L4_PER Peripheral Memory Map....................................................................................... 180
2-4. L4 Fast Peripheral Memory Map ....................................................................................... 184
3-1. MPU Subsystem Clock Frequencies ................................................................................... 190
3-2. Reset Scheme of the MPU Subsystem ................................................................................ 191
3-3. ARM Core Supported Features ........................................................................................ 193
3-4. Overview of the MPU Subsystem Power Domain .................................................................... 194
3-5. MPU Power States ....................................................................................................... 195
3-6. MPU Subsystem Operation Power Modes ............................................................................ 196
4-1. PRU-ICSS Connectivity Attributes ...................................................................................... 202
4-2. PRU-ICSS Clock Signals ................................................................................................ 202
4-3. PRU-ICSS Pin List ........................................................................................................ 203
4-4. PRU-ICSS Internal Signal Muxing: pin_mux_sel[0] .................................................................. 204
4-5. PRU-ICSS Internal Signal Muxing: pin_mux_sel[1] .................................................................. 204
4-6. Local Instruction Memory Map .......................................................................................... 206
4-7. Local Data Memory Map ................................................................................................. 206
4-8. Global Memory Map ...................................................................................................... 207
4-9. PRU0/1 Constants Table ................................................................................................ 209
4-10. Real-Time Status Interface Mapping (R31) Field Descriptions ..................................................... 211
4-11. Event Interface Mapping (R31) Field Descriptions ................................................................... 212
4-12. PRU R31 (GPI) Modes ................................................................................................... 213
4-13. PRU GPI Signals and Configurations .................................................................................. 213
4-14. Effective Clock Values ................................................................................................... 216
4-15. PRU R30 (GPO) Modes ................................................................................................. 217
4-16. PRU GPO Signals and Configurations ................................................................................. 217
4-17. Effective Clock Values ................................................................................................... 218
4-18. MPY/MAC XFR ID ........................................................................................................ 220
4-19. MAC_CTRL_STATUS Register (R25) Field Descriptions ........................................................... 221
4-20. Scratch Pad XFR ID ...................................................................................................... 223
4-21. Scratch Pad XFR Collision & Stall Conditions ........................................................................ 223
4-22. PRU-ICSS System Events............................................................................................... 227
4-23. Industrial Ethernet Timer Mode Mapping .............................................................................. 234
4-24. Baud Rate Examples for 192-MHZ UART Input Clock and 16× Over-sampling Mode .......................... 244
4-25. Baud Rate Examples for 192-MHZ UART Input Clock and 13× Over-sampling Mode .......................... 244
4-26. UART Signal Descriptions ............................................................................................... 245
4-27. Character Time for Word Lengths ...................................................................................... 248
4-28. UART Interrupt Requests Descriptions ................................................................................ 252
4-29. Data Path Configuration Comparison .................................................................................. 255
4-30. Frame Structure ........................................................................................................... 257
4-31. TX CRC Programming Models .......................................................................................... 258
4-32. PRU R31: Receive Interface Data and Status (Read Mode) ....................................................... 263
4-33. RX L2 Status .............................................................................................................. 265
4-34. RX L2 XFR ID ............................................................................................................. 266
4-35. PRU R30: Transmit Interface ........................................................................................... 268
4-36. PRU R31: Command Interface (Write Mode) ......................................................................... 269
15-95. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ........................... 2483
15-96. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ............................................. 2485
15-97. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers .............................. 2487
15-98. ECAP Initialization for APWM Mode .................................................................................. 2489
15-99. ECAP1 Initialization for Multichannel PWM Generation with Synchronization .................................. 2491
15-100. ECAP2 Initialization for Multichannel PWM Generation with Synchronization................................. 2491
15-101. ECAP3 Initialization for Multichannel PWM Generation with Synchronization................................. 2491
15-102. ECAP4 Initialization for Multichannel PWM Generation with Synchronization................................. 2491
15-103. ECAP1 Initialization for Multichannel PWM Generation with Phase Control ................................... 2494
15-104. ECAP2 Initialization for Multichannel PWM Generation with Phase Control ................................... 2494
15-105. ECAP3 Initialization for Multichannel PWM Generation with Phase Control ................................... 2494
15-106. ECAP Registers ........................................................................................................ 2495
15-107. TSCTR Register Field Descriptions ................................................................................. 2496
15-108. CTRPHS Register Field Descriptions ............................................................................... 2497
15-109. CAP1 Register Field Descriptions ................................................................................... 2498
15-110. CAP2 Register Field Descriptions ................................................................................... 2499
15-111. CAP3 Register Field Descriptions ................................................................................... 2500
15-112. CAP4 Register Field Descriptions ................................................................................... 2501
15-113. ECCTL1 Register Field Descriptions ................................................................................ 2502
15-114. ECCTL2 Register Field Descriptions ................................................................................ 2504
15-115. ECEINT Register Field Descriptions ................................................................................ 2506
15-116. ECFLG Register Field Descriptions ................................................................................. 2507
15-117. ECCLR Register Field Descriptions ................................................................................. 2508
15-118. ECFRC Register Field Descriptions ................................................................................. 2509
15-119. REVID Register Field Descriptions .................................................................................. 2510
15-120. Quadrature Decoder Truth Table ................................................................................... 2517
15-121. EQEP Registers ........................................................................................................ 2532
15-122. QPOSCNT Register Field Descriptions ............................................................................. 2533
15-123. QPOSINIT Register Field Descriptions ............................................................................. 2534
15-124. QPOSMAX Register Field Descriptions............................................................................. 2535
15-125. QPOSCMP Register Field Descriptions ............................................................................ 2536
15-126. QPOSILAT Register Field Descriptions ............................................................................. 2537
15-127. QPOSSLAT Register Field Descriptions ............................................................................ 2538
15-128. QPOSLAT Register Field Descriptions ............................................................................. 2539
15-129. QUTMR Register Field Descriptions ................................................................................ 2540
15-130. QUPRD Register Field Descriptions ................................................................................ 2541
15-131. QWDTMR Register Field Descriptions .............................................................................. 2542
15-132. QWDPRD Register Field Descriptions .............................................................................. 2543
15-133. QDECCTL Register Field Descriptions ............................................................................. 2544
15-134. QEPCTL Register Field Descriptions ............................................................................... 2545
15-135. QCAPCTL Register Field Descriptions ............................................................................. 2547
15-136. QPOSCTL Register Field Descriptions ............................................................................. 2548
15-137. QEINT Register Field Descriptions .................................................................................. 2549
15-138. QFLG Register Field Descriptions ................................................................................... 2550
15-139. QCLR Register Field Descriptions ................................................................................... 2551
15-140. QFRC Register Field Descriptions................................................................................... 2552
15-141. QEPSTS Register Field Descriptions ............................................................................... 2553
15-142. QCTMR Register Field Descriptions ................................................................................ 2554
15-143. QCPRD Register Field Descriptions ................................................................................ 2555
22-8. Channel Status and User Data for Each DIT Block ................................................................ 4678
22-9. Transmit Bitstream Data Alignment ................................................................................... 4689
22-10. Receive Bitstream Data Alignment.................................................................................... 4691
22-11. MCASP Registers ....................................................................................................... 4710
22-12. REV Register Field Descriptions ...................................................................................... 4712
22-13. PWRIDLESYSCONFIG Register Field Descriptions ............................................................... 4713
22-14. PFUNC Register Field Descriptions .................................................................................. 4714
22-15. PDIR Register Field Descriptions ..................................................................................... 4715
22-16. PDOUT Register Field Descriptions .................................................................................. 4717
22-17. PDIN Register Field Descriptions ..................................................................................... 4719
22-18. PDCLR Register Field Descriptions .................................................................................. 4720
22-19. GBLCTL Register Field Descriptions ................................................................................. 4722
22-20. AMUTE Register Field Descriptions .................................................................................. 4724
22-21. DLBCTL Register Field Descriptions ................................................................................. 4726
22-22. DITCTL Register Field Descriptions .................................................................................. 4727
22-23. RGBLCTL Register Field Descriptions ............................................................................... 4728
22-24. RMASK Register Field Descriptions .................................................................................. 4730
22-25. RFMT Register Field Descriptions .................................................................................... 4731
22-26. AFSRCTL Register Field Descriptions ............................................................................... 4733
22-27. ACLKRCTL Register Field Descriptions.............................................................................. 4734
22-28. AHCLKRCTL Register Field Descriptions............................................................................ 4735
22-29. RTDM Register Field Descriptions .................................................................................... 4736
22-30. RINTCTL Register Field Descriptions ................................................................................ 4737
22-31. RSTAT Register Field Descriptions ................................................................................... 4739
22-32. RSLOT Register Field Descriptions ................................................................................... 4741
22-33. RCLKCHK Register Field Descriptions ............................................................................... 4742
22-34. REVTCTL Register Field Descriptions ............................................................................... 4743
22-35. XGBLCTL Register Field Descriptions ............................................................................... 4744
22-36. XMASK Register Field Descriptions .................................................................................. 4746
22-37. XFMT Register Field Descriptions .................................................................................... 4747
22-38. AFSXCTL Register Field Descriptions ............................................................................... 4749
22-39. ACLKXCTL Register Field Descriptions .............................................................................. 4750
22-40. AHCLKXCTL Register Field Descriptions ............................................................................ 4751
22-41. XTDM Register Field Descriptions .................................................................................... 4752
22-42. XINTCTL Register Field Descriptions ................................................................................ 4753
22-43. XSTAT Register Field Descriptions ................................................................................... 4755
22-44. XSLOT Register Field Descriptions ................................................................................... 4757
22-45. XCLKCHK Register Field Descriptions ............................................................................... 4758
22-46. XEVTCTL Register Field Descriptions ............................................................................... 4759
22-47. DITCSRA_0 to DITCSRA_5 Register Field Descriptions .......................................................... 4760
22-48. DITCSRB_0 to DITCSRB_5 Register Field Descriptions .......................................................... 4761
22-49. DITUDRA_0 to DITUDRA_5 Register Field Descriptions .......................................................... 4762
22-50. DITUDRB_0 to DITUDRB_5 Register Field Descriptions .......................................................... 4763
22-51. SRCTL_0 to SRCTL_5 Register Field Descriptions ................................................................ 4764
22-52. XBUF_0 to XBUF_5 Register Field Descriptions ................................................................... 4766
22-53. RBUF_0 to RBUF_5 Register Field Descriptions ................................................................... 4767
22-54. WFIFOCTL Register Field Descriptions .............................................................................. 4768
22-55. WFIFOSTS Register Field Descriptions .............................................................................. 4769
22-56. RFIFOCTL Register Field Descriptions .............................................................................. 4770
(1)
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(3)
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Chapter 1
SPRUH73Q – October 2011 – Revised December 2019
Introduction
1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing
See newly added SMA2 register, Section 9.3.1.77.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.RMII2_CRS_DV_MODE_SEL.
1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register
See Section 9.3.1.53, vtp_ctrl Register.
PG1.0: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 0.
PG2.x: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 1.
1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot
See Section 26.1.9.4, EMAC Boot Procedure and Errata Advisory 1.0.7.
PG1.0: Link speed is determined by CONTROL register bit 6 in the external ethernet PHY. Note that some
PHYs may not update this bit, as it is not necessary as described in the 802.3 specification.
PG2.x: Link speed is determined by reading the Auto-Negotiation Advertisement and Auto-Negotiation
Link Partner Base Page Ability registers in the external ethernet PHY.
1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants
See Section 9.3.1.49, efuse_sma Register.
PG1.0: EFUSE_SMA register value is not applicable. Value is always 0.
PG2.x: Added EFUSE_SMA description to distinguish package type and maximum ARM frequency of the
device.
Memory Map
(1)
The first 1MB of address space 0x0-0xFFFFF is inaccessible externally.
(2)
Ex/R/W – Execute/Read/Write.
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MPU
Integer Neon Subsystem
Core Core
ETMSOC
L1 I L1 D
32KB w/SED 32KB w/SED
ICE Crusher
128
AXI2OCP
ROM 275 MHz
64 AINTC System
176 KB 32
Interrupts
275 MHz
128 64
OCM RAM
(SRAM internal) I2ASYNC I2ASYNC
550 MHz 550 MHz MPU PLL
64 KB
128 64
CLK_M_OSC
T2ASYNC T2ASYNC Frm Master OSC
200 MHz 200 MHz
To L3 To L3
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3.1.1 Features
This section outlines the key features of the MPU subsystem:
• ARM Microprocessor
– Cortex-A8
– ARM Architecture version 7 ISA.
– 2-issue, in-order execution pipeline.
– L1 Instruction and Data Cache of 32KB, 4-way, 16-word line with 128-bit interface.
– Integrated L2 cache of 256 KB, 8-way, 16 word line, 128 bit interface to L1 along with ECC/Parity
supported.
– Includes the Neon Media coprocessor (NEON™) which implements the Advanced SIMD media
processing architecture.
– Includes the VFP coprocessor which implements the VFPv3 architecture and is fully compliant with
IEEE 754 standard.
– The external interface uses the AXI protocol configured to 128-bit data width.
– Includes the Embedded Trace Macrocell (ETM) support for non-invasive debugging.
– Implements the ARMv7 debug with watch-point and breakpoint registers and 32-bit Advanced
Peripheral Bus (APB) slave interface to CoreSight debug systems.
• AXI2OCP Bridge
– Support OCP 2.2.
– Single Request Multiple Data Protocol on two ports.
– Multiple targets, including three OCP ports (128-bit, 64-bit and 32-bit).
• Interrupt Controller
– Support up to 128 interrupt requests
• Emulation/Debug
– Compatible with CoreSight Architecture.
• Clock Generation
– Through PRCM
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Device
MPU subsystem
MPU_MSTANDBY
MPU_INTC_IRQ
MPU_INTC_FIQ
Device
modules
AXI
Interrupts
sys_nirq
PRCM
INTC
AXI
MOCP CORE_RST
(P)
AXI2OCP
L3_ICLK
MPU_RST
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All major modules inside the MPU subsystem are clocked at half the frequency of the ARM core. The
divider of the output clock can be programmed with the CM_DIV_M2_DPLL_MPU.DPLL_CLKOUT_DIV
register field, the frequency is relative to the ARM core. For details see Chapter 8, Power, Reset, and
Clock Management (PRCM).
The clock generator generates the following functional clocks:
ARM (ARM_FCLK): This is the core clock. It is the base fast clock that is routed internally to the ARM
logic and internal RAMs, including NEON, L2 cache, the ETM core (emulation), and the ARM core.
AXI2OCP Clock (AXI_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). The OCP
interface thus performs at one half the frequency of ARM.
Interrupt Controller Functional Clock (MPU_INTC_FCLK): This clock, which is part of the INTC
module, is half the frequency of the ARM clock (ARM_FCLK).
ICE-Crusher Functional Clock (ICECRUSHER_FCLK): ICE-Crusher clocking operates on the APB
interface, using the ARM core clocking. This clock is half the frequency of the ARM clock (ARM_FCLK).
I2Async Clock (I2ASYNC_FCLK): This clock is half the frequency of the ARM clock (ARM_FCLK). It
matches the OCP interface of the AXI2OCP bridge.
NOTE: The second half of the asynchronous bridge (T2ASYNC) is clocked directly by the PRCM
with the core clock. T2ASYNC is not part of the MPU subsystem.
Emulation Clocking: Emulation clocks are distributed by the PRCM module and are asynchronous to the
ARM core clock (ARM_FCLK) and can run at a maximum of 1/3 the ARM core clock.
Table 3-1 summarizes the clocks generated in the MPU subsystem by the MPU clock generator.
MPU subsystem
INTC_FCLK (ARM_FCLK/2)
INTC
AXI2OP_FCLK (ARM_FCLK/2)
AXI2OCP
MPU_CLK MPU I2ASYNC_FCLK (ARM_FCLK/2)
clock I2Async
generator
PRCM ICECRUSHER_FCLK (ARM_FCLK/2)
ICECrusher
ARM_FCLK
ARM Cortex-A8
EMU EMU_CLOCKS
Emulation/
DPLL trace/debug
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MPU subsystem
CORE_RST
INTC
MPU_RST
AXI2OCP
I2Async
PRCM
ARM Cortex-A8
NEON_RST
NEON
EMU_RST
EMU_RSTPWRON EMU
MPU_RSTPWRON
ICECrusher
For details about clocks, resets, and power domains, see Chapter 8, Power, Reset, and Clock
Management (PRCM).
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NOTE: The emulation domain and the core domain are not fully embedded in MPU subsystem.
MPU subsystem
MPU_RST
MPU domain
ARM Cortex™-A8
I2Async
AXI2OCP
SRAM L1
SRAM L2
MPU_RSTPWRON
IceCrusher
EMU_RSTPWRON
Emulation domain EMU_RST
NEON_RST
NEON domain
INTC
CORE_RST
Core domain
Power management requirements at the device level govern power domains for the MPU subsystem. The
device-level power domains are directly aligned with voltage domains and thus can be represented as a
cross reference to the different voltage domains.
Table 3-4 shows the different power domains of the MPU subsystem and the modules inside.
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NOTE: L1 and L2 array memories have separate control signals into the in MPU Subsystem, thus
directly controlled by PRCM For details on the physical power domains and the voltage
domains, see Chapter 8, Power, Reset, and Clock Management (PRCM).
CAUTION
The MPU L1 cache memory does not support retention mode, and its array
switch is controlled together with the MPU logic. For compliance, the L1
retention control signals exist at the PRCM boundary, but are not used. The
ARM L2 can be put into retention independently of the other domains.
Table 3-6 outlines the supported operational power modes. All other combinations are illegal. The ARM
L2, NEON, and ETM/Debug can be powered up/down independently. The APB/ATB ETM/Debug column
refers to all three features: ARM emulation, trace, and debug.
The MPU subsystem must be in a power mode where the MPU power domain, NEON power domain,
debug power domain, and INTC power domain are in standby, or off state.
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NOTE: The INTC SWAKEUP output is a pure hardware signal to PRCM for the status of its IDLE
request and IDLE acknowledge handshake.
NOTE: In debug mode, ICE-Crusher could prevent MPU subsystem from entering into IDLE mode.
NOTE: The core domain must be on, and reset, before the MPU can be reset.
2. Follow the reset sequence as described in the Basic Power-On Reset section.
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Chapter 4
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4.1 Introduction
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs), shared, data, and
instruction memories, internal peripheral modules, and an interrupt controller (INTC). The programmable
nature of the PRU, along with its access to pins, events and all SoC resources, provides flexibility in
implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces,
and in offloading tasks from the other processor cores of the system-on-chip (SoC).
Figure 4-1 shows the PRU-ICSS details.
The PRUs have access to all resources on the SoC through the Interface/OCP Master port, and the
external host processors can access the PRU-ICSS resources through the Interface/OCP Slave port. The
32-bit interconnect bus connects the various internal and external masters to the resources inside the
PRU-ICSS. The INTC handles system input events and posts events back to the device-level host CPU.
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the device-level
host CPU. This interaction between processors is determined by the nature of the firmware loaded into the
PRU’s instruction memories.
PRU-ICSS
Data Mem0
PRU0 Core (8KB)
(8KB Program)
Data Mem1
EGP IO MAC (8KB)
32-Bit Interconnect Bus
IEP
INTC UART0
CFG
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4.1.1 Features
The PRU-ICSS includes the following main features:
• Two PRUs each with:
– 8KB program memory
– 8KB data memory
– High Performance Interface/OCP Master port for accessing external memories
– Enhanced GPIO (EGPIO) with async capture and serial support
– Multiplier with optional accumulation (MPY/MAC)
• One scratch pad (SPAD) memory
– 3 Banks of 30 32-bit registers
• Broadside direct connect between PRU cores within subsystem
• 12 KB general purpose shared memory
• One Interrupt Controller (INTC)
– Up to 64 input events supported
– Interrupt mapping to 10 interrupt channels
– 10 Host interrupts (2 to PRU0 and PRU1, 8 output to chip level)
– Each system event can be enabled and disabled
– Each host event can be enabled and disabled
– Hardware prioritization of events
• 16 software events generated by 2 PRUs
• One Ethernet MII_RT module with two MII ports and configurable connections to PRUs*
• One MDIO Port*
• One Industrial Ethernet Peripheral (IEP) to manage/generate Industrial Ethernet functions
– One Industrial Ethernet timer with 10 capture* and eight compare events
– Two Industrial Ethernet sync signals*
– Two Industrial Ethernet 16-bit watchdog timers*
– Industrial Ethernet digital IOs
• One 16550-compatible UART with a dedicated 192-MHz clock, supporting up to 12Mbaud for
PROFIBUS DP
• One Enhanced Capture Module (ECAP)
• Flexible power management support
• Integrated 32-bit interconnect bus for connecting the various internal and external masters to the
resources inside the PRU-ICSS
• Interface/OCP Slave port for external masters to access PRU-ICSS memories
• Optional address translation for PRU transaction to External Host
• All memories within the PRU-ICSS support parity
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4.2 Integration
The device includes a Programmable Real-Time Unit Subsystem and Industrial Communication
Subsystem (PRU-ICSS) consisting of two independent Programmable Real-time Units (PRUs). Each PRU
is a 32-bit Load/Store RISC processor with dedicated memories. The PRU-ICSS integration is shown in
Figure 4-2.
pr1_mii_mr0_clk
Async
Interface/ pr1_mii0_rxdv
L4 Fast
OCP Slave port pr1_mii0_rxd3
pr1_mii0_rxd2
pr1_mii0_rxd1
pr1_mii0_rxd0
pr1_mdio_data
OCP_HP0 MII_RT pr1_mdio_mdclk
Bridge
Async
PRU0 Core
L3 Fast (Interface/OCP pr1_mii_mt1_clk
(8KB Program RAM) pr1_mii1_rxlink
Master port)
Data RAM0 pr1_mii1_crs
(8KB) pr1_mii1_col
pr1_mii1_rxer
pr1_mii1_txen
pr1_pru0_pru_r31[16:0] Enhanced pr1_mii1_txd3
MAC Data RAM1
pr1_pru0_pru_r30[15:0] GPIO pr1_mii1_txd2
32-bit Interconnect Bus (8KB) pr1_mii1_txd1
Scratch pr1_mii1_txd0
ocp_clk Pad pr1_mii_mr1_clk
Shared RAM pr1_mii1_rxdv
uart_clk (12KB)
PRCM iep_clk Clocks/Reset pr1_mii1_rxd3
rst_main_arst_n pr1_mii1_rxd2
pr1_mii1_rxd1
CFG pr1_mii1_rxd0
pr1_edio_sof
OCP_HP1 Industrial pr1_edio_latch_in
Bridge
Async
For the availability of all features, see the device features in Chapter 1, Introduction.
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PRU-ICSS
pr1_mii0_rxd[3:0]
0
mii0_rxd[3:0]
pr1_pru1_pru_r31[8:11]
1
pin_mux_sel[0]
pru1_r31_status[8:11]
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PRU-ICSS
pr1_pru1_pru_r30[5:0]
pru1_r30[5:0]
1
pr1_pru0_pru_r30[13:8]
pru0_r30[13:8]
0
pin_mux_sel[1]
pr1_pru1_pru_r31[5:0]
0
pru1_r31[5:0]
pr1_pru0_pru_r31[13:8]
1
pin_mux_sel[1]
pru0_r31[13:8]
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Functional Description www.ti.com
Attribute Value
IO Architecture Load / Store
Data Flow Architecture Register to Register
Core Level Bus Architecture
4-Bus Harvard (1 Instruction, 3 Data)
Type
32-Bit
Instruction I/F
32-Bit
Memory I/F 0
32-Bit
Memory I/F 1
Execution Model
Scalar
Issue Type
None (Purposefully)
Pipelining
In Order
Ordering
Unsigned Integer
ALU Type
Registers
30 (R1 – R30)
General Purpose (GP)
1 (R31)
External Status
1 (R0)
GP / Indexing
Bit, Byte (8-bit), Halfword (16-bit), Word (32-bit), Pointer
Addressability in Instruction
Addressing Modes
16-bit Immediate
Load Immediate
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The processor is based on a four-bus architecture which allows instructions to be fetched and executed
concurrently with data transfers. In addition, an input is provided in order to allow external status
information to be reflected in the internal processor status register. Figure 4-5 shows a block diagram of
the processing element and the associated instruction RAM/ROM that contains the code that is to be
executed.
Op4 iram_XXX
i_data[31:0]
R0 Decode and Control
R0
op1 Mux
R1 Instruction
... Output RAM/ROM
Shifter (Clocked)
R1 R30 Shift/Mask
R31 Program i_addr[31:0]
Counter
R2
R0
Destination Selector
const_base_sel[4:0]
op2 Mux
R1 ALU Constants
... Shift/Mask Data
... I/F Constants Table
Path
R30 const_base[31:0]
R31
R29
R0 Memory mem0_XXX
Shift/Mask
I/F
op3 Mux
R30 R1 mem1_XXX
...
R30
R31(Status) Coprocessor I/F regs_XXX
R31
Register Execution Unit
File
R31(Event)
Output
Multiplexers PRU Core PRU
status_in[31:0] events_out[31:0]
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NOTE: Addresses in constants entries 24–31 are partially programmable. Their programmable bit
field (for example, c24_blk_index[3:0]) is programmable through the PRU CTRL register
space. As a general rule, the PRU should configure this field before using the partially
programmable constant entries.
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PRU<n>
i
R30 GPO Content PR1_PRU<n>_PRU_R30[ i:0 ]
INTC INTC j
GPI Content
R31(R) status status PR1_PRU<n>_PRU_R31[ j:0 ]
(bits 29:0)
(bit 31) (bit 30)
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PRU0
R31(W) 5 3 2 1 0
4
D Q
EN
see
R31(W) 5 3 2 1 0
4
D Q
EN
Simultaneously writing a '1' to pru<n>_r31_vec_valid (R31 bit 5) and a channel number from 0-15 to
pru<n>_r31_vec[3:0] (R31 bits 3:0) creates a pulse on the output of the corresponding
pr1_pru_mst_intr[x]_intr_req INTC system event (Table 4-22). For example, writing '100000' will generate
a pulse on pr1_pru_mst_intr[0]_intr_req, writing '100001' will generate a pulse on
pr1_pru_mst_intr[1]_intr_req, and so on to where writing '101111' will generate a pulse on
pr1_pru_mst_intr[15]_intr_req and writing '0xxxxx' will not generate any system event pulses. The output
values from both PRU cores in a subsystem are ORed together.
The output channels 0-15 are connected to the PRU-ICSS INTC system events 16-31, respectively. This
allows the PRU to assert one of the system events 16-31 by writing to its own R31 register. The system
event is used to either post a completion event to one of the host CPUs (ARM) or to signal the other PRU.
The host to be signaled is determined by the system event to interrupt channel mapping (programmable).
The 16 events are named as pr1_pru_mst_intr<15:0>_intr_req. For more details, see Section 4.4.2,
Interrupt Controller (INTC).
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NOTE: Some devices may not pin out all 30 bits of R31. For which pins are available on this device,
see Section 4.2.3, PRU-ICSS Pin List. See the device's datasheet for device-specific pin
mapping.
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Figure 4-8. PRU R31 (GPI) Direct Input Mode Block Diagram
PRU<n>_R31
0
1
PRU<n>_GPI [0:29] …
30 28
29
Figure 4-9. PRU R31 (GPI) 16-Bit Parallel Capture Mode Block Diagram
PRU<n>_R31
16
PRU<n>_DATAIN 0
1
PRU<n>_CLOCKIN …
14
ocp_clk 15
Sync Flop 16
ocp_clk ocp_clk
Sync Flop Sync Flop
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The shift rate is controlled by the effective divisor of two cascaded dividers applied to the ocp_clk. These
cascaded dividers can each be configured through the PRU-ICSS CFG register space to a value of {1,
1.5, …, 16}. Table 4-14 lists sample effective clock values and the divisor values that can be used to
generate these clocks.
PRU<n>_R31
PRU<n>_DATAIN 0
27 …
27
28 (CNT_16)
28-bit shift register 29 (SB)
Bit Bucket
Bit 0 Bit 27
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NOTE: Some devices may not pin out all 32 bits of R30. For which pins are available on this device,
see Section 4.2.3, PRU-ICSS Pin List. See the device's datasheet for device-specific pin
mapping.
NOTE: R30 is not initialized after reset. To avoid unintended output signals, R30 should be
initialized before pinmux configuration of PRU signals.
Figure 4-11. PRU R30 (GPO) Direct Output Mode Block Diagram
PRU<n>_R30
0
PRU<n>_GPO[0:31]
1
… 32
31
Shift out mode uses two 16-bit shadow registers (gpo_sh0 and gpo_sh1) to support ping-pong buffers.
Each shadow register has independent load controls programmable through pru<n>_r30[29:30]
(PRU<n>_LOAD_GPO_SH [0:1]). While PRU<n>_LOAD_GPO_SH [0/1] is set, the contents of
pru<n>_r31[0:15] are loaded into gpo_sh0/1.
NOTE: If any device-level pins mapped to pru<n>_r30 [2:15] are configured for the pru<n>_r30
[2:15] pinmux mode, then these pins will reflect the shadow register value written to
pru<n>_r30. Any pin configured for a different pinmux setting will not reflect the shadow
register value written to pru<n>_r30.
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The data shift will start from the lsb of gpo_sh0 when pru<n>_r30[31] (PRU<n>_ENABLE_SHIFT) is set.
Note that if no new data is loaded into gpo_shn<n> after shift operation, the shift operation will continue
looping and shifting out the pre-loaded data. When PRU<n>_ENABLE_SHIFT is cleared, the shift
operation will finish shifting out the current shadow register, stop, and reset.
Figure 4-12. PRU R30 (GPO) Shift Out Mode Block Diagram
GP_SH0
16 16
PRU<n>_R30
0
1
… 16
PRU<n>_DATAOUT
15
… GP_SH1
29 (gp_sh0_load)
30 (gp_sh1_load)
31 (enable_shift)
16 16
NOTE: Until the shift operation is disabled, the shift loop will continue looping and shifting out the
pre-loaded data if no new data has been loaded into gpo_sh<n>.
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4.4.1.3.1 Features
• Configurable Multiply Only and Multiply and Accumulate functionality via PRU register R25
• 32-bit operands with direct connection to PRU registers R28 and R29
• 64-bit result (with carry flag) with direct connection to PRU registers R26 and R27
• PRU broadside interface and XFR instructions (XIN, XOUT) allow for importing multiplication results
and initiating accumulate function
XIN R27
Upper 32 bit product R27
Upper product
R28 Auto-sampled
R28 32-bit operands:
Operand Sampled every clock.
In MAC mode, the product
R29 Auto-sampled of R28*R29 will be added
R29 to the accumulator on
Operand
every XOUT of R25.
MPY/MAC
The XFR instructions (XIN and XOUT) are used to load/store register contents between the PRU core and
the MAC. These instructions define the start, size, direction of the operation, and device ID. The device ID
number corresponding to the MPY/MAC is shown in Table 4-18.
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The PRU register R25 is mapped to the MAC_CTRL_STATUS register (Table 4-19). The MAC’s current
status (MAC_mode and ACC_carry states) is loaded into R25 using the XIN command on R25. The PRU
sets the MAC’s mode and clears the ACC_carry using the XOUT command on R25.
The two 32-bit operands for the multiplication are loaded into R28 and R29. These registers have a
direction connection with the MAC, and the MAC samples these registers every clock cycle. Note, XOUT
is not required to load the MAC. In multiply and accumulate mode, the product of R28*R29 is added to the
accumulator on every XOUT of R25.
The product from the MAC is linked to R26 (lower 32 bits) and R27 (upper 32 bits). The product is loaded
into register R26 and R27 using XIN.
32-bit operand 32-bit operand Upper 32-bit product Lower 32-bit product
Multiply mode :
sampled every clock cycle XIN
MAC
The following steps are performed by the PRU firmware for multiply-only mode:
1. Enable multiply only MAC_mode.
a. Clear R25[0] for multiply only mode.
b. Store MAC_mode to MAC using XOUT instruction with the following parameters:
• Device ID = 0
• Base register = R25
• Size = 1
2. Load operands into R28 and R29.
3. Delay at least 1 PRU cycle before executing XIN in step 4.
4. Load product into PRU using XIN instruction on R26, R27.
Repeat steps 2 through 4 for each new operand.
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32-bit operand 32-bit operand Upper 32-bit product Lower 32-bit product
The following steps are performed by the PRU firmware for multiply and accumulate mode:
1. Enable multiply and accumulate MAC_mode.
a. Set R25[1:0] = 1 for accumulate mode.
b. Store MAC_mode to MAC using XOUT instruction with the following parameters:
• Device ID = 0
• Base register = R25
• Size = 1
2. Clear accumulator and carry flag.
a. Set R25[1:0] = 3 to clear accumulator (R25[1]=1) and preserve accumulate mode (R25[0]=1).
b. Store accumulator to MAC using XOUT instruction on R25.
3. Load operands into R28 and R29.
4. Multiply and accumulate, XOUT R25[1:0] = 1
Repeat step 4 for each multiply and accumulate using same operands.
Repeat step 3 and 4 for each multiply and accumulate for new operands.
5. Load the accumulated product into R26, R27 and the ACC_carry status into R25 using the XIN
instruction.
Note: Steps one and two are required to set the accumulator mode and clear the accumulator and carry
flag.
4.4.1.4.1 Features
The PRU-ICSS scratch pad supports the following features:
• Three scratch pad banks of 30, 32-bit registers (R29:0)
• Flexible load/store options
– User-defined start byte and length of the transfer
– Length of transfer ranges from one byte of a register to the entire register content (R29 to R0)
– Simultaneous transactions supported between PRU0 ↔ Bank<n> and PRU1 ↔ Bank<m>
– Direct connection of PRU0 → PRU1 or PRU1 → PRU0 for all registers R29–R0
• XFR instructions operate in one clock cycle
• Optional XIN/XOUT shift functionality allows remapping of registers (R<n> → R<m>) during load/store
operation
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Bank0
R0
R1
R2
…
R28
R29
broadside interface
broadside interface
PRU0 Bank1 PRU1
R0 R0 R0
R1 R1 R1
R2 R2 R2
… … …
R28 R28 R28
R29 R29 R29
Bank2
R0
R1
R2
…
R28
R29
A collision occurs when two XOUT commands simultaneously access the same asset or device ID.
Table 4-21 shows the priority assigned to each operation when a collision occurs. In direct connect mode
(device ID 14), any PRU transaction will be terminated if the stall is greater than 1024 cycles. This will
generate the event pr1_xfr_timeout that is connected to INTC.
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Table 4-21. Scratch Pad XFR Collision & Stall Conditions (continued)
PRU<m> XIN (←) PRU<n> Direct Connect mode requires the transmitting core (PRU<n>) to
execute XOUT and the receiving core (PRU<m>) to execute
XIN. If PRU<m> executes XIN before PRU<n> executes XOUT,
then PRU<m> will stall until either PRU<n> executes XOUT or
the stall is greater than 1024 cycles.
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PRU0/1 Sys_event 1
R31 bit 30 Host-0 Channel-0
PRU0/1 Sys_event 2 Peripheral A
Host-1 Channel-1
R31 bit 31
Host-2 Channel-2
Host-3 Channel-3
Host-4 Channel-4
Host-6 Sys_event 31
Channel-6
Host-8 Channel-8
Peripheral Z
Host-9 Channel-9
Sys_event 58
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(1)
MII_RT mode is selected through the MII_RT register in the PRU-ICSS0 CFG register space.
(2)
Signals 63-56 and 31-0 for MII_RT Mode are the same as for Standard Mode.
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The INTC encompasses many functions to process the system events and prepare them for the host
interface. These functions are: processing, enabling, status, channel mapping, host interrupt mapping,
prioritization, and host interfacing. Figure 4-18 illustrates the flow of system events through the functions
to the host. The following subsections describe each part of the flow.
System
Status Enabling Processing
Interrupts
Prioritization
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4.4.3.2.1 Features
The industrial ethernet timer supports the following features:
• One master 32-bit count-up counter with an overflow status bit
– Runs on iep_clk or ocp_clk
– Write 1 to clear status
– Supports a programmable increment value from 1 to 16 (default 5)
– An optional compensation method allows the increment value to apply a compensation increment
value from 1 to 16, counting up to 2^24 iep_clk/ocp_clk events
• Ten 32-bit capture registers (CAPR[5:0], CAPR[7:6], CAPF[7:6])
– Eight capture inputs with optional synchronous or asynchronous mode
• Six rise-only capture inputs (CAPR[5:0])
• Two rise-and-fall capture inputs:
• CAPR[7] and CAPF[7]
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4.4.3.4.1 Features
The industrial ethernet sync block supports the following features:
• Two synchronize generation signals (SYNC0, SYNC1)
– Activation time synchronized with IEP Timer
• CMP[1] triggers SYNC0 activation time
• CMP[2] triggers SYNC1 activation time (only valid in the independent mode)
– Pulse width defined by registers or ack mode (remain asserted until software acknowledged)
– Cyclic or single-shot operation
– Option to enable or disable sync generation
• Programmable number of clock cycles between the start of SYNC0 to the start of SYNC1
Cyclic generation
SYNC0
Defined by SYNC_START
Single shot
SYNC0
Acknowledge
Cyclic generation
with acknowledgement
SYNC0
Acknowledge
Single shot
with acknowledgement
SYNC0
In SYNC1 dependent mode (SYNC_CTRL.sync1_ind_en = 0), SYNC1 depends on SYNC0 and the start
time of the SYNC1 can be defined by the SYNC1_DELAY register. Figure 4-21 shows different examples
when changing the value in the SYNC1_DELAY register. Note if the SYNC1 delay time is 0, SYNC1
reflects SYNC0.
Cyclic generation cannot be used for network time synchronized applications because only the
CMP1/CMP2 hit occurs in the compensated time domain.
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Cyclic generation
SYNC0 : Start time
with Acknowledge Activation
Acknowledge
Field Value
SYNC0_CYCLIC_EN 1
SYNC0_ACK_EN 1
SYNC_START SYNC0_PERIOD
Single shot
SYNC0 : Start time
with Acknowledge Activation
Acknowledge
Field Value
SYNC0_CYCLIC_EN 0
SYNC0_ACK_EN 1
SYNC_START
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4.4.3.5.1 Features
The industrial ethernet watchdog timer supports the following features:
• One 32-bit pre-divider for generating a WD clock (default 100μs) based on iep_clk input
• Two 16-bit Watchdog Timers:
– PDI_WD for Sync Managers WD, used in conjunction with digital input/output (DIGIO)
– PD_WD for data link layer user WD, used in conjunction with data link layer or application layer
interface actions
4.4.3.6.1 Features
The industrial ethernet digital I/O supports the following features:
• Digital data output
– 32 channels (pr1_edio_data_out[31:0])
– Five event options for driving output data output:
• End of frame event (PRU0/1_RX_EOF)
• SYNC0 events
• SYNC1 events
• Watchdog trigger
• Software enable
• Digital data out enable (optional tri-state control)
• Digital data input
– 32 channels (pr1_edio_data_in[31:0])
– DIGIO_DATA_IN_RAW supports direct sampling of pr1_edio_data_in
– DIGIO_DATA_IN supports four event options to trigger sampling of pr1_edio_data_in:
• Start of frame event in start of frame (SOF) mode
• pr1_edio_latch_in event
• SYNC0 events
• SYNC1 events
NOTE: Some devices may not pin out all 32 data I/O signals. For which data pins are available on
this device, see Table 4-3, PRU-ICSS Pin List.
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SYNC0 EN
SYNC_PWIDTH
SYNC0_PERIOD SYNC1
SYNC1_DELAY
SYNC0/1
(1) Register
(2) Internal signal wire
(3) External pin input/output
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Figure 4-23 shows the signals and registers for driving the DIGIO data out. The pr1_edio_data_out is
immediately forced to zero when OUTVALID_MODE = 1, pr1_edio_oe_ext = 1, and PD_WD_EXP = 1, or
the next update hardware post PD_WD_EXP. Delay assertion of pr1_edio_outvalid from
pr1_edio_data_out update events are controlled by software (SW_OUTVALID).
OUTVALID_OVR_EN
Delay function pr<k>_edio_outvalid
SW_OUTVALID
OUTVALID_DLY
OUT_MODE
RX_EOF
PRU<0/1> pr<k>_edio_data_out
SYNC0 DATA_OUT D Q
SYNC_PWIDTH
SYNC0_PERIOD EN
SYNC1
SYNC1_DELAY
SYNC0/1
SW_DATA_OUT_UPDATE
OUTVALID_MODE
WatchDog Timer
pr1_edio_oe_ext
32-bit WD_PREDIV
pd_wd_exp
16-bit PD_WD Timing
DATA_OUT_EN pr<k>_edio_data_out_en
16-bit PDI_WD WD_MODE Function
(1) Register
(2) Internal signal wire
(3) External pin input/output
Follow these steps to configure and write to the DIGIO Data Output.
1. Pre-configure DIGIO by setting DIGIO_EXP.OUTVALID_OVR_EN and
DIGIO_EXP.SW_DATA_OUT_UPDATE
2. Write to DIGIO_DATA_OUT to configure output data
3. To Hi-Z output, set DIGIO_DATA_OUT_EN (clear DIGIO_DATA_OUT_EN to drive value stored in
DIGIO_DATA_OUT)
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4.4.4.1 Introduction
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S
e
l 8 Receiver 8
e FIFO
8
c
t
16
Receiver
Line Timing and
Control Control
Register
Divisor
Latch (LS) 16 Baud
Divisor Generator
Latch (MS)
Line Transmitter
Status Timing and
Register Control
8 Transmitter 8 S
FIFO e
l
Transmitter 8 e 8 Transmitter UARTn_TXD
Holding c Shift
t Register signal
Register
Modem
8 Control
Control
Logic
Register
Interrupt 8 Interrupt/
Enable Event Interrupt to CPU
Register Control
Logic
Event to DMA controller
Interrupt 8
Identification
Register Power and
Emulation
Control
FIFO Register
Control
Register
NOTE: The value n indicates the applicable UART where there are multiple instances. For the PRU-ICSS, there is
only one instance and all UART signals should reflect this (e.g., UART0_TXD instead of UARTn_TXD).
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Two 8-bit register fields (DLH and DLL), called divisor latches, hold this 16-bit divisor. DLH holds the most
significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about
these register fields, see the UART register descriptions. These divisor latches must be loaded during
initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor
latches results in two wait states being inserted during the write access while the baud generator is loaded
with the new value.
Figure 4-26 summarizes the relationship between the transferred data bit, BCLK, and the UART input
clock. Note that the timing relationship depicted in Figure 4-26 shows that each bit lasts for 16 BCLK
cycles . This is in case of 16x over-sampling mode. For 13× over-sampling mode each bit lasts for 13
BCLK cycles .
Example baud rates and divisor values relative to a 192-MHz UART input clock and 16× over-sampling
mode are shown in Table 4-24.
PRU-ICSS
UART
Receiver
DLH:DLL timing and
control
Transmitter
timing and
control
Other logic
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Figure 4-26. Relationships Between Data Bit, BCLK, and UART Input Clock
n UART input clock cycles, where n = divisor in DLH:DLL
BCLK
BCLK
UARTn_TXD,
D1 D2
UARTn_RXD
D0
Table 4-24. Baud Rate Examples for 192-MHZ UART Input Clock and 16× Over-sampling Mode
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 5000 2400 0.00
4800 2500 4800 0.00
9600 1250 9600 0.00
19200 625 19200 0.00
38400 313 38338.658 -0.16
56000 214 56074.766 0.13
128000 94 127659.574 -0.27
300000 40 300000 0.00
Table 4-25. Baud Rate Examples for 192-MHZ UART Input Clock and 13× Over-sampling Mode
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 6154 2399.940 -0.0025
4800 3077 4799.880 -0.0025
9600 1538 9602.881 0.03
19200 769 19205.762 0.03
38400 385 38361.638 -0.10
56000 264 55944.056 -0.10
128000 115 128428.094 0.33
300000 49 301412.873 0.47
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4.4.4.2.4.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits
4.4.4.2.4.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Receiver section control is a function of the
UART line control register (LCR). Based on the settings chosen in LCR, the UART receiver accepts the
following from the transmitting device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
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1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1, 1.5, 2)
It transmits 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if
parity is selected; and 1, 1.5, or 2 STOP bits, depending on the STOP bit selection.
The UART receives in the following format:
1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + 1 STOP bit
It receives 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if
parity is selected; and 1 STOP bit.
The protocol formats are shown in Figure 4-27.
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4.4.4.2.5 Operation
4.4.4.2.5.1 Transmission
The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART
transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits
THR receives data from the internal data bus, and when TSR is ready, the UART moves the data from
THR to TSR. The UART serializes the data in TSR and transmits the data on the UARTn_TXD pin.
In the non-FIFO mode, if THR is empty and the THR empty (THRE) interrupt is enabled in the interrupt
enable register (IER), an interrupt is generated. This interrupt is cleared when a character is loaded into
THR or the interrupt identification register (IIR) is read. In the FIFO mode, the interrupt is generated when
the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or IIR is
read.
4.4.4.2.5.2 Reception
The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR).
When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16× receiver
clock. Receiver section control is a function of the UART line control register (LCR). Based on the settings
chosen in LCR, the UART receiver accepts the following from the transmitting device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
RSR receives the data bits from the UARTn_RXD pin. Then RSR concatenates the data bits and moves
the resulting value into RBR (or the receiver FIFO). The UART also stores three bits of error status
information next to each received character, to record a parity error, framing error, or break.
In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabled
in the interrupt enable register (IER), an interrupt is generated. This interrupt is cleared when the character
is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level
selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the
trigger level.
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Device Off-chip
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UARTn_RTS
Start Bits0−7 Stop Start Bits 0−7 Stop Start Bits 0−7 Stop
UARTn_TXD
UARTn_CTS
(1) When UARTn_CTS is active (low), the transmitter keeps sending serial data out.
(2) When UARTn_CTS goes high before the middle of the last STOP bit of the current byte, the transmitter
finishes sending the current byte but it does not send the next byte.
(3) When UARTn_CTS goes from high to low, the transmitter begins sending data again.
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4.4.4.2.7 Initialization
The following steps are required to initialize the UART:
1. Perform the necessary device pin multiplexing setup (see your device-specific data manual).
2. Set the desired baud rate by writing the appropriate clock divisor values to the divisor latch registers
(DLL and DLH).
3. If the FIFOs will be used, select the desired trigger level and enable the FIFOs by writing the
appropriate values to the FIFO control register (FCR). The FIFOEN bit in FCR must be set first, before
the other bits in FCR are configured.
4. Choose the desired protocol settings by writing the appropriate values to the line control register
(LCR).
5. If autoflow control is desired, write appropriate values to the modem control register (MCR). Note that
all UARTs do not support autoflow control; see your device-specific data manual for supported
features.
6. Choose the desired response to emulation suspend events by configuring the FREE bit, and enable
the UART by setting the UTRST and URRST bits in the power and emulation management register
(PWREMU_MGMT).
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IER(ERBI)
RTOINT Arbiter UART interrupt
request to CPU
Receiver time-out
Overrun error
Parity error RLSINT
Framing error IER(ELSI)
Break
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4.4.5 ECAP
The PRU ECAP module within the PRU-ICSS is identical to the ECAP module in the AM335x PWMSS.
For additional details about the ECAP module, see Section 15.3, Pulse-Width Modulation Subsystem
(PWMSS).
4.4.6 MII_RT
4.4.6.1 Introduction
The Real-time Media Independent Interface (MII_RT) provides a programmable I/O interface for the PRUs
to access and control up to two MII ports. The MII_RT module can also be configured to push and pull
data independent of the PRU cores.
NOTE: To ensure the MII_RT IO timing values published in the device data manual, the ocp_clk
must be configured for 200 MHz (default value) and the TX_CLK_DELAY bit field in the
PRUSS_MII_RT_TXCFG0/1 register must be configured as follows:
• 100 Mbps mode: 6h (non-default value)
• 10 Mbps mode: 0h (default value)
4.4.6.1.1 Features
The PRU-ICSS MII_RT module supports:
• Two MII ports
– Each MII port has:
• 32-byte RX L1 FIFO
• 64-byte RX L2 buffer
• 64-byte TX L1 FIFO
– Rate decoupling on TX L1 FIFO
– Configurable pre-amble removal on RX L1 FIFO and insertion on TX L1 FIFO
– Configurable TX L1 FIFO trigger (10 bits with 40 ns ticks)
• MII port multiplexer per direction to support line/ring structure
– Link detection through RX_ERR
• Cyclic redundancy check (CRC)
– CRC32 generation on TX path
– CRC32 checker on RX path
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PRU0
PRU1
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Bank 0
32 bytes of data XFR
PRU
Bank 1
32 bytes of data
RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
PRU
RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
Bank 0
32 bytes of data XFR Memory
PRU
Bank 1
32 bytes of data
RX L1 TX L1
RX_DV TX_DATA
MII RX port FIFO 32 bytes FIFO 64 bytes MII TX port
RX_CLK TX_EN
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The data following the SFD is formatted in a 4-bit nibble structure. Figure 4-37 illustrates the nibble order.
The MSB arriving first is on the LSB side of a nibble. When receiving data, the MII_RT receive logic will
wait for the next nibble to arrive before constructing a byte and delivering to the PRU.
LSB MSB
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D0 D1 D2 D3
Constructing a byte and LSB MSB LSB MSB
sent to PRU and TX L1 FIFO
First Nibble Second Nibble
R30 (W):
TX Interface Data
R31 (R):
Data
RX Interface
R31 (W):
RX & TX cmd Interface
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pop push
(R31 cmd) (R31 cmd)
FIFO 32 bytes
FIFO 64 bytes
RX L1 TX L1
NOTE: If “auto-generation of preamble” option is used (i.e. with the first push of payload into the TX
FIFO the preamble is inserted into the TX FIFO automatically), then the first push of payload
must be a byte push (i.e. TX_PUSH8). If you push a word first, the CRC is not calculated
correctly.
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This submodule also keeps track of a running count of receive error events within a 10 μs error detection
window, as shown in Figure 4-44. The INTC is notified when 32 or more events have occurred in a 10 μs
error detection window. The error detection window is not a sliding window but a non-overlapping window
with no specific initialization time with respect to incoming traffic. The timer starts its 10 μs counts
immediately after de-assertion of reset to the MII_RT module.
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(A)
10 μs
(B)
A There are fewer than 32 consecutive error events in the 10 μs window. The detection module will not forward to the
interrupt controller (INTC).
B There are more or equal to 32 error events in the 10 μs window. The detection module will notify the interrupt
controller (INTC).
PRU
R31
RX L1
RX_DV
MII RX port FIFO 32 bytes
RX_CLK
When the new data is received, the PRU is provided with up to two bytes at a time in the R31 register, as
shown in Figure 4-46. Once the PRU processes the incoming data, it instructs the MII_RT by writing to the
R31 command interface bits to pop one or two bytes of data from the 32-byte RX FIFO. The pop operation
causes current contents of R31 to be refreshed with new data from the incoming packet. Each time the
data is popped, the status bits change to indicate so. If the pop is completed and there is no new data, the
status bits immediately change to indicate no new data. Note the current R31 content, including data, will
be lost after issuing the pop operation. If this information needs to be accessed later, the PRU should
store the existing R31 content before popping new data.
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RESERVED
<ERR> bits
FIFO ERROR_CRC
ERROR_NIBBLE
RX_SOF
MII RX_DV
RX_SFD
MII RX_CLK
RX_EOF
RX_ERROR
WORD_RDY
BYTE_RDY
DATA_RDY
Table 4-32 describes the receive interface data and status contents provided by the R31 register. These
contents are available when R31 is read. To configure this register, the PRU GPI mode should be set for
MII_RT mode in the CFG register space. Note the following:
1. If the data from the receive path is not read in time, it could cause an overflow event because the data
is still continuously provided to the 32-byte receive FIFO. Due to the receive FIFO overflow, the data
gets automatically discarded to avoid lack of space in the FIFO. At the same time, an interrupt is raised
to the INTC through a system event (PRU<n>_RX_OVERFLOW). To detect an overflow condition, the
PRU should poll for this system event condition, and a RX RESET command through the R31
command interface is required to clear out from this condition. The received Ethernet frame is
corrupted and should not be used for further processing, as bytes have been dropped due to the
overflow condition. A FIFO reset is recommended.
2. The receive data in the R31 register is available following synchronization to the PRU clock domain.
So, there is a finite delay (120 ns) when data is available from MII interface and it is accessible to the
PRU.
3. The receive FIFO also has the capability to be reset through software. When reset, all contents of
receive FIFO are purged and it may result in the current frame not being received as expected. When
a frame is being received and the PRU resets the RX FIFO, the remaining frame is not placed into the
RX FIFO. However, any new frame arriving on the receive MII port will be stored in the FIFO.
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Table 4-32. PRU R31: Receive Interface Data and Status (Read Mode)
Bits Field Name Description
31:30 RESERVED In case of register interface, these bits are provided to PRU by other
modules in PRU-ICSS. From the MII_RT module point of view, these
bits are always zero.
29 RX_MIN_FRM_CNT_ERR RX_MIN_FRM_CNT_ERR is set to 1 when the count of total bytes of
incoming frame is less than the value defined by RX_MIN_FRM_CNT.
RX_MIN_FRM_CNT_ERR is cleared by RX_ERROR_CLR.
28 RX_MAX_FRM_CNT_ERR RX_MAX_FRM_CNT_ERR is set to 1 when the count of total bytes of
incoming frame is more than the value defined by
RX_MAX_FRM_CNT_ERR. RX_MAX_FRM_CNT_ERR is cleared by
RX_ERROR_CLR.
27 RX_EOF_ERROR RX_EOF_ERROR is set to 1 when an RX_EOF event or RX_ERROR
event occurs. RX_EOF_ERROR is cleared by RX_ EOF_CLR and/or
RX_ ERROR_CLR.
26 RX_MAX_PRE_CNT_ERR RX_MAX_PRE_CNT_ERR is set to 1 when the number of nibbles
equaling 0x5 before SFD event (0x5D) is more than the value defined by
RXPCNT0/1 [RX_MAX_PRE_CNT]. RX_MAX_PRE_CNT_ERR is
cleared by RX_ERROR_CLR.
25 RX_ERR RX_ERR is set to 1 when pr1_mii0/1_rxer is asserted while
pr1_mii0/1_rxdv bit is set. RX_ERR is cleared by RX_ERROR_CLR.
24 ERROR_CRC ERROR_CRC indicates that the frame has a CRC mismatch. This bit is
valid when the RX_EOF bit is set. It should be noted that ERROR_CRC
bit is ready in early status, which means it is calculated before data is
available in RXL1 FIFO. ERROR_CRC is cleared by RX_ERROR_CLR.
23 ERROR_NIBBLE ERROR_NIBBLE indicates that the frame ended in odd nibble. It should
be considered valid only when the RX_EOF bit and pr1_mii0/1_rxdv are
set. Nibble counter is enabled post SFD event. It should be noted that
ERROR_NIBBLE bit is ready in early status, which means it is
calculated before data is available in RXL1 FIFO. ERROR_NIBBLE is
cleared by RX_ERROR_CLR.
22 RX_SOF RX_SOF transitions from low to high when the frame data starts to
arrive and pr1_mii0/1_rxdv is asserted. Note there will be a small sync
delay of 0ns – 5ns. The PRU must write one to this bit through the R31
command interface to clear it. The recommended time to clear this bit is
at the end of frame (EOF). It should be noted that RX_SOF bit is ready
in early status, which means it is calculated before data is available in
RXL1 FIFO.
21 RX_SFD RX_SFD transitions from low to high when the SFD sequence (0x5D)
post RX_SOF is observed on the receive MII data. The PRU must write
one to this bit through the R31 command interface to clear it. The
recommended time to clear this bit is at the end of frame (EOF). It
should be noted that RX_SFD bit is ready in early status, which means it
is calculated before data is available in RXL1 FIFO.
20 RX_EOF RX_EOF indicates that the frame has ended and pr1_mii0/1_rxdv is de-
asserted. It also validates the CRC match bit. Note there will be a small
sync delay of 0ns – 5ns. The PRU must write one to clear this bit in the
R31 command interface at the end of the frame. It should be noted that
RX_EOF bit is ready in early status, which means it is calculated before
data is available in RXL1 FIFO.
19 RX_ERROR RX_ERROR indicates one or more of the following errors occurred:
• RX_MAX/MIN_FRM_CNT_ERR
• RX_MAX/MIN_PRE_CNT_ERR
• RX_ERR
RX_ERROR is cleared by RX_ERROR_CLR.
18 WORD_RDY WORD_RDY indicates that all four nibbles in R31 have valid data. There
is a 2 clock cycle latency from the command RX_POP16 to
WORD_RDY update. Therefore, firmware needs to insure it does not
read WORD_RDY until 2 clock cycles after RX_POP16.
17 BYTE_RDY BYTE_RDY indicates that the lower two nibbles in R31 have valid data.
There is a 2 clock cycle latency from the command RX_POP8 to
BYTE_RDY update. Therefore, PRU firmware needs to insure it does
not read BYTE_RDY until 2 clock cycles after RX_POP8.
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Table 4-32. PRU R31: Receive Interface Data and Status (Read Mode) (continued)
Bits Field Name Description
16 DATA_RDY DATA_RDY indicates there is valid data in R31 ready to be read. This
bit goes to zero when the PRU does a POP8/16 and there is no new
data left in the receive MII port. This bit is high if there is more receive
data for PRU to read. There is a 2 clock cycle latency from the
command RX_POP16/8 to WORD_RDY/BYTE_RDY update. Therefore,
PRU firmware must einsure it does not read BYTE_RDY/WORD_RDY
until 2 clock cycles after RX_POP16/8.
15:8 BYTE1 Data Byte 1. This data is available such that it is safe to read by the
PRU when the DATA_RDY/BYTE_RDY/WORD_RDY bits are asserted.
7:0 BYTE0 Data Byte 0. This data is available such that it is safe to read by the
PRU when the DATA_RDY/BYTE_RDY/WORD_RDY bits are asserted.
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PRU
RX L2
Bank 0 R2
32 bytes of data XFR …
R13
Bank 1
32 bytes of data R18
R31
RX L1
RX_DV
MII RX port FIFO 32 bytes
RX_CLK
The 64-byte RX L2 buffer is divided into two 32 byte banks, or ping/pong buffers. When the RX L2 is
enabled, the incoming data from the MII RX port will transmit first to the 32 byte RX L1 FIFO. RX L1
pushes data into RX L2, starting when the first byte is ready until the final EOF marker. The RX L2 buffer
does not apply any backpressure to the RX L1 FIFO. Therefore, it is the PRU firmware’s responsibility to
fetch the data in RX L2 before it is overwritten by the cyclic buffer. The RX L1 will remain near empty, with
only one byte (nibble) stored.
Each RX L2 bank holds up to 32 bytes of data, and every four nibbles (or 16 bits) of data has a
corresponding 8-bit status. The data and status information are stored in packed arrays. In each bank, R2
to R9 contains the data packed array and R10 to R13 contains the status packed array. Figure 4-48
shows the relationship of the data registers and status registers. The RX L2 status registers record status
information about the received data, such as ERROR_CRC, RX_ERROR, STATUS_RDY, etc. The RX L2
status register details are described in Table 4-33. Note RX_RESET clears all Data and Status elements
and resets R18.
Data Register R2 R3 R4 R5 R6 R7 R8 R9
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Bank 0 and Bank 1 are used as ping/pong buffers. RX L2 supports the reading of a write pointer in R18
that allows software to determine which bank has active write transactions, as well as the specific write
address within packed data arrays.
The PRU interacts with the RX L2 buffer using the high performance XFR read instructions and broadside
interface. Table 4-34 shows the device XFR ID numbers for each bank.
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XFR read transactions are passive and have no effect on any status or other states in RX L2. The
firmware can also read R18 to determine which bank has active write transactions, and the location of the
transaction. With this information, the firmware can read multiple times the stable preserved data. When
RX L1 data is written to RX L2, the next status byte gets cleared at the same time the current status byte
gets updated. The rest of the status buffer is persistent. When the software accesses any register of the
ping/pong buffer, the software must issue an XFER read transaction to fetch the latest or current state of
the ping/pong buffer. The PRU registers do not reflect the current snapshot of L2 unless an XFER is
issued by the software.
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PRU
R30
R31
TX L1
TX_DATA
FIFO 64 bytes MII TX port
TX_EN
Figure 4-50 shows the R30 transmit interface. The lower 16 bits of the R30 (or FIFO transmit word)
contain transmit data nibbles. The upper 16 bits contain mask information. The operation to be performed
on the transmit interface is controlled by PRU writes to the R31 command interface. Table 4-35 describes
the TXMASK and TXDATA bit fields of the R30 transmit interface.
TX MASK[15:8]
MII TX DATA
TX MASK[7:0]
Using the TX mask, the PRU can send a mix of R30 and RX L1 FIFO data to the TX L1 FIFO. Note the
TX mask is only available when the PRU is fed one word or byte at a time by the RX L1 FIFO. It is not
applicable when the RX L2 buffer is enabled. To disable TX mask, set TXMASK to 0xFFFF.
As shown in Figure 4-51, the PRU drives the MII transmit interface through its R30 register. The contents
of R30 and RX data from the receive interface are taken and fed into a 64 byte transmit FIFO.
Before transmission, a mask is applied to the data portion of the R30 register. By using the mask, the
PRU firmware can control whether received data from the RX L1 FIFO is sent to transmit, R30 data is sent
to transmit, or a mix of the two is sent. The Boolean equation that is used by MII_RT to compose TX data
is:
TXDATA[7/15:0] = (R30[7/15:0] & MASK[7/15:0]) | (RXDATA[7/15:0] & ~MASK [7/15:0])
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PRU 0/1
R30
R31
TXDATA[7/15:0] = (R30[7/15:0] & MASK[7/15:0]) |
(RXDATA[7/15:0] & ~MASK [7/15:0])
TX L1
RX L1 TX_DATA
RX_DV FIFO 64 bytes MII TX port
MII RX port FIFO 32 bytes TX_EN
RX_CLK
1. Push
2. Pop
Mask
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On the transmit side, the order of the two data bytes and mask bytes in TX R30 are configurable through
the TX_BYTE_SWAP bit in the TXCFG0/1 registers, as shown in Table 4-38. Note the Nibble0 is the first
nibble received.
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There are two receive multiplexer instances to enable selection of RX MII path for each PRU. The select
lines of the RX multiplexers are driven from the PRU-ICSS programmable registers (RXCFG0/1).
TX_DATA[3:0]
TX_DATA[3:0]
TX MII
TX_PRU1 TX_EN
TX_EN Multiplexer TX_MII1/0
(Port 0/1)
TX_SOF
TX_DATA[3:0]
RX_MII0/1
TX_EN
The transmit multiplexers enable the PRU-ICSS to either operate in a bypass mode where the PRU is not
involved in processing MII traffic or use of one of the PRU cores for transmitting data into the MII interface.
There are two instances of the TX MII multiplexer and the select lines for each TX multiplexer are
provided by the PRU-ICSS. The select lines are common between register and FIFO interface. It is
expected that the select lines will not change during the course of a frame so that can avoid data
exchange error.
Bank 0 PRU
32 bytes of data XFR R0
…
Bank 1 R31
32 bytes of data
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4.4.7 MDIO
The MDIO module within the PRU-ICSS is identical to the MDIO module in Section 14.3.8.
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4.5 Registers
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296 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 297
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298 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 299
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300 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 301
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302 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 303
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304 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 305
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306 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 307
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308 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 309
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310 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 311
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312 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 313
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314 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 315
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316 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 317
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318 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 319
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320 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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322 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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324 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 325
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326 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 327
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328 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 329
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330 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 331
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332 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 333
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334 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 335
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336 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 337
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338 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 339
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340 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 341
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342 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 343
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344 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 345
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346 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 347
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348 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 349
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350 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 351
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352 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 353
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354 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 355
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356 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 357
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358 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 359
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360 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 361
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362 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 363
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364 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 365
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366 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 367
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368 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 369
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370 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 371
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372 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 373
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374 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 375
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376 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 377
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378 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 379
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380 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 381
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382 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 383
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384 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 385
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386 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 387
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388 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 389
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390 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 391
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392 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 393
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394 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 395
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396 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 397
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398 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 399
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400 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 401
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402 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 403
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404 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 405
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406 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 407
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408 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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410 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 411
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412 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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414 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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416 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 417
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418 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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420 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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422 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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424 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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428 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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430 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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432 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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434 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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436 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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438 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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440 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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442 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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3 RESERVED R 0h
2 SYNC1_EN R/W 0h SYNC1 generation enable
0: Disable
1: Enable
1 SYNC0_EN R/W 0h SYNC0 generation enable
0: Disable
1: Enable
444 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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446 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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448 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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450 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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452 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PRE_DIV
R/WtoClr-4E20h
7 6 5 4 3 2 1 0
PRE_DIV
R/WtoClr-4E20h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PDI_WD_TIME
R/WtoReset-3E8h
7 6 5 4 3 2 1 0
PDI_WD_TIME
R/WtoReset-3E8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PD_WD_TIME
R/WtoReset-3E8h
7 6 5 4 3 2 1 0
PD_WD_TIME
R/WtoReset-3E8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
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23 22 21 20 19 18 17 16
Reserved PDI_WD_STAT
R-0h R-1h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PD_WD_STAT
R-0h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
456 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
PD_EXP_CNT
R/WtoClr-0h
7 6 5 4 3 2 1 0
PDI_EXP_CNT
R/WtoClr-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Programmable Real-Time Unit Subsystem and Industrial Communication 457
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23 22 21 20 19 18 17 16
Reserved PDI_WD_EN
R-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved PD_WD_EN
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
458 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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460 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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462 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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all accesses read or modify DLH. DLH can also be accessed with address offset 24h.
• IIR and FCR share one address. Regardless of the value of the DLAB bit, reading from the address
gives the content of IIR, and writing modifies FCR.
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15 8 7 0
Reserved DATA
R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 8 7 0
Reserved DATA
R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
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15 4 3 2 1 0
Reserved Rsvd ELSI ETBEI ERBI
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
468 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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15 8 7 6 5 4 3 1 0
Reserved FIFOEN Reserved INTID IPEND
R-0 R-0 R-0 R-0 R-1
LEGEND: R = Read only; -n = value after reset
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CAUTION
For proper communication between the UART and the EDMA controller, the
DMAMODE1 bit must be set to 1. Always write a 1 to the DMAMODE1 bit, and
after a hardware reset, change the DMAMODE1 bit from 0 to 1.
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15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RXFIFTL Reserved DMAMODE1 (1) TXCLR RXCLR FIFOEN
W-0 R-0 W-0 W1C-0 W1C-0 W-0
LEGEND: R = Read only; W = Write only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
(1)
Always write 1 to the DMAMODE1 bit. After a hardware reset, change the DMAMODE1 bit from 0 to 1. DMAMODE = 1 is required for
proper communication between the UART and the DMA controller.
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15 8 7 6 5 4 3 2 1 0
Reserved DLAB BC SP EPS PEN STB WLS
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 4-236. Relationship Between ST, EPS, and PEN Bits in LCR
ST Bit EPS Bit PEN Bit Parity Option
x x 0 Parity disabled: No PARITY bit is transmitted or checked
0 0 1 Odd parity selected: Odd number of logic 1s
0 1 1 Even parity selected: Even number of logic 1s
1 0 1 Stick parity selected with PARITY bit transmitted and checked as set
1 1 1 Stick parity selected with PARITY bit transmitted and checked as cleared
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15 6 5 4 3 2 1 0
Reserved AFE (1) LOOP OUT2 OUT1 RTS (1) Rsvd
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
All UARTs do not support this feature, see your device-specific data manual for supported features. If this feature is not available, this bit
is reserved and should be cleared to 0.
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15 8 7 6 5 4 3 2 1 0
Reserved RXFIFOE TEMT THRE BI FE PE OE DR
R-0 R-0 R-1 R-1 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 8 7 6 5 4 3 2 1 0
Reserved CD RI DSR CTS DCD TERI DDSR DCTS
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 8 7 0
Reserved SCR
R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 8 7 0
Reserved DLL
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
15 8 7 0
Reserved DLH
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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15 8 7 0
Reserved REVID2
R-0 R-0
LEGEND: R = Read only; -n = value after reset
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15 14 13 12 1 0
Rsvd UTRST URRST Reserved FREE
R/W-0 R/W-0 R/W-0 R-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-246. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 Reserved 0 Reserved. This bit must always be written with a 0.
14 UTRST UART transmitter reset. Resets and enables the transmitter.
0 Transmitter is disabled and in reset state.
1 Transmitter is enabled.
13 URRST UART receiver reset. Resets and enables the receiver.
0 Receiver is disabled and in reset state.
1 Receiver is enabled.
12-1 Reserved 1 Reserved
0 FREE Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When
halted, the UART can handle register read/write requests, but does not generate any
transmission/reception, interrupts or events.
0 If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the
UART halts after completion of the one-word transmission.
1 Free-running mode is enabled; UART continues to run normally.
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15 1 0
Reserved OSM_SEL
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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518 Programmable Real-Time Unit Subsystem and Industrial Communication SPRUH73Q – October 2011 – Revised December 2019
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Chapter 5
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Introduction
This chapter describes the 2D/3D graphics accelerator (SGX) for the device.
NOTE: The SGX subsystem is a Texas Instruments instantiation of the POWERVR® SGX530 core
from Imagination Technologies Ltd.
This document contains materials that are ©2003-2007 Imagination Technologies Ltd.
POWERVR® and USSE™ are trademarks or registered trademarks of Imagination
Technologies Ltd.
The 2D/3D graphics accelerator (SGX) subsystem accelerates 2-dimensional (2D) and 3-dimensional (3D)
graphics applications. The SGX subsystem is based on the POWERVR® SGX core from Imagination
Technologies. SGX is a new generation of programmable POWERVR graphic cores. The POWERVR
SGX530 v1.2.5 architecture is scalable and can target market segments, from portable devices to HMI.
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5.1 Integration
GFX Subsystem
L3 Fast Master
Interconnect
L3 Fast Slave
Interconnect
THALIAIRQ
MPU Subsystem
PRCM
CORE_CLKOUTM4
(200 MHz) pd_gfx_gfx_l3_gclk
SYSCLK
MEMCLK
0 pd_gfx_gfx_fclk
/1, /2 CORECLK
1
PER_CLKOUTM2
(192 MHz)
SGX530 Integration
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POWERVR
SGX530 Vertex data Coarse-grain
master scheduler Tiling
coprocessor
Universal
Prog. data
Pixel data sequencer scalable
master shader
engine
(USSE)
Data master Pixel
General-purpose selector coprocessor
data master
SOCIF BIF
L3 interconnect L3 interconnect
sgx-003
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input control stream, which contains triangle index data and state data. The state data indicates the
PDS program, size of the vertices, and the amount of USSE output buffer resource available to the
VDM. The triangle data is parsed to determine unique indices that must be processed by the USSE.
These are grouped together according to the configuration provided by the driver and presented to the
DMS.
• The PDM is the initiator of rasterization processing within the system. Each pixel pipeline processes
pixels for a different half of a given tile, which allows for optimum efficiency within each pipe due to
locality of data. It determines the amount of resource required within the USSE for each task. It merges
this with the state address and issues a request to the DMS for execution on the USSE.
• The general-purpose data master responds to events within the system (such as end of a pass of
triangles from the ISP, end of a tile from the ISP, end of render, or parameter stream breakpoint
event). Each event causes either an interrupt to the host or synchronized execution of a program on
the PDS. The program may, or may not cause a subsequent task to be executed on the USSE.
The USSE is a user-programmable processing unit. Although general in nature, its instructions and
features are optimized for three types of task: processing vertices (vertex shading), processing pixels
(pixel shading), and video/imaging processing.
The multilevel cache is a 2-level cache consisting of two modules: the main cache and the
mux/arbiter/demux/decompression unit (MADD). The MADD is a wrapper around the main cache module
designed to manage and format requests to and from the cache, as well as providing Level 0 caching for
texture and USSE requests. The MADD can accept requests from the PDS, USSE, and texture address
generator modules. Arbitration, as well as any required texture decompression, are performed between
the three data streams.
The texturing coprocessor performs texture address generation and formatting of texture data. It receives
requests from either the iterators or USSE modules and translates these into requests in the multilevel
cache. Data returned from the cache are then formatted according to the texture format selected, and sent
to the USSE for pixel-shading operations.
To process pixels in a tiled manner, the screen is divided into tiles and arranged as groups of tiles by the
tiling coprocessor. An inherent advantage of tiling architecture is that a large amount of vertex data can be
rejected at this stage, thus reducing the memory storage requirements and the amount of pixel processing
to be performed.
The pixel coprocessor is the final stage of the pixel-processing pipeline and controls the format of the final
pixel data sent to the memory. It supplies the USSE with an address into the output buffer and then USSE
returns the relevant pixel data. The address order is determined by the frame buffer mode. The pixel
coprocessor contains a dithering and packing function.
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Chapter 6
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Interrupts
Priority Threshold
THRESHOLD Priority
Comparator
If (INT Priority
>Threshold)
PRIORITY
PENDING_IRQp
PENDING_FIQp
IRQ_PRIORITY
Processor
6.1.1.2 Masking
5. The ISR saves the remaining context, identifies the interrupt source by reading the
ACTIVEIRQ/ACTIVEFIQ field, and jumps to the relevant subroutine handler as follows:
CAUTION
The code in steps 5 and 7 is an assembly code compatible with ARM
architecture V6 and V7. This code is developed for the Texas Instruments Code
Composer Studio tool set. It is a draft version, only tested on an emulated
environment.
6. The subroutine handler executes code specific to the peripheral generating the interrupt by handling
the event and deasserting the interrupt condition at the peripheral side.
; IRQ0 subroutine
IRQ0handler:
; Save working registers
STMFD SP!, {R0-R1}
; Now read-modify-write the peripheral module status register
; to de-assert the M_IRQ_0 interrupt signal
; De-Assert the peripheral interrupt
MOV R0, #0x7 ; Mask for 3 flags
LDR R1, MODULE0_STATUS_REG_ADDR ; Get the address of the module Status Register
STR R0, [R1] ; Clear the 3 flags
; Restore working registers LDMFD SP!, {R0-R1}
; Jump to the end part of the ISR
B IRQ_ISR_end/FIQ_ISR_end
7. After the return of the subroutine, the ISR sets the NEWIRQAGR/NEWFIQAGR bit to enable the
processing of subsequent pending IRQs/FIQs and to restore ARM context in the following code.
Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done
before enabling IRQs/FIQs, a Data Synchronization Barrier is used. This operation ensure that the
IRQ/FIQ line is de-asserted before IRQ/FIQ enabling. After that, the INTC processes any other pending
interrupts or deasserts the IRQ/FIQ signal if there is no interrupt.
; INTC_CONTROL register address
INTC_CONTROL_ADDR .word 0x48200048;
NEWIRQAGR/NEWFIQAGR bit mask to set only the NEWIRQAGR/NEWFIQAGR bit
NEWIRQAGR_MASK/NEWFIQAGR_MASK .equ 0x01/0x02
IRQ_ISR_end/FIQ_ISR_end:
; Allow new IRQs/FIQs at INTC side
; The INTC_CONTROL register is a write only register so no need to write back others bits
MOV R0, #NEWIRQAGR_MASK/NEWFIQAGR_MASK ; Get the NEWIRQAGR/NEWFIQAGR bit position
LDR R1, INTC_CONTROL_ADDR
STR R0, [R1] ; Write the NEWIRQAGR/NEWFIQAGR bit to allow new IRQs/FIQ
; Data Synchronization Barrier
MOV R0, #0
MCR P15, #0, R0, C7, C10, #4
; restore critical context
MSR SPSR, R11 ; Restore the SPSR from R11
LDMFD SP!, {R0-R12, LR} ; Restore working registers and Link register
; Return after handling the interrupt
SUBS PC, LR, #4
8. After the ISR return, the ARM automatically restores its context as follows:
CPSR = SPSR
PC = LR
Figure 6-2 shows the IRQ/FIQ processing sequence from the originating device peripheral module to the
main program interruption.
The priority sorting mechanism is frozen during an interrupt processing sequence. If an interrupt condition
occurs during this time, the interrupt is not lost. It is sorted when the NEWIRQAGR/NEWFIQAGR bit is set
(priority sorting is reactivated).
MPU INTC
If the IRQ_n is not masked and configured as an IRQ/FIQ,
the MPU_INTC_IRQ/MPU_INTC_FIQ line is asserted.
MPU_INTC_IRQ/
Step 2
MPU_INTC_FIQ Asserted Main Program
Branch
Branch
CAUTION
The following code is an assembly code compatible with ARM architecture V6
and V7. This code is developed for the Texas Instruments Code Composer
Studio tool set. It is a draft version, only tested on an emulated environment.
CAUTION
The following code is an assembly code compatible with ARM architecture V6
and V7. This code is developed for the Texas Instruments Code Composer
Studio tool set. It is a draft version, only tested on an emulated environment.
IRQ_ISR_end:
; Step 1 : Read-modify-write the CPSR to disable IRQs/FIQs at ARM side
MRS R0, CPSR ; Read the CPSR
ORR R0, R0, #0x80/0x40 ; Set the I/F bit
MSR CPSR, R0 ; Write it back to disable IRQs
; Step 2 : Restore the INTC_THRESHOLD register from R12
LDR R0, INTC_THRESHOLD_ADDR
STR R12, [R0]
; Step 3 : Restore critical context
MSR SPSR, R11 ; Restore the SPSR from R11
LDMFD SP!, {R0-R12, LR} ; Restore working registers and Link register
; Return after handling the interrupt
SUBS PC, LR, #4
Figure 6-3 shows the nested IRQ/FIQ processing sequence from the originating device peripheral module
to the main program interruption.
MPU INTC
If the IRQ_n is not masked and configured as an IRQ/FIQ,
the MPU_INTC_IRQ/MPU_INTC_FIQ line is asserted.
MPU_INTC_IRQ/
Step 2
MPU_INTC_FIQ Asserted Main Program
Branch
Branch
NOTE:
1. The INTC_SIR_IRQ[31:7] SPURIOUSIRQFLAG bit field is a copy of the
INTC_IRQ_PRIORITY[31:7] SPURIOUSIRQFLAG bit field.
2. The INTC_SIR_FIQ[31:7] SPURIOUSFIQFLAG bit field is a copy of the
INTC_FIQ_PRIORITY[31:7] SPURIOUSFIQFLAG bit field.
Memory Subsystem
7.1 GPMC
7.1.1 Introduction
The general-purpose memory controller (GPMC) is an unified memory controller dedicated to interfacing
external memory devices:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (only available in non-multiplexed mode) burst NOR flash
devices
• NAND Flash
• Pseudo-SRAM devices
• Pre-fetch and write posting engine associated with system DMA to get full performance from NAND
device with minimum impact on NOR/SRAM concurrent access.
• On the fly ECC Hamming Code calculation to improve NAND usage reliability with minimum impact on
SW
Address
Chip-select
configuration Address
CS selection
Access engine
FIFO
Data Address
Prefetch and write-
posting engine
Control
ECC
7.1.2 Integration
An instantiation of GPMC provides this device with access to NAND Flash, NOR Flash, and other
asynchronous and synchronous interface peripherals. Figure 7-2 shows the integration of the GPMC
module in this device.
BE0n/CLE GPMC_BEN0_CLE
BE1n GPMC_BEN1
WPn GPMC_WPn
CONTROL_STATUS
SYSBOOT[11]
LCD_DATA11 WAIT[1:0] GPMC_WAIT[1:0]
SYSBOOT[10] ADMUX
LCD_DATA10 CS0MuxDevice[1:0] DIR2 GPMC_DIR
SYSBOOT[8] BW BootDeviceSize0
LCD_DATA8 WAITEN
SYSBOOT[9] BootWaitEn DATA[31:16]
LCD_DATA9
WaitSelectPin[1:0] CS[7]
BootDeviceSize1 WAIT[3:2]
Functional Description
Table 7-5 shows the use of address and data GPMC controller pins based on the type of external device.
(1)
The values in this column represent the signals on the memory. Be aware that some 16-bit memories may label the address
lines differently. Some label the LSB as A0, while others use A1 for the LSB. These columns assume the LSB is A0.
With all device types, the GPMC does not drive unnecessary address lines. They stay at their reset value
of 00.
Address mapping supports address/data-multiplexed 16-bit wide devices:
• The NOR flash memory controller still supports non-multiplexed address and data memory devices.
• Multiplexing mode can be selected through the GPMC_CONFIG1_i[9-8] MUXADDDATA bit field.
• Asynchronous page mode is not supported for multiplexed address and data devices.
Device
gpmc_a[11:1] 11
A[27:17] A[26:16]
gpmc_ad[15:0] 16
A[16:1]/D[15:0] A/D[15:0]
CSn[6:0] gpmc_csn[6:0] CEn
gpmc_advn_ale
ADVn_ALE ADVn
gpmc_oen
OEn_REn OEn
WEn gpmc_wen
WEn
gpmc_be0n_cle
BE0n_CLE BE0n/CLE
BE1n gpmc_be1n
BE1n
WPn gpmc_wpn
WPn
gpmc_wait[1:0]
WAIT[1:0] WAIT
gpmc_clk
CLK CLK
Device
gpmc_a[27:1] 27
A[27:1] A[26:0]
gpmc_ad[15:0] 16
D[15:0] D[15:0]
CSn[6:0] gpmc_csn[6:0] CEn
gpmc_advn_ale
ADVn_ALE ADVn
OEn_REn gpmc_oen
OEn
WEn gpmc_wen
WEn
gpmc_be0n_cle
BE0n_CLE BE0n/CLE
BE1n gpmc_be1n
BE1n
WPn gpmc_wpn
WPn
gpmc_wait[1:0]
WAIT[1:0] WAIT
gpmc_clk
CLK CLK
Device
gpmc_ad[7:0] 8
D[7:0] D[7:0]
CSn[6:0] gpmc_csn[6:0] CSn
ADVn_ALE gpmc_advn_ale
ADVn/ALE
OEn_REn gpmc_oen
OEn/REn
WEn gpmc_wen
WEn
BE0n_CLE gpmc_be0n_cle
CLE
BE1n gpmc_be1n
WPn gpmc_wpn
WPn
gpmc_wait[1:0]
WAIT[1:0] WAIT
gpmc_clk
CLK
The GPMC_CLK is generated by the GPMC from the internal GPMC_FCLK clock. The source of the
GPMC_FCLK is described in Table 7-3. The GPMC_CLK is configured via the GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER field (for i = 0 to 3) as shown in Table 7-7.
NOTE: In this section and next sections, the i in GPMC_CONFIGx_i stands for the GPMC chip-
select i where i = 0 to 6.
256 MBytes
128 MBytes
64 MBytes
32 MBytes
16 MBytes
1 GBytes
Base address A29 A28 A27 A26 A25 A24 (16-MBytes minimum granularity)
256 MBytes 0 0 0 0
128 MBytes 1 0 0 0
64 MBytes 1 1 0 0
32 MBytes 1 1 1 0
16 MBytes 1 1 1 1
A mask value of 0010 or 1001 must be avoided because it will create holes in the chip-select address space.
Chip-select configuration (base and mask address or any protocol and timing settings) must be performed
while the associated chip-select is disabled through the GPMC_CONFIG7_i[6] CSVALID bit. In addition, a
chip-select configuration can only be disabled if there is no ongoing access to that chip-select. This
requires activity monitoring of the prefetch or write-posting engine if the engine is active on the chip-select.
Also, the write buffer state must be monitored to wait for any posted write completion to the chip-select.
Any access attempted to a nonvalid GPMC address region (CSVALID disabled or address decoding
outside a valid chip-select region) is not propagated to the external interface and a GPMC access error is
posted. In case of chip-selects overlapping, an error is generated and no access will occur on either chip-
select. Chip-select 0 is the only chip-select region enabled after either a power-up or a GPMC reset.
Although the GPMC interface can drive up to seven chip-selects, the frequency specified for this interface
is for a specific load. If this load is exceeded, the maximum frequency cannot be reached. One solution is
to implement a board with buffers, to allow the slowest device to maintain the total load on the lines.
Figure 7-7. Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1)
RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
WAIT
WAITPINMONITORING = 0b00
WAITPINMONITORING = 0b01
When a delay larger than two GPMC clock cycles must be observed between wait-pin deassertion time
and the effective data write into the external device (including the required GPMC data setup time and the
device data setup time), an extra delay can be added between wait-pin deassertion time detection and
effective data write time into the external device and the effective unfreezing of the CYCLETIME counter.
This extra delay can be programmed in the GPMC_CONFIG1_i[19-18] WAITMONITORINGTIME fields.
• The WAITMONITORINGTIME parameter does not delay the wait-pin assertion or deassertion
detection, nor does it modify the two GPMC clock cycles pipelined detection delay.
• This extra delay is expressed as a number of GPMC_CLK clock cycles, even though the access is
defined as asynchronous, and even though no clock is provided to the external device. Still,
GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER is used as a divider for the GPMC clock and so it must
be programmed to define the correct WAITMONITORINGTIME delay.
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
RDACCESSTIME PAGEBURSTACCESSTIME
WAITMONITORINGTIME = 0b01
WAITMONITORINGTIME = 0b00
CLKACTIVATIONTIME
GPMC_FCLK
GPMC_CLK
A[16:1]/D[15:0] D0 D1 D2 D3
nBE1/nBE0
CSRDOFFTIME0 CSRDOFFTIME1
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME0 OEOFFTIME1
OEONTIME
nOE
WAIT
Wait deasserted one Wait deasserted
GPMC.CLK cycle same cycle as
before valid data valid data
Figure 7-9. Read to Read for an Address-Data Multiplexed Device, On Different CS,
Without Bus Turnaround (CS0n Attached to Fast Device)
New read/write access
RD/WRCYCLETIME
RDCYCLETIME
D[15:0] DATA 0
OEOFFTIME
nOE
CSOFFTIME
nCS0
nCS1
DIR IN
Figure 7-10. Read to Read / Write for an Address-Data Multiplexed Device, On Different CS,
With Bus Turnaround
New read/write
access
OEOFFTIME
nOE
RDCYCLETIME RD/WRCYCLETIME
CSOFFTIME
nCS0
BUSTURNAROUND
nCS1
DIR IN OUT
Figure 7-11. Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS,
With Bus Turnaround
New read/write
access
A[16:1]/D[15:0] DATA 0 ADD 1
OEOFFTIME
nOE
BUSTURNAROUND
RDCYCLETIME RD/WRCYCLETIME
CSOFFTIME
nCS0
DIR IN OUT
7.1.2.3.8.3.10 Reset
No reset signal is sent to the external memory device by the GPMC. For more information about external-
device reset, see Chapter 8, Power, Reset, and Clock Management (PRCM).
The PRCM module provides an input pin, global_rst_n, to the GPMC:
• The global_rst_n pin is activated during device warm reset and cold reset.
• The global_rst_n pin initializes the internal state-machine and the internal configuration registers.
• ERRORNOTSUPPADD occurs when an incoming system request address decoding does not match
any valid chip-select region, or if two chip-select regions are defined as overlapped, or if a register file
access is tried outside the valid address range of 1KB.
• ERRORNOTSUPPMCMD occurs when an unsupported command request is decoded at the L3 Slow
interconnect interface
• ERRORTIMEOUT: A time-out mechanism prevents the system from hanging. The start value of the
9-bit time-out counter is defined in the GPMC_TIMEOUT_CONTROL register and enabled with the
GPMC_TIMEOUT_CONTROL[0] TIMEOUTENABLE bit. When enabled, the counter starts at start-cycle
time until it reaches 0 and data is not responded to from memory, and then a time-out error occurs. When
data are sent from memory, this counter is reset to its start value. With multiple accesses (asynchronous
page mode or synchronous burst mode), the counter is reset to its start value for each data access within
the burst.
The GPMC does not generate interrupts on these errors. True abort to the MPU or interrupt generation is
handled at the interconnect level.
7.1.2.3.9.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
The GPMC_CONFIG5_i[4-0] RDCYCLETIME and GPMC_CONFIG5_i[12-8] WRCYCLETIME fields define
the address bus and byte enables valid times for read and write accesses. To ensure a correct duty cycle
of GPMC_CLK between accesses, RDCYCLETIME and WRCYCLETIME are expressed in GPMC_FCLK
cycles and must be multiples of the GPMC_CLK cycle. RDCYCLETIME and WRCYCLETIME bit fields can
be set with a granularity of 1 or 2 throught GPMC_CONFIG1_i[4] TIMEPARAGRANULARITY.
When either RDCYCLETIME or WRCYCLETIME completes, if they are not already deasserted, all control
signals (CSn, ADV_ALEn, OE_REn, WEn, and BE0_CLEn) are deasserted to their reset values,
regardless of their deassertion time parameters.
An exception to this forced deassertion occurs when a pipelined request to the same chip-select or to a
different chip-select is pending. In such a case, it is not necessary to deassert a control signal with
deassertion time parameters equal to the cycle-time parameter. This exception to forced deassertion
prevents any unnecessary glitches. This requirement also applies to BE signals, thus avoiding an
unnecessary BE glitch transition when pipelining requests.
If no inactive cycles are required between successive accesses to the same or to a different chip-select
(GPMC_CONFIG6_i[7] CYCLE2CYCLESAMECSEN = 0 or GPMC_CONFIG6_i[6]
CYCLE2CYCLEDIFFCSEN = 0, where i = 0 to 3), and if assertion-time parameters associated with the
pipelined access are equal to 0, asserted control signals (CSn, ADV_ALEn, BE0_CLEn, WEn, and
OE_REn) are kept asserted. This applies to any read/write to read/write access combination.
If inactive cycles are inserted between successive accesses, that is, CYCLE2CYCLESAMECSEN = 1 or
CYCLE2CYCLEDIFFCSEN = 1, the control signals are forced to their respective default reset values for
the number of GPMC_FCLK cycles defined in CYCLE2CYCLEDELAY.
7.1.2.3.9.3 ADVn/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME /
ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME
)
The GPMC_CONFIG3_i[3-0] ADVONTIME field defines the ADVn_ALE signal-assertion time relative to
start access time. It is common to read and write accesses.
The GPMC_CONFIG3_i[12-8] ADVRDOFFTIME (read access) and GPMC_CONFIG3_i[20-16]
ADVWROFFTIME (write access) bit fields define the ADVn_ALE signal-deassertion time relative to start
access time.
ADVONTIME can be used to control an address and byte enable valid setup time control before
ADVn_ALE assertion. ADVRDOFFTIME and ADVWROFFTIME can be used to control an address and
byte enable valid hold time control after ADVn_ALE de-assertion. ADVRDOFFTIME and
ADVWROFFTIME are applicable to both synchronous and asynchronous modes.
ADVn_ALE signal transitions as controlled through ADVONTIME, ADVRDOFFTIME, and
ADVWROFFTIME can be delayed by half a GPMC_FCLK period by enabling the GPMC_CONFIG3_i[7]
ADVEXTRADELAY bit. This half of a GPMC_FCLK period provides more granularity on ADVn_ALE
assertion and deassertion time to assure proper setup and hold time relative to GPMC_CLK. The
ADVEXTRADELAY configuration parameter is especially useful in configurations where GPMC_CLK and
GPMC_FCLK have the same frequency, but can be used for all GPMC configurations. If enabled,
ADVEXTRADELAY applies to all parameters controlling ADVn_ALE transitions.
ADVEXTRADELAY must be used carefully to avoid control-signal overlap between successive accesses
to different chip-selects. This implies the need to program the RDCYCLETIME and WRCYCLETIME bit
fields to be greater than ADVn_ALE signal-deassertion time, including the extra half-GPMC_FCLK-period
delay.
The GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME, GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME, and GPMC_CONFIG3_i[30-28] ADVAADMUXWROFFTIME parameters have
the same functions as ADVONTIME, ADVRDOFFTIME, and ADVWROFFTIME, but apply to the first
address phase in the AAD-multiplexed protocol. It is the user responsibility to make sure
ADVAADMUXxxOFFTIME is programmed to a value lower than or equal to ADVxxOFFTIME. Functionality
in AAD-mux mode is undefined if the settings do not comply with this requirement.
ADVAADMUXxxOFFTIME can be programmed to the same value as ADVONTIME if no high ADVn pulse
is needed between the two AAD-mux address phases, which is the typical case in synchronous mode. In
this configuration, ADVn is kept low until it reaches the correct ADVxxOFFTIME.
See Section 7.1.2.3.12 for more details on ADVONTIME, ADVRDOFFTIME, ADVWROFFTIME, and
ADVAADMUXRDOFFTIME, ADVAADMUXWROFFTIME usage for CLE and ALE (Command / Address
Latch Enable) usage for a NAND Flash interface.
7.1.2.3.9.4 OEn/REn: Output Enable / Read Enable Signal Control Assertion / Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
The GPMC_CONFIG4_i[3-0] OEONTIME field defines the OEn_REn signal assertion time relative to start
access time. It is applicable only to read accesses.
The GPMC_CONFIG4_i[12-8] OEOFFTIME field defines the OEn_REn signal deassertion time relative to
start access time. It is applicable only to read accesses. OEn_REn is not asserted during a write cycle.
OEONTIME, OEOFFTIME, OEAADMUXONTIME and OEAADMUXOFFTIME parameters are applicable to
synchronous and asynchronous modes. OEONTIME can be used to control an address and byte enable
valid setup time control before OEn_REn assertion. OEOFFTIME can be used to control an address and
byte enable valid hold time control after OEn_REn assertion.
OEAADMUXONTIME and OEAADMUXOFFTIME parameters have the same functions as OEONTIME
and OEOFFTIME, but apply to the first OE assertion in the AAD-multiplexed protocol for a read phase, or
to the only OE assertion for a write phase. It is the user responsibility to make sure OEAADMUXOFFTIME
is programmed to a value lower than OEONTIME. Functionality in AAD-mux mode is undefined if the
settings do not comply with this requirement. OEAADMUXOFFTIME shall never be equal to OEONTIME
because the AAD-mux protocol requires a second address phase with the OEn signal de-asserted before
OEn can be asserted again to define a read command.
The OEn_REn signal transitions as controlled through OEONTIME, OEOFFTIME, OEAADMUXONTIME
and OEAADMUXOFFTIME can be delayed by half a GPMC_FCLK period by enabling the
GPMC_CONFIG4_i[7] OEEXTRADELAY bit. This half of a GPMC_FCLK period provides more granularity
on OEn_REn assertion and deassertion time to assure proper setup and hold time relative to GPMC_CLK.
If enabled, OEEXTRADELAY applies to all parameters controlling OEn_REn transitions.
OEEXTRADELAY must be used carefully, to avoid control-signal overlap between successive accesses to
different chip-selects. This implies the need to program RDCYCLETIME and WRCYCLETIME to be
greater than OEn_REn signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
When the GPMC generates a read access to an address-/data-multiplexed device, it drives the address
bus until OEn assertion time.
7.1.2.3.9.5 WEn: Write Enable Signal Control Assertion / Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY)
The GPMC_CONFIG4_i[19-16] WEONTIME field (where i = 0 to 3) defines the WEn signal-assertion time
relative to start access time. The GPMC_CONFIG4_i[28-24] WEOFFTIME field defines the WEn signal-
deassertion time relative to start access time. These bit fields only apply to write accesses. WEn is not
asserted during a read cycle.
WEONTIME can be used to control an address and byte enable valid setup time control before WEn
assertion. WEOFFTIME can be used to control an address and byte enable valid hold time control after
WEn assertion.
WEn signal transitions as controlled through WEONTIME, and WEOFFTIME can be delayed by half a
GPMC_FCLK period by enabling the GPMC_CONFIG4_i[23] WEEXTRADELAY bit. This half of a
GPMC_FCLK period provides more granularity on WEn assertion and deassertion time to guaranty proper
setup and hold time relative to GPMC_CLK. If enabled, WEEXTRADELAY applies to all parameters
controlling WEn transitions.
The WEEXTRADELAY bit must be used carefully to avoid control-signal overlap between successive
accesses to different chip-selects. This implies the need to program the WRCYCLETIME bit field to be
greater than the WEn signal-deassertion time, including the extra half-GPMC_FCLK-period delay.
7.1.2.3.9.6 GPMC_CLK
GPMC_CLK is the external clock provided to the attached synchronous memory or device.
• The GPMC_CLK clock frequency is the GPMC_FCLK functional clock frequency divided by 1, 2, 3, or
4, depending on the GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER bit field, with a guaranteed 50-
percent duty cycle.
• The GPMC_CLK clock is only activated when the access in progress is defined as synchronous (read
or write access).
• The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field defines the number of GPMC_FCLK
cycles from start access time to GPMC_CLK activation.
• The GPMC_CLK clock is stopped when cycle time completes and is asserted low between accesses.
• The GPMC_CLK clock is kept low when access is defined as asynchronous.
• When the GPMC is configured for synchronous mode, the GPMC_CLK signal (which is an output)
must also be set as an input in the Pin Mux configuration for the pin. GPMC_CLK is looped back
through the output and input buffers of the corresponding GPMC_CLK pad at the device boundary.
The looped-back clock is used to synchronize the sampling of the memory signals.
When cycle time completes, the GPMC_CLK may be high because of the GPMCFCLKDIVIDER bit field.
To ensure correct stoppage of the GPMC_CLK clock within the 50-percent required duty cycle, it is the
user's responsibility to extend the RDCYCLETIME or WRCYCLETIME value.
To ensure a correct external clock cycle, the following rules must be applied:
• (RDCYCLETIME - CLKACTIVATIONTIME) must be a multiple of (GPMCFCLKDIVIDER + 1).
• The PAGEBURSTACCESSTIME value must be a multiple of (GPMCFCLKDIVIDER + 1).
GPMC_CLK which is sent to the memory device for synchronization with the GPMC controller, is internally
retimed to correctly latch the returned data. GPMC_CONFIG5_i[4-0] RDCYCLETIME must be greater than
RDACCESSTIME in order to let the GPMC latch the last return data using the internally retimed
GPMC_CLK.
The external WAIT signal can be used in conjunction with RDACCESSTIME to control the effective GPMC
data-capture GPMC_FCLK edge on read access in both asynchronous mode and synchronous mode. For
details about wait monitoring, see Section 7.1.2.3.8.1.
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
WAIT
Figure 7-13. Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device
(32-Bit Read Split Into 2 × 16-Bit Read)
CYCLE2CYCLEDELAY
RDCYCLETIME RDCYCLETIME
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME CSRDOFFTIME
CSONTIME CSONTIME
nCS
ADVRDOFFTIME ADVRDOFFTIME
ADVONTIME ADVONTIME
nADV
OEOFFTIME OEOFFTIME
OEONTIME OEONTIME
nOE
WAIT
GPMC_FCLK
GPMC_CLK
A[27:17] Valid Address
WRDATAONADMUXBUS
A[16:1]/D[15:0] Valid Address Data
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
After a write operation, if no other access (read or write) is pending, the data bus keeps its previous value.
See Section 7.1.2.3.9.10.
RDCYCLETIME
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
ADVAADMUXRDOFFTIME
ADVAADMUXONTIME
nADV
OEOFFTIME
OEONTIME
OEAADMUXOFFTIME
OEAADMUXONTIME
nOE
WAIT
WRCYCLETIME
GPMC_FCLK
GPMC_CLK
WRDATAONADMUXBUS
A[16:1]/D[15:0] MSB Address LSB Address Data
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
ADVAADMUXWROFFTIME
ADVAADMUXONTIME
nADV
OEAADMUXOFFTIME
OEAADMUXONTIME
nOE
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
RDACCESSTIME
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
WAIT
GPMC_FCLK
RDACCESSTIME
CLKACTIVATIONTIME
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
WAIT
• Direction signal DIR: DIR goes from OUT to IN at the same time as OEn assertion.
When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven onto
the address/data bus in two separate phases. The first phase is used for the MSB address and is qualified
with OEn driven low. The second phase for LSB address is qualified with OEn driven high. The address
phase ends at WEn assertion time.
The CSn and DIR signals are controlled in the same way as for synchronous single read operation on an
address/data-multiplexed device.
• Address valid signal ADVn is asserted and deasserted twice during a read transaction
– ADVn first assertion time is controlled by the GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME field.
– ADVn first deassertion time is controlled by the GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME field.
– ADVn second assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[12-8] ADVRDOFFTIME
field.
• Output Enable signal OEn is asserted and deasserted twice during a read transaction (OEn second
assertion indicates a read cycle)
– OEn first assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
– OEn first deassertion time is controlled by the GPMC_CONFIG3_i[15-13] OEAADMUXOFFTIME
field.
– OEn second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field.
– OEn second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See Section 7.1.2.3.9.10.
7.1.2.3.10.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
Figure 7-19 and Figure 7-20 show a synchronous multiple read operation with GPMCFCLKDivider equal
to 0 and 1, respectively.
PAGEBURSTACCESSTIME
RDACCESSTIME PAGEBURSTACCESSTIME
CLKACTIVATIONTIME PAGEBURSTACCESSTIME
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME0 CSRDOFFTIME1
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
DIR OUT IN OUT
WAIT
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME0 CSRDOFFTIME1
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME0 OEOFFTIME1
OEONTIME
nOE
DIR OUT IN OUT
WAIT
GPMC_FCLK
GPMC_CLK
WRDATAONADMUXBUS
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
When the GPMC generates a write access to an address/data-multiplexed device, it drives the data bus
(with address bits A[16:1]) until [19:16] WRDATAONADMUXBUS time. First data of the burst is driven on
the address/data bus at WRDATAONADMUXBUS time.
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
Figure 7-23 shows the same synchronous burst write access when the chip-select is configured in
address/address/data-multiplexed (AAD-multiplexed) mode.
GPMC_FCLK
CLKACTIVATIONTIME
GPMC_CLK
nCS
ADVWROFFTIME
ADVONTIME
ADVAADMUXOFFTIME
ADVAADMUXONTIME
nADV
OEAADMUXOFFTIME
OEAADMUXONTIME
nOE
WEOFFTIME
WEONTIME
nWE
DIR OUT
WAIT
The first data of the burst is driven on the A/D bus at GPMC_CONFIG6_i[19:16]
WRDATAONADMUXBUS.
When WRACCESSTIME completes, control-signal timings are frozen during the multiple data
transactions, corresponding to the GPMC_CONFIG5_i[27-24] PAGEBURSTACCESSTIME multiplied by
the number of remaining data transactions.
When the GPMC generates a read access to an address/data-multiplexed device, it drives the address
bus until OEn assertion time. For details, see Section 7.1.2.3.8.2.3.
• Chip-select signal CSn
– CSn assertion time is controlled by the GPMC_CONFIG2_i[3-0] CSONTIME field and ensures
address setup time to CSn assertion.
– CSn deassertion time controlled by the GPMC_CONFIG2_i[20-16] CSWROFFTIME field and
ensures address hold time to CSn deassertion.
• Address valid signal ADVn
– ADVn assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADVn deassertion time is controlled by the GPMC_CONFIG3_i[20-16] ADVWROFFTIME field.
RDACCESSTIME
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSRDOFFTIME
CSONTIME
nCS
ADVRDOFFTIME
ADVONTIME
nADV
OEOFFTIME
OEONTIME
nOE
WAIT
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus
D[15:0].
Read data is latched at GPMC_CONFIG1_5[20-16] RDACCESSTIME completion time. The end of the
access is defined by the GPMC_CONFIG1_5[4-0] RDCYCLETIME parameter.
CSn, ADVn, OEn and DIR signals are controlled in the same way as address/data multiplexed accesses,
see Section 7.1.2.3.10.1.1.2.
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
CSWROFFTIME
CSONTIME
nCS
ADVWROFFTIME
ADVONTIME
nADV
WEOFFTIME
WEONTIME
nWE
WAIT
The 27-bit address is driven onto the address bus A[27:1] and the 16-bit data is driven onto the data bus
D[15:0].
CSn, ADVn, WEn and DIR signals are controlled in the same way as address/data multiplexed accesses,
see Section 7.1.2.3.10.1.1.3.
GPMC_CLK
RDACCESSTIME
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
A[27:1] A0 A1 A2 A3 A4
RDCYCLETIME0 RDCYCLETIME1
D[15:0] D0 D1 D2 D3 D3
nBE1/nBE0
CSRDOFFTIME0 CSRDOFFTIME1
CSONTIME
nCS
ADVRDOFFTIME0
ADVONTIME
nADV
OEOFFTIME0 OEOFFTIME1
OEONTIME
nOE
WAIT
The device system issues only requests with addresses or starting addresses for nonwrapping burst
requests; that is, the request size boundary is aligned. In case of an eight-word-wrapping burst, the
wrapping address always occurs on the eight-words boundary. As a consequence, all words requested
must be available from the memory data buffer when the buffer size is equal to or greater than the
ATTACHEDDEVICEPAGELENGTH value. This usually means that data can be read from or written to the
buffer at a constant rate (number of cycles between data) without wait states between data accesses. If
the memory does not behave this way (nonzero wait state burstable memory), wait-pin monitoring must be
enabled to dynamically control data-access completion within the burst.
When the system burst request length is less than the ATTACHEDDEVICEPAGELENGTH value, the
GPMC proceeds with the required accesses.
Any chip-select region can be qualified as a NAND region to constrain the ADVn_ALE signal as Address
Latch Enable (ALE active high, default state value at low) during address program access, and the
BE0n_CLE signal as Command Latch Enable (CLE active high, default state value at low) during
command program access. GPMC address lines are not used (the previous value is not changed) during
NAND access.
7.1.2.3.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
The GPMC_CONFIG7_i register associated with a NAND device region interfaced in byte or word stream
mode can be initialized with a minimum size of 16 Mbytes, because any address location in the chip-select
memory region can be used to access a NAND data array. The NAND Flash protocol specifies an address
sequence where address bits are passed through the data bus in a series of write accesses with the ALE
pin asserted. After this address phase, all operations are streamed and the system requests address is
irrelevant.
To allow correct command, address, and data-access controls, the GPMC_CONFIG1_i register
associated with a NAND device region must be initialized in asynchronous read and write modes with the
parameters shown in Chip-Select Configuration for NAND Interfacing. Failure to comply with these
settings corrupts the NAND interface protocol.
The GPMC_CONFIG1_i to GPMC_CONFIG4_i register associated with a NAND device region must be
initialized with the correct control-signal timing value according to the NAND device timing parameters.
Command and address values are not latched during the access and cannot be read back at the register
location.
• Only write accesses must be issued to these locations, but the GPMC does not discard any read
access. Accessing a NAND device with OEn and CLE or ALE asserted (read access) can produce
undefined results.
• Write accesses to the GPMC_NAND_COMMAND_i register location and to the
GPMC_NAND_ADDRESS_i register location must be posted for faster operations. The
GPMC_CONFIG[0] NANDFORCEPOSTEDWRITE bit enables write accesses to these locations as
posted, even if they are defined as nonposted.
A write buffer is used to store write transaction information before the external device is accessed:
• Up to eight consecutive posted write accesses can be accepted and stored in the write buffer.
• For nonposted write, the pipeline is one deep.
• A GPMC_STATUS[0] EMPTYWRITEBUFFERSTATUS bit stores the empty status of the write buffer.
The GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i registers are 32-bit word locations,
which means any 32-bit word or 16-bit word access is split into 4- or 2-byte accesses if an 8-bit wide
NAND device is attached. For multiple-command phase or multiple-address phase, the software driver can
use 32-bit word or 16-bit word access to these registers, but it must account for the splitting and little-
endian ordering scheme. When only one byte command or address phase is required, only byte write
access to a GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i can be used, and any of the
four byte locations of the registers are valid.
The same applies to GPMC_NAND_COMMAND_i and GPMC_NAND_ADDRESS_i 32-bit word write
access to a 16-bit wide NAND device (split into two 16-bit word accesses). In the case of a 16-bit word
write access, the MSByte of the 16-bit word value must be set according to the NAND device requirement
(usually 0). Either 16-bit word location or any one of the four byte locations of the registers is valid
CSWROFFTIME
CSONTIME = 0
nCS
nBE0/CLE
WEOFFTIME
WEONTIME = 0
nWE
nADV/ALE
D[15:0] Command
CSWROFFTIME = WRCYCLETIME
CSONTIME = 0
nCS
nBE0/CLE
WEOFFTIME
WEONTIME = 0
nWE
ADVWROFFTIME = WRCYCLETIME
ADVONTIME = 0
nADV/ALE
D[15:0] Address
7.1.2.3.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
NAND device data read and write accesses are achieved through a read or write request to the chip-
select-associated memory region at any address location in the region or through a read or write request
to the GPMC_NAND_DATA_i location mapped in the chip-select-associated control register region.
GPMC_NAND_DATA_i is not a true register, but an address location to enable REn or WEn signal
control. The associated chip-select signal timing control must be programmed according to the NAND
device timing specification.
Reading data from the GPMC_NAND_DATA_i location or from any location in the associated chip-select
memory region activates an asynchronous read access.
• CSn is controlled by the CSONTIME and CSRDOFFTIME timing parameters.
• REn is controlled by the OEONTIME and OEOFFTIME timing parameters.
• To take advantage of REn high-to-data invalid minimum timing value, the RDACCESSTIME can be set
so that data are effectively captured after REn deassertion. This allows optimization of NAND read
access cycle time completion. For optimal timing parameter settings, see the NAND device and the
device IC timing parameters.
ALE, CLE, and WEn are maintained inactive.
Figure 7-29 shows the NAND data read cycle.
CSRDOFFTIME = RDCYCLETIME
CSONTIME = 0
nCS
nBE0/CLE
RDACCESSTIME
OEOFFTIME
OEONTIME = 0
nOE/nRE
nADV/ALE
D[15:0] Data
WAIT
Writing data to the GPMC_NAND_DATA_i location or to any location in the associated chip-select
memory region activates an asynchronous write access.
• CSn is controlled by the CSONTIME and CSWROFFTIME timing parameters.
• WEn is controlled by the WEONTIME and WEOFFTIME timing parameters.
• ALE, CLE, and REn (OEn) are maintained inactive.
Figure 7-30 shows the NAND data write cycle.
CSONTIME = 0
CSWROFFTIME = WRCYCLETIME
nCS
nBE0/CLE
WEOFFTIME
WEONTIME = 0
nWE
D [15:0] Data
Host byte read and write access requests to a 16-bit wide NAND device are completed as 16-bit accesses
on the device itself, because there is no byte-addressing capability on 16-bit wide NAND devices. This
means that the NAND device address pointer is incremented on a 16-bit word basis and not on a byte
basis. For a read access, only the requested byte is given back to the host, but the remaining byte is not
stored or saved by the GPMC, and the next byte or 16-bit word read access gets the next 16-bit word
NAND location. For a write access, the invalid byte part of the 16-bit word is driven to FF, and the next
byte or 16-bit word write access programs the next 16-bit word NAND location.
Generally, byte access to a 16-bit wide NAND device should be avoided, especially when ECC calculation
is enabled. 8-bit or 16-bit ECC-based computations are corrupted by a byte read to a 16-bit wide NAND
device, because the nonrequested byte is considered invalid on a read access (not captured on the
external data bus; FF is fed to the ECC engine) and is set to FF on a write access.
Host requests (read/write) issued in the chip-select memory region are translated in successive single or
split accesses (read/write) to the attached device. Therefore, incrementing 32-bit burst requests are
translated in multiple 32-bit sequential accesses following the access adaptation of the 32-bit to 8- or 16-
bit device.
The wait transition pin detector must be cleared before any transition detection. This is done by writing 1
to the WAITxEDGEDETECTIONSTATUS bit (x = 0 or 1) of the GPMC_IRQSTATUS register according to
the gpmc_wait pin used for the NAND device-ready signal monitoring. To detect a wait-to-no-wait
transition, the transition detector requires a wait active time detection of a minimum of two GPMC_FCLK
cycles. Software must incorporate precautions to clear the wait transition pin detector before wait (busy)
time completes.
A wait-to-no-wait transition detection can issue a GPMC interrupt if the WAITxEDGEDETECTIONENABLE
bit in the GPMC_IRQENABLE register is set and if the WAITxEDGEDETECTIONSTATUS bit field in the
GPMC_IRQSTATUS register is set.
The WAITMONITORINGTIME field does not affect wait-to-no-wait transition time detection.
It is also possible to poll the WAITxEDGEDETECTIONSTATUS bit field in the GPMC_IRQSTATUS
register according to the gpmc_wait pin used for the NAND device ready signal monitoring.
The starting NAND page location must be programmed first, followed by an ECC accumulation context
reset with an ECC enabling, if required. The NAND device accesses discussed in the following sections
must be limited to data read or write until the specified number of ECC calculations is completed.
Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 253 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 253 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
P2o P2o
For line parities, the bits of each new data are XORed together, and line parity bits are computed as:
P8e = row0 XOR row2 XOR row4 XOR ... XOR row254
P8o = row1 XOR row3 XOR row5 XOR ... XOR row255
P16e = row0 XOR row1 XOR row4 XOR row5 XOR ... XOR row252 XOR row 253
P16o = row2 XOR row3 XOR row6 XOR row7 XOR ... XOR row254 XOR row 255
Unused parity bits in the result registers are cleared to 0.
Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e
Row 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 253 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 253 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e
Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Figure 7-33 shows ECC computation for a 256-byte data stream (read or write). The result includes six
column parity bits (P1o-P2o-P4o for odd parities, and P1e-P2e-P4e for even parities) and sixteen row
parity bits (P8o-P16o-P32o--P1024o for odd parities, and P8e-P16e-P32e--P1024e for even parities).
Figure 7-33. ECC Computation for a 256-Byte Data Stream (Read or Write)
256 byte
Bytes input
input
Row 00
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 11
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
P1024e
Row 22
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16o
P16o
Row 33
Row bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
Row 252
Row 252 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 253
Row 253 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
P1024o
P1024o
Row 254
Row 254 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16o
P16o
Row 255
Row 255 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P8o
P1o
P1o P1e P1o
P1o P1e P1o
P1o P1e P1o
P1o P1e
P2o
P2o P2e P2o
P2o P2e
P4o
P4o P4e
Figure 7-34 shows ECC computation for a 512-byte data stream (read or write). The result includes six
column parity bits (P1o-P2o-P4o for odd parities, and P1e-P2e-P4e for even parities) and eighteen row
parity bits (P8o-P16o-P32o--P1024o- - P2048o for odd parities, and P8e-P16e-P32e--P1024e- P2048e for
even parities).
For a 2 Kbytes page, four 512 bytes ECC calculations plus one for the spare area are required. Results
are stored in the GPMC_ECCj_RESULT registers (j = 1 to 9).
Figure 7-34. ECC Computation for a 512-Byte Data Stream (Read or Write)
Row 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
Row 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16o
P2048e
Row 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
Row 508 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16e
Row 509 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o P2048o
Row 510 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8e P16o
Row 511 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P8o
P4o P4e
256 byte
256 Bytes input
input
st
1st
1 row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
2ndt row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1024e
3rd row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
4th row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
123th row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
124th t row
124th bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1024o
125th row
125th bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
th
128 row
128th bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e
P8o P8e
512 Bytes
51-bytes input
input
st
1st
1 row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
2ndt row
2nd row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o P2048e
3rd
3rd row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
4th
4th row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
253th row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32e
th t P2048o
254
254th row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
th
255
255throw
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16e P32o
th
256
256th row
row bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P16o
P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e P1o P1e
P8o P8e
7.1.2.3.12.3.2.1 Requirements
Read and write accesses to a NAND flash take place by whole pages, in a predetermined sequence: first
the data byte page itself, then some spare bytes, including the BCH ECC (and other information). The
NAND IC can cache a full page, including spares, for read and write accesses.
Typical page write sequence:
• Sequential write to NAND cache of main data + spare data, for a page. ECC is calculated on the fly.
Calculated ECC may be inserted on the fly in the spares, or replaced by dummy accesses.
• When the calculated ECC is replaced by dummy accesses, it must be written to the cache in a second,
separate phase. The ECC module is disabled during that time.
• NAND writes its cache line (page) to the array
Typical page read sequence:
• Sequential read of a page. ECC is calculated on the fly.
• ECC module buffers status determines the presence of errors.
• Accesses to several memories may be interleaved by the GPMC, but only one of those memories can
be a NAND using the BCH engine at a time; in other words, only one BCH calculation (for example, for
a single page) can be on-going at any time. Note also that the sequential nature of NAND accesses
guarantees that the data is always written / read out in the same order. BCH-relevant accesses are
selected by the GPMCs chip-select.
• Each page may hold up to 4 Kbytes of data, spare bytes not included. This means up to 8 x 512-byte
BCH messages. Since all the data is written / read out first, followed by the BCH ECC, this means that
the BCH engine must be able to hold 8 104-bit remainders or syndromes (or smaller, 52-bit ones) at
the same time.
The BCH module has the capacity to store all remainders internally. After the page start, an internal
counter is used to detect the 512-byte sector boundaries. On those boundaries, the current remainder is
stored and the divider reset for the next calculation. At the end of the page, the BCH module contains all
remainders.
• NAND access cycles hold 8 or 16 bits of data each (1 or 2 bytes); Each NAND cycle takes at least 4
cycles of the GPMCs internal clock. This means the NAND flash timing parameters must define a
RDCYCLETIME and a WRCYCLETIME of at least 4 clock cycles after optimization when using the
BCH calculator.
• The spare area is assumed to be large enough to hold the BCH ECC, that is, to have at least a
message of 13 bytes available per 512-byte sector of data. The zone of unused spare area by the
ECC may or may not be protected by the same ECC scheme, by extending the BCH message beyond
512 bytes (maximum codeword is 1023-byte long, ECC included, which leaves a lot of space to cover
some spares bytes).
Table 7-11. Flattened BCH Codeword Mapping (512 Bytes + 104 Bits)
Message M(x) ECC R(x)
Bit number M4095 ... M0 R103 ... R0
If the message is extended by the addition of spare bytes to be protected by the same ECC, the principle
is still valid. For example, a 3-byte extension of the message gives a polynomial message M(x) of degree
((512 + 3) × 8) - 1 = 4119, for a total of 3 + 13 = 16 spare bytes of spare, all protected as part of the same
codeword.
The message and the ECC bits are manipulated and mapped in the GPMC byte-oriented system. The
ECC bits are stored in:
• GPMC_BCH_RESULT0_i
• GPMC_BCH_RESULT1_i
• GPMC_BCH_RESULT2_i
• GPMC_BCH_RESULT3_i
Table 7-14 and Table 7-15 show the mapping in memory of arbitrarily-sized messages, starting on access
(byte or 16-bit word) boundaries for more clarity. Note that message may actually start and stop on
arbitrary nibbles. A nibble is a 4-bit entity. The unused nibbles are not discarded, and they can still be
used by the BCH module, but as part of the next message section (for example, on another sectors ECC).
Table 7-17. Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble)
16-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
(S+1)/2 - 4 Nibble 4 Nibble 3 Nibble 6 Nibble 5
(S+1)/2 - 2 Nibble 0 (LSB) Nibble 2 Nibble 1
Table 7-18. Misaligned Nibble Mapping of Message in 16-bit NAND (2 Unused Nibble)
16-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
(S+2)/2 - 4 Nibble 3 Nibble 2 Nibble 5 Nibble 4
(S+2)/2 - 2 Nibble 1 Nibble 0 (LSB)
Table 7-19. Misaligned Nibble Mapping of Message in 16-bit NAND (3 Unused Nibble)
16-Bit Word
Byte Offset
4-Bit Most Significant Nibble 4-Bit Less Significant Nibble
0 Nibble S-3 Nibble S-4 (MSB) Nibble S-1 Nibble S-2
2 Nibble S-7 Nibble S-8 Nibble S-5 Nibble S-6
⋮ ⋮ ⋮ ⋮ ⋮
(S+3)/2 - 4 Nibble 2 Nibble 1 Nibble 4 Nibble 3
(S+3)/2 - 2 Nibble 0 (LSB)
Note that many other cases exist than the ones represented above, for example, where the message does
not start on a word boundary.
There are cases where the same NAND access contains both data and the ECC protecting that data. This
is the case when the data/ECC boundary (which can be on any nibble) does not coincide with an access
boundary. The ECC is calculated on-the-fly following the write. In that case, the write must also contain
part of the ECC because it is impossible to insert the ECC on-the-fly. Instead:
• During the initial page write (BCH encoding), the ECC is replaced by dummy bits. The BCH encoder is
by definition turned OFF during the ECC section, so the BCH result is unmodified.
• During a second phase, the ECC is written to the correct location, next to the actual data.
• The completed line buffer is then written to the NAND array.
M0
Manual mode
to ECC divider unused
Protected data Unused data
Mode Size 0 Size 1 P U
M1
Per-sector spares
Spares covered by sector ECC Sector data Sector data Sector spares Sector spares
per sector ECC mapping.
Data0 Data1 Prot0 Ecc0 Prot1 Ecc1
Mode Size0 Size1 512 bytes 512 bytes P E P E
M2
Per-sector spares
Spares covered by sector ECC Sector data Sector data Sector spares Sector spares
per sector, left-padded ECC.
Data0 Data1 Prot0 Pad Ecc0 Prot1 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes P 1 E P 1 E
M3
Per-sector spares
Spares covered by sector ECC, Sector data Sector data Sector spares Sector spares
ECC not right-aligned.
Data0 Data1 Prot0 Ecc0 U0 Prot1 Ecc1 U1
Mode Size0 Size1 512 bytes 512 bytes P E U P E U
M4
Per-sector spares
Spares not covered by ECC, Sector data Sector data Sector spares Sector spares
ECC right-aligned per sector.
Data0 Data1 Unprot0 Ecc0 Unprot1 Ecc1
Mode Size0 Size1 512 bytes 512 bytes U E U E
Figure 7-39. NAND Page Mapping and ECC: Pooled Spare Schemes
M5
Pooled spares
Spares covered by ECC0. Sector data Sector data Pooled page spares
All ECC at the end (of page).
Data0 Data1 Protected (pooled) Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes P E E
Write 7 P E 0 1 0 inactive
size0 size1 size1
Read 3 P E 0 1 0 1
size0 size1 size1
M6
Pooled spares
Spares covered by ECC0. Sector data Sector data Pooled page spares
All ECC at the end, left-padded.
Data0 Data1 Protected (pooled) Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes P 1 E 1 E
M7
Pooled spares
Spares not covered by ECC. Sector data Sector data Pooled page spares
All ECC at the end.
Data0 Data1 Unprotected (pooled) Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes U E E
U/S
Write 6 0 0 1 inactive
+E
size1 size1
Read 4 U E 0 1 inactive 0 1
size0 size1 size1
M8
Pooled spares
Spares not covered by ECC. Sector data Sector data Pooled page spares
All ECC at the end, left-padded.
Data0 Data1 Unprotected (pooled) Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes U 1 E 1 E
U/S
Write 6 0 0 1 inactive
+1+E
size1 size1
Read 9 U E 0 1 inactive 0 i. 1
size0 1 size1 1 size1
7.1.2.3.12.3.3.3 Per-Sector Spare Mapping, With ECC Separated at the End of the Page
In these schemes (Figure 7-40), each 512-byte sector of the main area is associated with two sections of
the spare area.
• ECC section, all aligned at the end of the page
• other data section, aligned before the ECCs, each of which may or may not be protected by its sectors
ECC
Figure 7-40. NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC
M9
Per-sector spares, separate ECC
Spares covered by sector ECC. Sector data Sector data non-ECC spares ECC
All ECC at the end.
Data0 Data1 Prot0 Prot1 Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes P P E E
Write 6 P E 0 1 0 1 inactive
size0 size0 size1 size1
Read 5 P E 0 1 0 1 0 1
size0 size0 size1 size1
M
Per-sector spares, separate ECC
10
Spares covered by sector ECC. Sector data Sector data non-ECC spares ECC
All ECC at the end, left-padded.
Data0 Data1 Prot0 Prot1 Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes P P 1 E 1 E
M
Per-sector spares, separate ECC
11 Spares not covered by ECC. Sector data Sector data non-ECC spares ECC
All ECC at the end.
Data0 Data1 Unprot0 Unprot1 Ecc0 Ecc1
Mode Size0 Size1 512 bytes 512 bytes U U E E
M
Per-sector spares, separate ECC
12
Spares not covered by ECC. Sector data Sector data non-ECC spares ECC
All ECC at the end, left-padded.
Data0 Data1 Unprot0 Unprot1 Pad Ecc0 Pad Ecc1
Mode Size0 Size1 512 bytes 512 bytes U U 1 E 1 E
NOTE: The COUNTVALUE value is only valid when the prefetch engine is active (started), and an
interrupt is only triggered when COUNTVALUE reaches 0, that is, when the prefetch engine
automatically goes from an active to an inactive state.
NOTE: The COUNTVALUE value is only valid if the write-posting engine is active and started, and
an interrupt is only issued when COUNTVALUE reaches 0, that is, when the posting engine
automatically goes from active to inactive.
In DMA filling mode, the DMAMode bit field in the GPMC_PREFETCH_CONFIG1[2] DMAMODE bit must
be set so that the GPMC issues a DMA hardware request when at least FIFOTHRESHOLD bytes-free
places are available in the FIFO. The DMA channel owning this DMA request must be programmed so
that a number of bytes equal to the value programmed in the FIFOTHRESHOLD bit field are written into
the FIFO during the DMA access. The DMA request remains active until the associated number of bytes
has effectively been written into the FIFO, and no other DMA request can be issued until the ongoing
active request has been completed.
Any potentially active DMA request is cleared when the prefetch engine goes from inactive to active
prefetch (STARTENGINE set to 1). The associated DMA channel must always be enabled by the MPU
after setting the STARTENGINE bit so that an out-of-date active DMA request does not trigger spurious
DMA transfers.
In write-posting mode, the DMA or the MPU fill the FIFO with no consideration to the associated byte
enables. Any byte stored in the FIFO is written into the memory device.
7.1.2.3.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
Access time to a NAND memory device can be optimized for back-to-back accesses if the associated CSn
signal is not deasserted between accesses. The GPMC access engine can track prefetch engine
accesses to optimize the access timing parameter programmed for the allocated chip-select, if no
accesses to other chip-selects (that is, interleaved accesses) occur. Similarly, the access engine also
eliminates the CYCLE2CYCLEDELAY even if CYCLE2CYCLESAMECSEN is set. This capability is limited
to the prefetch and write-posting engine accesses, and MPU accesses to a NAND memory device
(through the defined chip-select memory region or through the GPMC_NAND_DATA_i are never
optimized.
The GPMC_PREFETCH_CONFIG1[27] ENABLEOPTIMIZEDACCESS bit must be set to enable optimized
accesses. To optimize access time, the GPMC_PREFETCH_CONFIG1[30-28] CYCLEOPTIMIZATION
field defines the number of GPMC_FCLK cycles to be suppressed from the RDCYCLETIME,
WRCYCLETIME, RDACCESSTIME, WRACCESSTIME, CSOFFTIME, ADVOFFTIME, OEOFFTIME, and
WEOFFTIME timing parameters.
NAND Read Cycle Optimization Timing Description, in the case of back-to-back accesses to the NAND
flash through the prefetch engine, CYCLE2CYCLESAMECSEN is forced to 0 when using optimized
accesses. The first access uses the regular timing settings for this chip-select. All accesses after this one
use settings reduced by x clock cycles, x being defined by the GPMC_PREFETCH_CONFIG1[30-28]
CYCLEOPTIMIZATION field.
GPMC_FCLK
RDCYCLETIME
CSRDOFFTIME
nCS
nBE0/CLE
OEONTIME = 0 OEONTIME = 0
7.1.2.3.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
Any on-going read or write access from the prefetch and write-posting engine is completed before an
access to any other chip-select can be initiated. As a default, the arbiter uses a fixed-priority algorithm,
and the prefetch and write-posting engine has the lowest priority. The maximum latency added to access
starting time in this case equals the RDCYCLETIME or WRCYCLETIME (optimized or not) plus the
requested BUSTURNAROUND delay for bus turnaround completion programmed for the chip-select to
which the NAND device is connected to.
Alternatively, a round-robin arbitration can be used to prioritize accesses to the external bus. This
arbitration scheme is enabled by setting the GPMC_PREFETCH_CONFIG1[23] PFPWENROUNDROBIN
bit. When a request to another chip-select is received while the prefetch and write-posting engine is active,
priority is given to the new request. The request processed thereafter is the prefetch and write-posting
engine request, even if another interconnect request is passed in the mean time. The engine keeps
control of the bus for an additional number of requests programmed in the
GPMC_PREFETCH_CONFIG1[19-16] PFPWWEIGHTEDPRIO bit field. Control is then passed to the
direct interconnect request.
As an example, the round-robin arbitration scheme is selected with PFPWWEIGHTEDPRIO set to 2h.
Considering the prefetch and write-posting engine and the interconnect interface are always requesting
access to the external interface, the GPMC grants priority to the direct interconnect access for one
request. The GPMC then grants priority to the engine for three requests, and finnaly back to the direct
interconnect access, until the arbiter is reset when one of the two initiators stops initiating requests.
Start
initialization
GPMC
2. Enable GPMC pads
3. Reset GPMC
8. NAND chip-select
configuration
5. NOR chip-select
configuration
9. Write operations
(asynchronous)
6. NOR timings
configuration
configuration
GPMC
9. Read operations
(asynchronous)
13. Enable
chip-select
* Optional
End
NOTE: In the tables of this section, 'x' in Value column stands for 'depends on configuration'.
Start
Asynchronous Synchronous
write Type write
of access?
No Write Access
Asynchronous Synchronous
Operational mode: NOR interfacing
write write
operation operation
Asynchronous
Synchronous read
read Type
of access?
No read access
Synchronous Asynchronous
read read
operation operation
End
Figure 7-43 shows the typical connection between the GPMC module and an attached NOR Flash
memory.
Device
gpmc_a[26:16] 11
A [27:17] A[26:16]
gpmc_d[15:0] 16
A [16:1] / D [15:0] A/D[15:0]
gpmc_ncs[7:0]
nCS [7:0] nCE
gpmc_nadv_ale
ADV /ALE nAVD
gpmc_noe_nre
OE / RE nOE
gpmc_nwe
WE nWE
gpmc_nwp
WP nWP
gpmc_wait [1:0]
WAIT [1:0] RDY
gpmc_clk
DEVICECLK CLK
The following sections demonstrate how to calculate GPMC parameters for three access types:
• Synchronous burst read
• Asynchronous read
• Asynchronous single write
The following terms, which describe the timing interface between the controller and its attached device,
are used to calculate the timing parameters on the GPMC side:
• Read Access time (GPMC side): Time required to activate the clock + read access time requested on
the memory side + data setup time required for optimal capture of a burst of data
• Data setup time (GPMC side): Ensures a good capture of a burst of data (as opposed to taking a burst
of data out). One word of data is processed in one clock cycle (T = 9,615 ns). The read access time
between 2 bursts of data is tBACC = 5,2 ns. Therefore, data setup time is a clock period - tBACC =
4,415 ns of data setup.
• Access completion (GPMC side): (Different from page burst access time) Time required between the
last burst access and access completion: CSn/OEn hold time (CSn and OEn must be released at the
end of an access. These signals are held to allow the access to complete).
• Read cycle time (GPMC side): Read Access time + access completion
• Write cycle time for burst access: Not supported for NOR flash memory
Figure 7-44. Synchronous Burst Read Access (Timing Parameters in Clock Cycles)
2nd burst access RdCycleTime = 11
AccessTime = 10 3rd last burst access
FCLK
ClkActivationTime = 1 Access Completion
Data Setup
CLK
tIACC (access time on memory side)
AdvRdOffTime = 2
nADV
CsReadOffTime = RdCycleTime
nCS
OeOffTime = RdCycleTime
OeOnTime = 3
nOE
Use the following formula to calculate the RdCycleTime parameter for this typical access:
RdCycleTime = RdAccessTime + AccessCompletion = RdAccessTime + 1 clock cycle + tOEZ
• First, on the memory side, the external memory makes the data available to the output bus. This is the
memory-side read access time defined in Table 7-43: the number of clock cycles between the address
capture (ADVn rising edge) and the data valid on the output bus.
The GPMC requires some hold time to allow the data to be captured correctly and the access to be
finished.
• To read the data correctly, the GPMC must be configure to meet the data setup time requirement of
the memory; the GPMC module captures the data on the next rising edge. This is access time on the
GPMC side.
• There must also be a data hold time for correctly reading the data (checking that there is no OEn/CSn
deassertion while reading the data). This data hold time is 1 clock cycle (that is, AccessTime + 1).
• To complete the access, OEn/CSn signals are driven to high-impedance. AccessTime + 1 + tOEZ is
the read cycle time.
• Addresses can now be relatched and a new read cycle begun.
Figure 7-45. Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
Data capture on GPMC side: RdAccessTime = 9 RdCycleTime = 11
FCLK
Data Setup time
CsReadOffTime = 10
nCS
AdvRdOffTime = 1
nADV
tOEZ
OeOffTime = 10
OeOnTime = 3
nOE
For asynchronous single write access, write cycle time is WrCycleTime = WeOffTime + AccessCompletion
= WeOffTime + 1. For the AccesCompletion, the GPMC requires 1 cycle of data hold time (CSn de-
assertion).
Figure 7-46. Asynchronous Single Write Access (Timing Parameters in Clock Cycles)
WrCycleTime = 6
FCLK
CsWriteOffTime = 6
nCS
AdvWrOffTime = 1
nADV
Access Completion / Data Hold time
WeOffTime = 5
7.2 OCMC-RAM
7.2.1 Introduction
7.2.2 Integration
This device includes a single instantiation of the on-chip memory controller interfacing to a single 64K
bank of RAM.
Control
Module
7.3 EMIF
7.3.1 Introduction
7.3.1.1 Features
The general features of the EMIF module are as follows:
• 16-bit data path to external SDRAM memory
• One 128-bit OCPIP 2.2 interface
• Support for the following memory types:
– mDDR (LPDDR1)
– DDR2
– DDR3
External memory configurations supported:
• Memory device capacity
– Up to 1G Byte addressability
• Flexible bank/row/column/chip-select address multiplexing schemes
• Device driver strength feature for mobile DDR supported
• Supports following CAS latencies:
– DDR2 => 2, 3, 4, 5, 6, and 7
– DDR3 => 5, 6, 7, 8, 9, 10, and 11
– mDDR => 2, 3, and 4
• Supports following number of internal banks:
– DDR2 => 1, 2, 4, and 8
– DDR3 => 1, 2, 4, and 8
– mDDR => 1, 2, and 4
• Supports 256, 512, 1024, and 2048-word page sizes
• Supports burst length of 8 (sequential burst)
• Write/read leveling/calibration and data eye training in conjunction with DID
• Self Refresh and Power-Down modes for low power:
– Flexible OCP to DDR address mapping to support Partial Array Self Refresh in LPDDR1, DDR2
and DDR3.
– Temperature Controlled Self Refresh for LPDDR1 and DDR3 having on-chip temperature sensor.
• Periodic ZQ calibration for DDR3
• ODT on DDR2 and DDR3
• Prioritized refresh scheduling
• Programmable SDRAM refresh rate and backlog counter
• Programmable SDRAM timing parameters
• Big and little endian modes
7.3.2 Integration
DDR_CLK
DDR_CLKn
DDR_CKE
DDR_WEn
DDR_CSN0
DDR_RASn
DDR_CASn
DDR_DQM[1:0]
DDR_DQS[1:0]
DDR_DQSn[1:0]
DDR_ODT
DDR_RST
DDR_BA[2:0]
DDR_A[15:0]
DDR_D[15:0]
DDR_VTP
DDR_RSTn
DDR_VREF
128-bit
OCP DDR2/3/mDDR
Memory
data[15:8] to/from DDR
Controller data
fifo_we_out
Data Macro 1
fifo_we_in IO 1
p/n
VTP Macro
Where
fifo_we_out = DQS enable output for timing match between DQS and system (Memory) clock.
fifo_we_in = DQS enable input for timing match between DQS and system (Memory) clock.
Memory
Mapped
Registers
OCP
Register Read Data FIFO
Return
Control
Data
The command FIFO stores all the commands coming in on the OCP command interface.
The Write Data FIFO stores the write data for all the write transactions coming in on the OCP write data
interface.
The Return Command FIFO stores all the return transactions that are to be issued to the OCP return
interface. These include the write status return and the read data return commands.
There are two Read Data FIFOs that store the read data to be sent to the OCP return interface. One Read
Data FIFO stores read data from the memory mapped registers and other Read Data FIFO stores read
data from external memory.
The data macro is a bidirectional interface. It is used to transmit data from the memory controller to the
external memory chip during a write operation and receive data from memory and transmit it to the
memory controller during a read operation.
During a write operation, the data macro translates 32/16-bit words from memory controller to 8-bit words
and transmits them at double the bit rate to the memory along with the strobe. The strobe is center-
aligned to the data. Data can be prevented from writing to the memory using data mask signal.
During a read operation, the data macro receives 8-bit DDR data along with the strobe and converts it to
32/16- bit words and transmits them to the memory controller along with the read-valid signals.
When addressing SDRAM, if the REG_IBANK_POS field in the SDRAM Config register is set to 0, and the
REG_EBANK_POS field in the SDRAM Config 2 register is also set to 0, the DDR2/3/mDDR memory
controller uses the three fields, IBANK, EBANK and PAGESIZE in the SDRAM Config register to
determine the mapping from source address to SDRAM row, column, bank, and chip select. If the
REG_IBANK_POS field in the SDRAM Config register is set to 1, 2, or 3, or the REG_EBANK_POS field
in the SDRAM Config 2 register is set to 1, the DDR2/3/mDDR memory controller uses the 4 fields -
IBANK, EBANK, PAGESIZE, and ROWSIZE in the SDRAM Config register to determine the mapping from
source address to SDRAM row, column, bank, and chip select. In all cases the DDR2/3/mDDR memory
controller considers its SDRAM address space to be a single logical block regardless of the number of
physical devices or whether the devices are mapped across 1 or 2 DDR2/3/mDDR memory controller chip
selects.
Table 7-211. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=0 and
REG_EBANK_POS=0
Logical Address
Row Address Chip Select Bank Address Column Address
# of bits defined by EBANK of # of bits defined by IBANK of # of bits defined by PAGESIZE
SDRCR SDRCR of SDRCR
16 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 3 bits PAGESIZE=3 => 11 bits
Table 7-212. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=1 and
REG_EBANK_POS=0
Logical Address
Bank Address[2] Row Address Chip Select Bank Address[1:0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
IBANK of SDRCR RSIZE of SDRCR EBANK of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 0 bits RSIZE=1 => 10 bits EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 0 bits RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 1 bit RSIZE=3 => 12 bits IBANK=3 => 3 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Table 7-213. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=2 and
REG_EBANK_POS=0
Logical Address
Bank Address[2:1] Row Address Chip Select Bank Address[0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
IBANK of SDRCR RSIZE of SDRCR EBANK of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 0 bits RSIZE=1 => 10 bits EBANK=1 => 1 bit IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 1 bit RSIZE=2 => 11 bits IBANK=2 => 1 bit PAGESIZE=2 => 10 bits
IBANK=3 => 2 bits RSIZE=3 => 12 bits IBANK=3 => 1 bit PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Table 7-214. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=3 and
REG_EBANK_POS=0
Logical Address
Bank Address Row Address Chip Select Column Address
# of bits defined by IBANK of # of bits defined by RSIZE of # of bits defined by EBANK of # of bits defined by PAGESIZE
SDRCR SDRCR SDRCR of SDRCR
IBANK=0 => 0 bits RSIZE=0 => 9 bits EBANK=0 => 0 bits PAGESIZE=0 => 8 bits
IBANK=1 => 1 bit RSIZE=1 => 10 bits EBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 2 bits RSIZE=2 => 11 bits PAGESIZE=2 => 10 bits
IBANK=3 => 3 bits RSIZE=3 => 12 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Table 7-215. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=0 and
REG_EBANK_POS=1
Logical Address
Chip Select Row Address Bank Address Column Address
# of bits defined by EBANK of # of bits defined by RSIZE of # of bits defined by IBANK of # of bits defined by PAGESIZE
SDRCR SDRCR SDRCR of SDRCR
EBANK=0 => 0 bits RSIZE=0 => 9 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
RSIZE=3 => 12 bits IBANK=3 => 3 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Table 7-216. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=1 and
REG_EBANK_POS = 1
Logical Address
Chip Select Bank Address[2] Row Address Bank Address[1:0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
EBANK of SDRCR IBANK of SDRCR RSIZE of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
EBANK=0 => 0 bits IBANK=0 => 0 bits RSIZE=0 => 9 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
Table 7-216. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=1 and
REG_EBANK_POS = 1 (continued)
Logical Address
Chip Select Bank Address[2] Row Address Bank Address[1:0] Column Address
EBANK=1 => 1 bit IBANK=1 => 0 bits RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 0 bits RSIZE=2 => 11 bits IBANK=2 => 2 bits PAGESIZE=2 => 10 bits
IBANK=3 => 1 bit RSIZE=3 => 12 bits IBANK=3 => 2 bits PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Table 7-217. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=2 and
REG_EBANK_POS = 1
Logical Address
Chip Select Bank Address[2:1] Row Address Bank Address[0] Column Address
# of bits defined by # of bits defined by # of bits defined by # of bits defined by # of bits defined by
EBANK of SDRCR IBANK of SDRCR RSIZE of SDRCR IBANK of SDRCR PAGESIZE of SDRCR
EBANK=0 => 0 bits IBANK=0 => 0 bits RSIZE=0 => 9 bits IBANK=0 => 0 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit IBANK=1 => 0 bits RSIZE=1 => 10 bits IBANK=1 => 1 bit PAGESIZE=1 => 9 bits
IBANK=2 => 1 bit RSIZE=2 => 11 bits IBANK=2 => 1 bit PAGESIZE=2 => 10 bits
IBANK=3 => 2 bits RSIZE=3 => 12 bits IBANK=3 => 1 bit PAGESIZE=3 => 11 bits
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Table 7-218. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=3 and
REG_EBANK_POS=1
Logical Address
Chip Select Bank Address Row Address Column Address
# of bits defined by EBANK of # of bits defined by IBANK of # of bits defined by RSIZE of # of bits defined by PAGESIZE
SDRCR SDRCR SDRCR of SDRCR
EBANK=0 => 0 bits IBANK=0 => 0 bits RSIZE=0 => 9 bits PAGESIZE=0 => 8 bits
EBANK=1 => 1 bit IBANK=1 => 1 bit RSIZE=1 => 10 bits PAGESIZE=1 => 9 bits
IBANK=2 => 2 bits RSIZE=2 => 11 bits PAGESIZE=2 => 10 bits
IBANK=3 => 3 bits RSIZE=3 => 12 bits PAGESIZE=3 => 11 bits
Table 7-218. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=3 and
REG_EBANK_POS=1 (continued)
Logical Address
Chip Select Bank Address Row Address Column Address
RSIZE=4 => 13 bits
RSIZE=5 => 14 bits
RSIZE=6 => 15 bits
RSIZE=7 => 16 bits
Since the DDR2/3/mDDR memory controller interleaves among less number of banks when
IBANK_POS!= 0 or EBANK_POS= 1, these cases are lower in performance than the IBANK_POS= 0
case. Thus these cases are only recommended to be used along with partial array self-refresh where
performance can be traded off for power savings.
1. (Highest priority) SDRAM refresh request due to Refresh Must level of refresh urgency reached (see
Section 7.3.3.5.5).
2. Request for a read or a write.
3. SDRAM Activate commands.
4. SDRAM Deactivate commands.
5. SDRAM Deep Power-Down request.
6. SDRAM clock stop or Power-Down request.
7. SDRAM refresh request due to Refresh May or Release level of refresh urgency reached (Refer
Section Refresh Scheduling)
8. (Lowest priority) SDRAM self-refresh request.
NOTE: Leaving the REG_COS bits at their default value (FFh) in the Interface Configuration register
(OCP_CONFIG) disables this feature of the DDR2/3/mDDR memory controller. This means
commands can stay in the command FIFO indefinitely. Therefore, these bits should be set to
FEh immediately following reset to enable this feature with the highest level of allowable
memory transfers. It is suggested that system-level prioritization be set to avoid placing high-
bandwidth masters on the highest priority levels. These bits can be left as FEh unless
advanced bandwidth/prioritization control is required.
The DDR2/3/mDDR memory controller starts servicing new memory accesses after Refresh Release level
is cleared. If any of the commands in the Command FIFO have class of service latency counters that are
expired, the DDR2/3/mDDR memory controller will not wait for Refresh Release level to be cleared but will
only perform one refresh command and exit the refresh state.
5. Issues a LOAD MODE REGISTER command to the extended mode register 3 (pad_ba_o[2:0] = 0x3)
with pad_a_o[15:0] = 0x0.
6. Issues a LOAD MODE REGISTER command to the extended mode register 1 (pad_ba_o[2:0] = 0x1)
with the pad_a_o bits set as follows:
7. Issues a LOAD MODE REGISTER command to the mode register (pad_ba_o[2:0] = 0x0) with the
pad_a_o bits set as follows:
8. After 267 clock cycles, issues a PRECHARGE command with pad_a_o[10] held high to indicate all
banks.
9. After 2 AUTO REFRESH commands, issues a LOAD MODE REGISTER command to the mode
register (pad_ba_o[2:0] = 0x0) with the pad_a_o bits set as follows:
10. Issues a LOAD MODE REGISTER command to the extended mode register 1 (pad_ba_o[2:0] = 0x1)
with the pad_a_o bits set as follows:
11. Issues a LOAD MODE REGISTER command to the extended mode register 1 (pad_ba_o[2:0] = 0x1)
with the pad_a_o bits equal to step 6.
12. If the reg_ddr_disable_dll bit in the SDRAM Config register is 1, issues a LOAD MODE REGISTER
command to the extended mode register 1 (pad_ba_o[2:0] = 0x1) with the pad_a_o bits, set as follows:
4. Issues a LOAD MODE REGISTER command to the extended mode register 3 (pad_ba_o[2:0] = 0x3)
with pad_a_o[15:0] = 0x0.
5. Issues a LOAD MODE REGISTER command to the extended mode register 1 (pad_ba_o[2:0] = 0x1)
with the pad_a_o bits set as follows:
6. Issues a LOAD MODE REGISTER command to the mode register (pad_ba_o[2:0] = 0x0) with the
pad_a_o bits set as follows:
4. Issues a LOAD MODE REGISTER command to the extended mode register (pad_ba_o[2:0] = 0x2)
with the pad_a_o bits set as follows:
NOTE: Please refer the device specific data sheet to know the type of leveling supported.
The memory controller supports incremental leveling to better track voltage and temperature changes
during normal operation. The incremental leveling can be enabled by writing a non-zero value to the
REG_WRLVLINC_INT, REG_RDLVLGATEINC_INT, and REG_RDLVLINC_INT fields in the Read-Write
Leveling Control register(RWLCR). The memory controller periodically triggers incremental write leveling
every time REG_WRLVLINC_INT expires. In other words, the REG_WRLVLINC_INT defines the interval
between successive incremental write leveling.
Similarly, the memory controller periodically triggers incremental read DQS gate training every time
REG_RDLVLGATEINC_INT expires, and triggers incremental read data eye training every time
REG_RDLVLINC_INT expires.
To minimize impact on bandwidth, the software can program these intervals such that these three
intervals do not expire at same time. The value of interval programmed is dependent on the slope of
voltage and temperature changes.
The memory controller supports increasing the rate of incremental leveling automatically for a defined
period of time. This can be achieved by programming the Read-Write Leveling Ramp Window
register(RDWR_LVL_RMP_WIN) and the Read-Write Leveling Ramp Control
register(RDWR_LVL_RMP_CTRL). Whenever a pulse is received, the memory controller would use the
intervals programmed in the Read-Write Leveling Ramp Control register until the
REG_RDWRLVLINC_RMP_WIN in the Read-Write Leveling Ramp Window register expires. After the
expiration of REG_RDWRLVLINC_RMP_WIN the memory controller switches back to use the intervals
programmed in the Read-Write Leveling Control register.
To guarantee none of the incremental leveling events are missed, the REG_RDWRLVLINC_RMP_WIN
must be programmed greater than the intervals in the Read-Write Leveling Ramp Control register.
If the memory controller is in Self-Refresh or Power-Down modes when any of the incremental leveling
intervals expire, the memory controller will exit Self-Refresh or Power-Down mode, perform the required
leveling, and then re-enter the Self-Refresh or Power-Down mode. The memory controller also triggers
incremental leveling on Self-Refresh exit.
When the SDRAM is in power-down, the memory controller services register accesses as normal. If the
REG_LP_MODE field is set not equal to 4, or an SDRAM access is requested, or the Refresh Must level
is reached while the SDRAM is in power-down, the memory controller will bring the SDRAM out of power-
down. For DDR3, memory controller will also exit power-down to perform incremental leveling.
Exit sequence of power-down mode for DDR2, DDR3 and LPDDR1: The memory controller
• Drives DDR_CKE high after T_CKE + 1 cycles have elapsed since the POWER-DOWN command was
issued. The value of T_CKE is taken from SDRAM Timing 2 register.
• Waits for T_XP + 1 cycles. The value of T_XP is taken from SDRAM Timing 2 register.
• Enters its idle state and can issue any commands.
7.3.5.17 OCP_CFG_VAL_2 Register (offset = 5Ch) [reset = 00021616 00002011 00000000 00000000
00000000h]
OCP_CFG_VAL_2 (Interface Configuration Value 2) is shown in Figure 7-220 and described in Table 7-
238.
7.3.5.30 Read-Write Leveling Ramp Window Register (offset = D4h) [reset = 0h]
Read-Write Leveling Ramp Window is shown in Figure 7-233 and described in Table 7-251.
7.3.5.31 Read-Write Leveling Ramp Control Register (offset = D8h) [reset = 0h]
Read-Write Leveling Ramp Control is shown in Figure 7-234 and described in Table 7-252.
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
7.3.5.35 Priority to Class of Service Mapping Register (offset = 100h) [reset = 0h]
Priority to Class of Service Mapping is shown in Figure 7-238 and described in Table 7-256.
7.3.5.36 Connection ID to Class of Service 1 Mapping Register (offset = 104h) [reset = 0h]
Connection ID to Class of Service 1 Mapping is shown in Figure 7-239 and described in Table 7-257.
7.3.5.37 Connection ID to Class of Service 2 Mapping Register (offset = 108h) [reset = 0h]
Connection ID to Class of Service 2 Mapping is shown in Figure 7-240 and described in Table 7-258.
7.3.5.38 Read Write Execution Threshold Register (offset = 120h) [reset = 00000305h]
Read Write Execution Threshold is shown in Figure 7-241 and described in Table 7-259.
Figure 7-242. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
31 16
Reserved
R-0
15 10 9 0
Reserved CMD_SLAVE_RATIO
R-0 W-100h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-261. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-10 Reserved Reserved
9-0 CMD_SLAVE_RATIO 0-100h Ratio value for address/command launch timing in DDR PHY macro. This is the fraction of a
clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other
words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to
get the delay value for the slave delay line.
Figure 7-243. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
31 16
Reserved
R-0
15 4 3 0
Reserved DLL_LOCK_DIFF
R-0 W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-262. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
(CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions
Bit Field Value Description
31-4 Reserved Reserved
3-0 DLL_LOCK_DIFF 0-4h The max number of delay line taps variation allowed while maintaining the master DLL lock.This is
calculated as total jitter/ delay line tap size, where total jitter is half of (incoming clock jitter (pp) +
delay line jitter (pp)).
Figure 7-244. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0)
31 16
Reserved
R-0
15 1 0
Reserved INVERT_CLK_SEL
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-263. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 INVERT_CLK_SE Inverts the polarity of DRAM clock.
L
0 Core clock is passed on to DRAM
1 inverted core clock is passed on to DRAM
7.3.6.4 DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Read DQS Slave Ratio
Register(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-245. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0))
31 i 19 16
Reserved Reserved
R-0h R-0h
15 10 9 0
Reserved RD_DQS_SLAVE_RATIO_CS0
R-0h W-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-264. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved Reserved
19-10 Reserved 0h Reserved
9-0 RD_DQS_SLAVE Ratio value for Read DQS slave DLL for CS0.
_RATIO_CS0
40h This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of
256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number
over 256 to get the delay value for the slave delay line.
7.3.6.5 DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Write DQS Slave Ratio
Register(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) is shown in the figure and table below.
Table 7-265. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0h
15 10 9 0
Reserved WR_DQS_SLAVE_RATIO_CS0
R-0 W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-266. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register(
DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reserved
19-10 Reserved Reserved
9-0 WR_DQS_SLAVE_R Ratio value for Write DQS slave DLL for CS0.
ATIO_CS0
This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in
units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by
this number over 256 to get the delay value for the slave delay line.
7.3.6.6 DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
The DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) is showin in the figure and table below.
Figure 7-246. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved WRLVL_INIT_RATIO_CS0
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-267. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reserved
19-10 Reserved 0h Reserved
9-0 WRLVL_INIT_RATIO 0h The user programmable init ratio used by Write Leveling FSM when
_CS0 DATA0/1_REG_PHY_WRLVL_INIT_MODE_0 register value set to 1
7.3.6.7 DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
The DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) is shown in the figure and table below..
Figure 7-247. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
31 16
Reserved
R-0
15 1 0
Reserved WRLVL_INIT_MODE_S
EL
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-268. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
Bit Field Value Description
31-1 Reserved 0 Reserved
0 WRLVL_INIT_MO The user programmable init ratio selection mode for Write Leveling FSM.
DE_SEL
0 Selects a starting ratio value based on Write Leveling of previous data slice.
1 Selects a starting ratio value based in register DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0 value
programmed by the user.
7.3.6.8 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
The DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) is shown in the figure and table below.
Figure 7-248. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved GATELVL_INIT_RATIO_CS0
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-269. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved Reserved
19-10 Reserved 0h Reserved
9-0 GATELVL_INIT_RATIO_CS0 0h The user programmable init ratio used by DQS Gate Training FSM when
DATA0/1/_REG_PHY_GATELVL_INIT_MODE_0 register value set to 1.
7.3.6.9 DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0)
The DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection
Register(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) is shown in the figure and table below.
Figure 7-249. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0)
31 16
Reserved
R-0
15 1 0
Reserved GATELVL _INIT _MODE_SEL
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-270. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 GATELVL_INIT_MODE_SEL User programmable init ratio selection mode for DQS Gate Training FSM.
0 Selects a starting ratio value based on Write Leveling of the same data slice.
1 selects a starting ratio value based on
DATA0/1_REG_PHY_GATELVL_INIT_RATIO_0 value programmed by the user.
7.3.6.10 DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-250. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-0 R-0
15 10 9 0
Reserved FIFO_WE_SLAVE_RATIO_CS0
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-271. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reserved
19-10 Reserved 0h Reserved
9-0 RD_DQS_GATE _SLAVE_RATIO_CS0 0h Ratio value for fifo we for CS0.
7.3.6.11 DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
The DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) is shown in the figure and table below.
Figure 7-251. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
31 20 19 16
Reserved Reserved
R-40h R-0h
15 10 9 0
Reserved WR_DATA_SLAVE_RATIO_CS0
R-0h W-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-272. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) Field Descriptions
Bit Field Value Description
31-20 Reserved 40h Reserved
19-10 Reserved 0
9-0 WR_DATA_SLAVE_RATIO_CS0 40h Ratio value for write data slave DLL for CS0.
This is the fraction of a clock cycle represented by the shift to be applied to
the write DQ muxes in units of 256ths. In other words, the full-cycle tap
value from the master DLL will be scaled by this number over 256 to get the
delay value for the slave delay line.
7.3.6.12 DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
The DATA0/1_REG_PHY_USE_RANK0_DELAYS is shown in Figure 7-252 and described in Table 7-273.
Figure 7-252. DDR PHY Data Macro 0/1 Delay Selection Register
(DATA0/1_REG_PHY_USE_RANK0_DELAYS)
31 16
Reserved
R-0
15 1 0
Reserved RANK0 _DELAY
R-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-273. DDR PHY Data Macro 0/1 Delay Selection Register
(DATA0/1_REG_PHY_USE_RANK0_DELAYS) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 PHY_USE_RANK Delay Selection
0_DELAYS_0
0 Each Rank uses its own delay. (Recommended). This is applicable only in case of DDR3
1 Rank 0 delays are used for all ranks. This must be set to 1 for DDR2 and mDDR.
7.3.6.13 DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0)
The DDR PHY Data 0/1 DLL Lock Difference Register (DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) is
shown in the figure and table below. This register should be left at its default value and should not be
altered for proper operation.
Figure 7-253. DDR PHY Data 0/1 DLL Lock Difference Register
(DATA0/1_REG_PHY_DLL_LOCK_DIFF_0)
31 16
Reserved
R-0
15 4 3 0
Reserved DLL_LOCK_DIFF
R-0 W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-274. DDR PHY Data 0/1 DLL Lock Difference Register
(DATA0/1_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions
Bit Field Value Description
31-4 Reserved Reserved
3-0 DLL_LOCK_DIFF 0-4h The max number of delay line taps variation allowed while maintaining the master DLL lock.This is
calculated as total jitter/ delay line tap size, where total jitter is half of (incoming clock jitter (pp) +
delay line jitter (pp)).
7.3.6.14 Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1
_REG_PHY_DQ_OFFSET_0)
The Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1 _REG_PHY_DQ_OFFSET_0)
is shown in the figure and table below.
Figure 7-254. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1
_REG_PHY_DQ_OFFSET_0)
31 16
Reserved
R-0
15 7 6 0
Reserved Offset value from DQS to DQ
R-0 RW-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-275. Offset value from DQS to DQ for Data Macro Register (DATA0/DATA1
_REG_PHY_DQ_OFFSET_0) Field Descriptions
Bit Field Value Description
31-7 Reserved Reserved
6-0 Offset value from 0h Default value 40 equates to a 90 degree shift.
DQS to DQ
7.4 ELM
7.4.1 Introduction
Non-managed NAND flash memories can be dense and nonvolatile in their own nature, but error-prone.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction
process is delegated to the memory controller.
The general-purpose memory controller (GPMC) probes data read from an external NAND flash and uses
this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each
syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data,
parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation
is based on a Bose-ChaudhurI-Hocquenghem (BCH) algorithm. The error-location module (ELM) extracts
error addresses from these syndrome polynomials.
Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and
give the location of each error bit. The actual data is not required to complete the error-correction
algorithm. Errors can be reported anywhere in the NAND flash block, including in the parity bits.
The maximum acceptable number of errors that can be corrected depends on a programmable
configuration parameter. 4-, 8-, and 16-bit error-correction levels are supported. The ELM relies on a static
and fixed definition of the generator polynomial for each error-correction level that corresponds to the
generator polynomials defined in the GPMC (there are three fixed polynomial for the three correction error
levels). A larger number of errors than the programmed error-correction level may be detected, but the
ELM cannot correct them all. The offending block is then tagged as uncorrectable in the associated
computation exit status register. If the computation is successful, that is, if the number of errors detected
does not exceed the maximum value authorized for the chosen correction capability, the exit status
register contains the information on the number of detected errors.
When the error-location process completes, an interrupt is triggered to inform the central processing unit
(CPU) that its status can be checked. The number of detected errors and their locations in the NAND
block can be retrieved from the module through register accesses.
7.4.2 Integration
The error location module (ELM) is used to extract error addresses from syndrome polynomials generated
using a BCH algorithm. Each of these polynomials gives a status of the read operations for a 512 bytes
block from a NAND flash and its associated BCH parity bits, plus optionally some spare area information.
The ELM is intended to be used in conjunction with the GPMC. Syndrome polynomials generated on-the-
fly when reading a NAND Flash page and stored in GPMC registers are passed to the ELM module. The
MPU can then easily correct the data block by flipping the bits pointed to by the ELM error locations
outputs.
PORSIDLEACK[1:0]
PIMIDLEREQ
CAUTION
The PRCM module has no hardware means of reading CLOCKACTIVITY
settings. Thus, software must ensure consistent programming between the
ELM CLOCKACTIVITY and ELM clock PRCM control bits.
In all other cases, the engine goes through the entire error-location process. Each time an error-location is
found, it is logged in the associated ECC_ERROR_LOCATION bit field. The first error detected is logged
in the ELM_ERROR_LOCATION_0_i[12:0] ECC_ERROR_LOCATION bit field; the second in the
ELM_ERROR_LOCATION_1_i[12:0] ECC_ERROR_LOCATION bit field, and so on.
NOTE: Do not modify page setting parameters in the ELM_PAGE_CTRL register unless the engine
is idle, no polynomial input is valid, and all interrupts have been cleared.
Next page can be correctly processed after a page is fully processed, when all tagged polynomials have
been processed (ELM_IRQSTATUS[i] LOC_VALID_i = 0x1 for all syndrome polynomials i used in the
page).
The NAND flash data in the sector are seen as a polynomial of degree 4223 (number of bits in a 528 byte
buffer minus 1), with each data bit being a coefficient in the polynomial. When reading from a NAND flash
using the GPMC module, computation of the polynomial syndrome assumes that the first NAND word read
at address 0x0 contains the highest-order coefficient in the message. Furthermore, in the 16-bit NAND
word, bits are ordered from bit 7 to bit 0, then from bit 15 to bit 8. Based on this convention, an address
table of the data buffer can be built. NAND memory addresses in Table 7-285 are given in decimal format.
The table can now be used to determine which bits in the buffer were incorrect and must be flipped. In this
example, the first bit to be flipped is bit 4 from the 49th byte read from memory. It is up to the processor to
correctly map this word to the copied buffer and to flip this bit. The same process must be repeated for all
detected errors.
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8.1.1 Introduction
The device power-management architecture ensures maximum performance and operation time for user
satisfaction (audio/video support) while offering versatile power-management techniques for maximum
design flexibility, depending on application requirements. This introduction contains the following
information:
• Power-management architecture building blocks for the device
• State-of-the-art power-management techniques supported by the power-management architecture of
the device
Device interconnect
Registers Interconnect
PRCM interface
Functional clock
X_FCLK
prcm-001
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For the idle protocol management on the PRCM module side, the behavior of the PRCM module is
configured in the CM_<Power domain>_<module>_CLKCTRL[x] MODULEMODE bit field. Based on the
configured behavior, the PRCM module asserts the idle request to the module unconditionally (that is,
immediately when the software requests).
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In addition to the IDLE and STANDBY protocol, PRCM offers also the possibility to manage optional
clocks, through a direct SW control: “OptFclken” bit from programming register.
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FCLK2
ICLK1
CLK1
Module 1 Module 22
Module
prcm-002
Figure above is an example of two clock managers: CM_a and CM_b. Each clock manager manages a
clock domain. The clock domain of CM_b is composed of two clocks: a functional clock (FCLK2) and an
interface clock (ICLK1), while the clock domain of CM_a consists of a clock (CLK1) that is used by the
module as a functional and interface clock. The clocks to Module 2 can be gated independently of the
clock to Module 1, thus ensuring power savings when Module 2 is not in use. The PRCM module lets
software check the status of the clock domain functional clocks. The CM_<Clock domain>_CLKSTCTRL[x]
CLKACTIVITY_<FCLK/Clock name_FCLK> bit in the PRCM module identifies the state of the functional
clock(s) within the clock domain. Table shows the possible states of the functional clock.
prcm-003
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Each clock domain transition behavior is managed by an associated register bit field in the CM_<Clock
domain>_CLKSTCTRL[x] CLKTRCTRL PRCM module
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PRCM
PM
Vdd
Varray
Memory array
Logic power
Logic power
Memory logic
power switch
power switch
switch
switch
Memory Memory Memory Flip-flop Flip-flop
array array logic logic logic
To minimize device power consumption, the modules are grouped into power domains. A power domain
can be split into a logic area and a memory area.
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8.1.4.3.1 Active
In Active mode, the supply to all voltage rails must be maintained. All power domains come up in ON state
and the device is fully functional.
8.1.4.3.2 Standby
The device can be placed in Standby mode to reduce power consumption during low activity levels. This
first level of power management allows you to maintain the device context for fast resume times. The main
characteristics of this mode which distinguish it from Active mode are:
• All modules are clock gated except GPIOs
• PLLs may be placed in bypass mode if downstream clocking does not require full performance
• Voltage domains VDD_MPU and VDD_CORE voltage levels can be reduced to OPP50 levels because
the required performance of the entire device is reduced
• MPU power domain (PD_MPU) is in OFF state
• DDR memory is in low power self-refresh mode.
Further power reduction can be achieved in this mode if the RTC function is not required. See
Section 8.1.4.3.6, Internal RTC LDO.
The above conditions result in lower power consumption than Active mode but require the user to save the
MPU context to OCMC RAM or DDR to resume properly upon wakeup. Contents of the internal SRAM are
lost because PD_MPU is turned OFF. Wakeup in Standby mode is achieved using any GPIO. GPIO
wakeup is possible by switching the pad to GPIO mode and configuring the corresponding GPIO bank for
generating an interrupt to the MPUSS. Note that pads that do not have a GPIO muxmode (for example,
ADC or USB), cannot cause these wakeups. If additional or other wakeup sources are required, the
associated peripheral module clock and interconnect clock domain should remain enabled (this may
require the associated PLL to remain locked) and the module must be configured appropriately for wakeup
by configuring it to generate an interrupt to the MPUSS.
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8.1.4.3.3 DeepSleep1
DeepSleep1 mode enables lower power consumption than Standby mode. The main characteristic of this
mode which distinguish it from Standby mode is the main oscillator (OSC0) is disabled.
DeepSleep1 is the lowest sleep mode required for certain USB wakeup modes. See Section 8.1.4.3.7,
Supported Low Power USB Wakeup Scenarios, for more information.
Further power reduction can be achieved in this mode if the RTC function is not required. See
Section 8.1.4.3.6, Internal RTC LDO.
Similar to Standby mode, the contents of the internal SRAM are lost because PD_MPU is turned OFF. In
addition, the contents of the SDRAM are preserved by placing the SDRAM in self-refresh. Activity on
wakeup peripherals via wake-up events enables the master crystal oscillator using the oscillator control
circuit. The wakeup events also interrupt Cortex-M3. See Section 8.1.4.5, Wakeup Sources/Events, for
details on wakeup sources.
8.1.4.3.4 DeepSleep0
DeepSleep0 mode enables lower power consumption than DeepSleep1. The main characteristics of the
mode which distinguish it from other higher power modes are:
• All on-chip power domains are shut off (except PD_WKUP and PD_RTC remain ON) to reduce power
leakage
• VDD_CORE power (except VDDA analog) to DPLLs is turned OFF using dpll_pwr_sw_ctrl register (PG
2.x only)
• VDDS_SRAM_CORE_BG is in retention using SMA2.vsldo_core_auto_ramp_en (PG2.x only)
DeepSleep0 mode is typically used during periods of inactivity when the user requires very low power
while waiting for an event that requires processing or higher performance. This is the lowest power mode
which still includes DDR in self-refresh, so wakeup events do not require a full cold boot, which greatly
reduces wakeup latencies over RTC-only mode.
Further power reduction can be achieved in this mode if the RTC function is not required. See
Section 8.1.4.3.6, Internal RTC LDO.
Similar to DeepSleep1 mode, the contents of the internal SRAM are lost because PD_MPU is turned OFF.
Before entering DeepSleep0 mode, peripheral and MPU context must be saved in the DDR. Upon
wakeup, the boot ROM executes and checks to see if it has resumed from a DeepSleep0 state. If so, it
redirects to the DDR to continue the resume process. Because power to PD_WKUP is ON throughout
DeepSleep0, power to key modules such as GPIO0, I2C, and others is maintained to allow wakeup events
to exit out of this mode. In addition, power to OCMC RAM is maintained to preserve information internally
during DeepSleep0.
Activity on wakeup peripherals via wakeup events enables the master crystal oscillator using the oscillator
control circuit. The wakeup events also interrupt Cortex M3 which controls proper enabling of power
domains and clocks in the PRCM. See Section 8.1.4.5, Wakeup Sources/Events, for details on wakeup
sources during DeepSleep0 and other low power modes mentioned.
8.1.4.3.5 RTC-Only
RTC-only mode is an ultra-low power mode which allows the user to maintain power and clocks to the
real-time clock (RTC) domain while the rest of the device is powered down. All context and memories will
be lost, and the only portion of the chip that will be maintained is the RTC. Only the RTC power supply
must be ON. All the remaining supplies must be OFF. The RTC battery backup domain consists of the
RTC subsystem (RTCSS), a dedicated, on-chip 32.768 Hz crystal oscillator and I/Os associated with the
RTCSS: pmic_power_en and ext_wakeup.
Figure 8-5 gives a high level view of system which implements the RTC-only mode.
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Internal FSM/control
SoC-Power-on-reset
Main supply
SoC-Power-on-supplies
Wakeup
AM335x
Enable/NSleep
Pushbutton
ext_wakeup0 PMIC
RTC/
Backup
battery pmic_pwr_enable
domain
RTC-Power-on-reset
Backup supply
RTC Power supply
Wakeup from RTC-only mode can only be achieved using the ext_wakeup0 signal or RTC Alarm
(ALARM). Once a wakeup is triggered using either of these sources, the device drives pmic_pwr_enable
to initiate a power-up sequence by the PMIC. The device must go through a full cold boot upon wakeup
from RTC-only mode.
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Table 8-14. USB Wakeup Use Cases Supported in System Sleep States
No. USB Wakeup System Sleep USB Controller USB Mode Supported USB Wakeup
Use Case State State Event
1 USB Connect DS0 POWER OFF Host No N/A
2 DS0 POWER OFF Device Yes VBUS2GPIO
3 DS1/ Standby Clock Gated Host Yes PHY WKUP
4 DS1/ Standby Clock Gated Device Yes VBUS2GPIO
5 USB Suspend / DS0 POWER OFF Host No N/A
Resume
6 DS0 POWER OFF Device No N/A
7 DS1/ Standby Clock Gated Host Yes PHY WKUP
8 DS1/ Standby Clock Gated Device Yes PHY WKUP
9 USB Disconnect DS0 POWER OFF Host No N/A
10 DS0 POWER OFF Device No N/A
11 DS1/ Standby Clock Gated Host Yes PHY WKUP
12 DS1/ Standby Clock Gated Device Yes VBUS2GPIO
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Figure 8-6. System Level View of Power Management of Cortex A8 MPU and Cortex M3
PD_PER
PD_GFX
IP/Peripherals
Power
Bus connect/
disconnect
PD_MPU
(Cortex-A8)
Power
Interconnect
Idle
WKUP
MBX
Power
Bus
Idle
INTR2
MSG3 INTR3
MSG1
TXEV RXEV
PRCM
INTR1
16KB unified RAM
Cortex-
M3
8KB DRAM
Control
MSG3
Cortex-M3 subsystem
Interrupt
Alternate Interrupt/Event
Legend: s/w message
Data flow
The Cortex-M3 handles all of the low-level power management control of the AM335x. A firmware binary
is provided by Texas Instruments that includes all of the necessary functions to achieve low power modes.
Inter-Processor Communication (IPC) registers (ipc_msg_regx, located in the Control Module Registers)
are available to communicate with the Cortex-M3 so the user can provide certain configuration parameters
based on the level of low power that is required. Figure 8-7 provides a mapping of these registers.
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IPC_MSG_REG0 Reserved
IPC_MSG_REG1 contains the CMD_STAT and CMD_ID parameters as described in Table 8-15 and
Table 8-16.
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A set of modular, re-usable FSM blocks to be assembled into the full clock and power management
mechanism. A register set and associated programming model. Functional sub-block definitions for clock
management, power management, system clock source generation, and master clock generation.
The device supports an enhanced power management scheme based on four functional power domains:
Generic Domains
• WAKEUP
• MPU
• PER
• RTC
The PRCM provides the following functional features:
• Software configurable for direct, automatic, or a combination thereof, functional power domain state
transition control
• Device power-up sequence control
• Device sleep / wake-up sequence control
• Centralized reset generation and management
• Centralized clock generation and management
The PRCM modules implement these general functional interfaces:
• OCP configuration ports
• Direct interface to device boundary
• Power switch control signals
• Device control signals
• Clocks control signals
• Resets signals
• A set of power management protocol signals for each module to control and monitor standby, idle and
wake-up modes (CM and PRM)
• Emulation signals
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8.1.6.1 Terminology
The PRCM produces 2 types of clock:
Interface clocks: these clocks primarily provide clocking for the system interconnect modules and the
portions of device's functional modules which interface to the system interconnect modules. In most
cases, the interface clock supplies the functional module's system interconnect interface and registers. For
some modules, interface clock is also used as functional clock. In this document, interface clocks are
represented by blue lines.
Functional clock: this clock supplies the functional part of a module or a sub-system. In some cases, a
module or a subsystem may require several functional clocks: 1 or several main functional clock(s), 1 or
several optional clock(s). A module needs its main clock(s) to be operational. Optional clocks are used for
specific features and can be shutdown without stopping the module
The device has two reference clocks which are generated by on-chip oscillators or externally. These are
for the main clock tree and RTC block, respectively.
In the case of an external oscillator, a clock can directly be connected to XTALIN pin and the oscillator will
be put in bypass mode. The 32-Khz crystal oscillator is controlled and configurable by RTC IP. This device
also contains an on-chip RC oscillator. This oscillator is not configurable and is always on.
The main oscillator on the device (see Chapter 26, Initialization, for possible frequencies) produces the
master high frequency clock CLK_M_OSC.
8.1.6.3 ADPLLS
The ADPLLS is a high resolution frequency synthesizer PLL with built in level shifters which allows the
generation of PLL locked frequencies up to 2 GHz. ADPLLS has a predivide feature which allows user to
divide, for instance, a 24- or 26-MHz reference clock to 1-MHz and then multiply up to 2-GHz maximum.
All PLLs will come-up in bypass mode at reset. SW needs to program all the PLL settings appropriately
and then wait for PLL to be locked. For more details, see the configuration procedure for each PLL.
The following PLLs are:
• MPU PLL
• Core PLL
• Display PLL
• DDR PLL
ULOWCLKEN
1/(N2+1)
(4 bits)
CLKOUTX2
1/(N+1) CLKINPULOW
7 bits
BYPASS_INT
REFCLK
1/M2 ½ CLKOUT
PFD Multiplier DAC (5 bits) (1 bit)
FBCLK CLKDCOLDO
½
1/M.f
(1 bit)
1/M3 CLKOUTHIF
(5 bits)
CLKINPHIF
SSC sigmadelta
CLKINPHIFSEL
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Table 8-18. Output Clocks Before Lock and During Relock Modes
Pin Name Frequency Comments
CLKINP / (N2+1) ULOWCLKEN='0'
CLKOUT
CLKINPULOW ULOWCLKEN='1'
CLKINP / (N2+1) ULOWCLKEN='0'
CLKOUTX2
CLKINPULOW ULOWCLKEN='1'
CLKDCOLDO Low
CLKINPHIF/M3 ULOWCLKEN='1'
CLKOUTHIF
Low ULOWCLKEN='0'
Note: Since M3 divider is running on the internal LDO domain, in the case when CLKINPHIFSEL=’1’,
CLKOUTHIF could be active only when internal LDO is ON. Hence, whenever LDOPWDN goes low to
high to powerdown LDO (happens when TINITZ activated / when entering slow relock bypass mode),
output CLKOUTHIF will glitch and stop. To avoid this glitch, it is recommended to gate CLKOUTHIF using
control CLKOUTHIFEN before asserting TINITZ / entering any slow relock bypass mode Frequency
Range (MHz)
See the device-specific data manual for details on operating performance points (OPPs) supported by
your device.
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1/(N+1)
8 bits
SELFREQDCO
CLKOUTLDO
REFCLK
HS1: 2–1 GHz
HS1 1/M2
PFD Multiplier DAC
HS2 7 bits
ULOWCLKEN
FBCLK
SDCLK
Sigma 1/(SD) 1/(N2 + 1) CLKINPULOW
delta 8 bits 4 bits
CLKINP CLKDCOLDO
1/M.f
8 bits
SSC
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All clock outputs of the DPLL can be gated. The Control module provides the DPLL with a clock gating
control signal to enable or disable the clock, and the DPLL provides the PRCM module with a clock
activity status signal to let the PRCM module hardware know when the clock is effectively running or
effectively gated. Output clock gating control for various clockouts:
CLKOUTEN/CLKOUTLDOEN/CLKDCOLDOEN.
Table 8-20. Output Clocks Before Lock and During Relock Modes
Pin Name Frequency Comments
CLKINP/(N2+1) ULOWCLKEN=’0’
CLKOUT
CLKINPLOW ULOWCLKEN=’1’
CLKDCOLDO LOW
CLKOUTLDO LOW
NOTE: Spread spectrum clock is only supported for the DISP/LCD and MPU PLLs on this device.
Spread spectrum clocking is not supported for DDR, PER, and CORE PLLs. When enabling
SSC on MPU PLL, ensure the maximum MPU frequency remains below the maximum rated
frequency for the chosen OPP (see the device-specific Data Manual for more details).
The module supports spread spectrum clocking (SSC) on its output clocks. SSC is used to spread the
spectral peaking of the clock to reduce any electromagnetic interference (EMI) that may be caused due to
the clock’s fundamental or any of its harmonics. When SSC is enabled the clock’s spectrum is spread by
the amount of frequency spread, and the attenuation is given by the ratio of the frequency spread (Δf) and
the modulation frequency (fm), i.e., [{10*log10(Df/fm)}-10] dB.
8.1.6.6.1 Definition
The aim of SSC is to add a variation in the frequency of an original clock, which spreads the generated
interferences over a larger band of frequency.
In theory, SSC means that the clock signal is varied around the desired frequency. For example, for a 1-
GHz clock, the frequency may be 999.5 MHz at one moment and 1.0005 GHz at another. When SSC is
enabled the clock spectrum is spread by the amount of frequency spread. Doing this constantly causes
the power of the tone to be spread out more over a broader band of tight frequencies (centered at the
desired tone). To realize this constant variation on the original signal, a modulation with an additional
signal (called spreading waveform) is realized.
Creating an SSC by spreading the initial clock frequency is done by defining the following parameters:
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• The spreading frequency (deviation), which is the ratio of the range of spreading frequency over the
original clock frequency
• The modulation rate (fm), which is used to determine the clock-frequency spreading-cycling rate and is
the time during which the generated clock frequency varies through Δf and returns to the original
frequency
• The modulation waveform, which describes the variation curve in terms of time
The spectral power reduction in the DPLL clocks is dependent on the modulation index (K), which is a
ratio of spreading frequency calculated from the frequency deviation (Δf) and the modulation rate (fm) .
Figure 8-10 shows not only the power reduction of the main peak, but also the flatter aspect of the
modulated signal. The minimum level of the second signal is higher than the minimum level of the first
signal. This effect is normal and is due to the noise added for the modulation.
NOTE: The spreading technique scatters the energy of the peaks on the other frequencies, which
reduces the power of the peaks but increases the global noise of the signal.
Figure 8-11 shows the effect of triangular spreading on a clock signal in the time domain.
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dB
Reduction
Freq/Hz
The electromagnetic interference reduction can be estimated with the following equation:
Peak_power_reduction = 10 * log ((Deviation * fc) / fm
With:
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• Peak_power_reduction in dB
• Deviation in % of the initial clock frequency (fc), equals Δf / fc
• fc is the original clock frequency, in MHz
• fm is the spreading frequency, in MHz
According to equation (1), it is also possible to compute the deviation, and then Δf, for a required peak
power reduction:
Deviation = (fm / fc) * 10(Peak_power_reduction / 10)
Example:
For fc=400 MHz, deviation =1% peak from fc(Δf = 4MHz) and fm=400kHz; the estimated peak power
reduction is 10dB.
NOTE: Although the same value of ModFreqDivider can be obtained by different combinations of
mantissa and exponent values, it is recommended to get the target ModFreqDivider by
programming maximum mantissa and a minimum exponent.
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To define the Frequency spread (Δf), ΔM must be controlled as explained previously. To define ΔM, the
step size of M for each Fref during the triangular pattern must be programmed; that is,
ΔM = (2^ModFreqDividerExponent) * ModFreqDividerMantissa * DeltaMStep IF
ModFreqDividerExponent ≤ 3ΔM = 8 * ModFreqDividerMantissa * DeltaMStep IF
ModFreqDividerExponent > 3
DeltaMStep is split into integer part and fractional part. Integer part is controlled by 2-bit signal
DeltaMStepInteger through the CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_INTEGER bit field.
Fractional part is controlled by 18-bit signal DeltaMStepFraction through the
CM_SSC_DELTAMSTEP_DPLL_xxx.DELTAMSTEP_FRACTION bit field.
The frequency spread achieved has an overshoot of 20 percent or an inaccuracy of +20 percent. If the
CM_CLKMODE_DPLL.DPLL_SSC_DOWNSPREADis set to 1, the frequency spread on lower side is
twice the programmed value. The frequency spread on higher side is 0 (except for the overshoot as
described previously).
There is restriction of range of M values. The restriction is M-ΔM should be ≥ 20. Also, M+ΔM should be ≤
2045. In case the downspread feature is enabled, M-2*ΔM should be ≥ 20 and M ≤ 2045.
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NOTE: It is necessary to configure the spreading on a clock carefully to avoid adding noise on
frequencies that are used by another module. For example, adding spreading on a clock to
reduce noise on GSM frequencies can "move" the generated noise to the frequency of the
memory controller and degrade its performance.
The state of the modulation feature can be monitored with the DPLL_SSC_ACK bit of the
corresponding register.
HSDIVIDER To DDR,
CORE_CLKOUTM6
M6 Display, MPU
A PLLs
Core PLL
(ADPLLS) PRCM B
PER_CLKOUTM2
1 /1, /2
(192 MHz) SGX CORECLK
0 (0) (1)
CLKINPULOW L3S_CLK
ULOWCLKEN L4_PER_CLK
/2 L4_WKUP_CLK
CLKDCOLDO CLKINPHIFLDO
L3F_CLK
CORE_CLKOUTM4 L4F_CLK
(CLK_M_OSC)
M4
(200 MHz) C PRU-ICSS_IEP_CLK,
CLKOUT 0
Master
Debugss_clka
Osc
E
ALT_CLKs are to be used for internal test purpose and should not be used in functional mode.
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Table 8-22 gives the typical PLL and clock frequencies. The HSDIVIDER is used to generate three divided
clocks M4, M5 & M6. M4 & M5 are nominally 200 & 250 MHz, respectively.
The ADPLLS module supports two different bypass modes via their internal MNBypass mode and their
external Low Power Idle bypass mode. The PLLs are in the MNBypass mode after power-on reset and
can be configured by software to enter Low Power Idle bypass mode for power-down.
When the Core PLL is configured in bypass mode, the HSDIVIDER enters bypass mode and the
CLKINBYPASS input is driven on the M4, M5, and M6 outputs. CLKINBYPASS defaults to the master
oscillator input (typically 24 MHz).
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Master
Osc
(CLK_M_OSC)
Per PLL
(ADPLLLJ)
0
USB_PHY_CLK (960 MHz)
ALT_CLK1 1 CLKINP CLKDCOLDO To USB PHY
ALT_CLK2 2
PER_CLKOUTM2 PRCM
TEST.CDR (via P1500) (192 MHz)
CLKOUT PRU_ICSS_UART_CLK
Reset default = 0
(96 MHz)
/2 MMC_CLK
(32,768 Hz)
CLK_32KHZ
To DDR, Disp, MPU PLLs bypass
clocking PRCM SGX clock mux
*Reset default zero
ALT_CLKs are to be used for internal test purpose and should not be used in functional mode.
The PLL is locked at 960 MHz. The PLL output is divided by the M2 divider to generate a 192-MHz
CLKOUT. This clock is gated in the PRCM to form the PRU-ICSS UART clock. There is a /2 divider to
create 96 MHz for MMC_CLK. The clock is also divided within the PRCM by a fixed /4 divider to create a
48-MHz clock for the SPI, UART and I2C modules. The 48-MHz clock is further divided by a fixed /2
divider and a fixed /732.4219 divider to create an accurate 32.768-KHz clock for Timer and debounce use.
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The ADPLLLJ module supports two different bypass modes via their internal MNBypass mode and their
external Low Power Idle bypass mode. The PLLs are in the MNBypass mode after power-on reset and
can be configured by software to enter Low Power Idle bypass mode for power-down.
The PER PLL can use the Low Power Idle bypass mode. When the internal bypass mode is selected, the
CLKOUT output is driven by CLKINP/(N2+1) where N2 is driven by the PRCM. CLKINP defaults to the
master oscillator input (typically 24 MHz)
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PRCM
Control
Master
Osc
(CLK_M_OSC) MPU PLL
(ADPLLS)
0
ALT_CLK1 1 CLKINP
ALT_CLK2 2
CLKOUT A8 clock
CORE_CLKOUTM6 0
CLKINPULOW
PER_CLKOUTM2 1
CONTROL.PLL_CLKINPULOW_CTRL.MPU_PLL_CLKINPULOW_SEL
(Reset default = 0)
ULOWCLKEN
PRCM.CM_CLKSEL_DPLL_MPU.DPLL_BYP_CLKSEL 0: CLKINP
(Reset default = 0) 1: CLKINPULOW
ULOWPRIORITY
MPU subsystem
For example:
For a frequency for MPU, say 600 MHz, the ADPLLS is configured (PLL locked at 1200 MHz and M2
Divider =1) so as to expect CLKOUT = 600 MHz .
The ULOWCLKEN input from a programmable PRCM register selects whether CLKINP or CLKINPULOW
is the bypass clock source. This is a glitch free switch. When CLKINP is selected it is sourced through the
ADPLLS 1/(N2+1) divider. The PRCM register defaults to 0 on power-up to select the CLKINP source.
The CLKINPULOW input may be sourced from the CORE_CLKOUTM6 from the Core PLL, or
PER_CLKOUTM2 from the Per PLL. These PLL output clocks can be used as alternate clock sources in
low power active use cases for the MPU Subsystem clock when the PLL is in bypass mode.
CONTROL.PLL_CLKINPULOW_CTRL.DISP_
PLL_CLKINPULOW_SEL (Reset default = 0)
ULOWCLKEN
PRCM.CM_CLKSEL_DPLL_DISP. 0: CLKINP
DPLL_BYP_CLKSEL (Reset default = 0) 1: CLKINPULOW
ULOWPRIORITY
CORE_CLKOUTM5
PER_CLKOUTM2
For example: say frequency for pixel clock 100 MHz, the ADPLLS is configured (PLL locked at 200 MHz
and M2 Divider =1) so as to expect CLKOUT = 100 MHz.
The ULOWCLKEN input from a programmable PRCM register selects whether CLKINP or CLKINPULOW
is the bypass clock source. This is a glitch free switch. When CLKINP is selected it is sourced through the
ADPLLS 1/(N2+1) divider. The PRCM register defaults to 0 on power-up to select the CLKINP source.
The CLKINPULOW input is sourced from the CORE_CLKOUTM6 from the Core PLL or PER_CLKOUTM2
from the Per PLL. This PLL output clock can be used as an alternate clock source in low power active use
cases for the pixel clock when the Display PLL is in bypass mode.
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Note: M2 divider can also be changed on-the-fly (ie., there is no need to put the PLL in bypass and back
to lock mode). After changing CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_DISP.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to
see if the change was acknowledged by the PLL.
CONTROL.PLL_CLKINPULOW_CTRL.DDR_
PLL_CLKINPULOW_SEL (Reset default = 0)
ULOWCLKEN
PRCM.CM_CLKSEL_DPLL_DDR. 0: CLKINP
DPLL_BYP_CLKSEL (Reset default = 0) 1: CLKINPULOW
ULOWPRIORITY
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Note: M2 divider can also be changed on-the-fly (i.e., there is no need to put the PLL in bypass and back
to lock mode). After changing CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIV, check
CM_DIV_M2_DPLL_DDR.DPLL_CLKOUT_DIVCHACK for a toggle (a change from 0 to 1 or 1 to 0) to see
if the change was acknowledged by the PLL.
Master PRCM
Osc CLKOUT1
(CLK_M_OSC)
4
PIXEL_CLK
PRCM.CM_CLKOUT_CTRL.CLKOUT2SOURCE PRCM.CM_CLKOUT_CTRL.CLKOUT2DIV
(Default = 0) (Default = 0)
Device
PRCM
On-Chip ~32 kHz
32K RC Osc 0
(CLK_RC32K)
To WDT1
CLK_32KHZ 32 kHz
1
From PRCM PRCM.CLKSEL_WDT1_
CLK.CLKSEL
To DMTIMER0
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Figure 8-20. Watchdog and Secure Timer Clock Selection (For Secure Devices only)
Device
PRCM
On-Chip ~32,768 Hz
32K RC Osc 0
(CLK_RC32K)
To WDT0
(Secure)
CLK_32KHZ 32,768 Hz
1
From PRCM CONTROL.SEC_CLK_
CTRL.SECWDCLKSEL
0 (Default: 0)
To WDT1
1
PRCM.CLKSEL_WDT1_
CLK.CLKSEL
(Default: 0)
0
1
To DMTIMER0
Master
Xtal Osc 2
(CLK_M_OSC)
TCLKIN 3 CONTROL.SEC_CLK_CTRL.
SECTIMERCLKSEL
(Default: 0)
All mux selections are in PRCM unless explicitly shown otherwise in the diagrams.
The clock selections for the other device Timer modules are shown in Figure 8-21. CLK_32KHZ, the
master oscillator, and the external pin (TCLKIN) are optional clocks available for timers which may be
selected based on end use application.
DMTIMER1 is implemented using the DMTimer_1ms module which is capable of generating an accurate
1ms tick using a 32.768 KHz clock. During low power modes, the Master Oscillator is disabled.
CLK_32KHZ also would not be available in this scenario since it is sourced from the Master Osc based
PER PLL. Hence, in low power modes DMTIMER1 in the WKUP domain can use the 32K RC oscillator for
generating the OS (operating system) 1ms tick generation and timer based wakeup. Since most
applications expect an accurate 1ms OS tick which the inaccurate 32K RC (16-60 KHz) oscillator cannot
provide, a separate 32768 Hz oscillator (32K Osc) is provided as another option.
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Device
PRCM
32K
32,768 Hz 32,768 Hz
Osc 4
Xtal (CLK_32K_RTC)
On-Chip
~32,768 Hz
32K RC Osc 3
(CLK_RC32K)
CLK_32KHZ 32,768 Hz
1 To
From PLL DMTIMER1_1ms
Master
Osc 0
Xtal
(CLK_M_OSC)
TCLKIN 2
PRCMCLKSEL_TIME
R1MS_CLK.CLKSEL
(Default: 0)
2
6
1 x6 To
6 6 DMTIMER{2-7}
0 PRCMCLKSEL_TIME
6 Rn_CLK.CLKSEL
(Default: 1)
All mux selections are in PRCM unless explicitly shown otherwise in the diagrams.
The RTC, Debounce and VTP clock options are shown in Figure 8-22. In low power modes, the debounce
for GPIO0 in WKUP domain can use the accurate 32768 Hz crystal oscillator or the inaccurate (16 KHz to
60 KHz) 32K RC oscillator when the Master Osc is powered down.
The 32K Osc requires an external 32768-Hz crystal.
All mux selections are in PRCM unless explicitly shown otherwise in the diagrams.
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Device
RTC.OSC_REG.SEL_32KCLK_SRC
32K 32,768 Hz
32,768 Hz 1 (Reset default = 0)
Osc
Xtal (CLK_32K_RTC)
RTC clock
PRCM
CLK_32KHZ 32,768 Hz
0
From PLL
RTC IP
1
2 To GPIO0 debounce
On-Chip
~32,768 Hz PRCM.CLKSEL_GPIO0_DBCLK.
32K RC Osc 0
(CLK_RC32K) CLKSEL (Reset default = 0)
All mux selections are in PRCM unless explicitly shown otherwise in the diagrams.
8.1.7.1 Overview
The PRCM manages the resets to all power domains inside device and generation of a single reset output
signal through device pin, WARMRSTn, for external use. The PRCM has no knowledge of or control over
resets generated locally within a module, e.g., via the OCP configuration register bit
IPName_SYSCONFIG.SoftReset.
All PRM reset outputs are asynchronously asserted. These outputs are active-low except for the PLL
resets. Deassertion is synchronous to the clock which runs a counter used to stall, or delay, reset de-
assertion upon source deactivation. This clock will be CLK_M_OSC used by all the reset managers. All
modules receiving a PRCM generated reset are expected to treat the reset as asynchronous and
implement local re-synchronization upon de-activation as needed.
One or more Reset Managers are required per power domain. Independent management of multiple reset
domains is required to meet the reset sequencing requirements of all modules in the power domain
Warm reset types are not necessarily applied globally within each receiving entity. A module may use a
warm reset to reset a subset of its logic. This is often done to speed-up reset recovery time, i.e., the time
to transition to a safe operating state, compared to the time required upon receipt of a cold reset. Warm
reset events include: software initiated per power-domain, watch-dog time-out, security violation, externally
triggered, and emulation initiated.
Reset sources, warm or cold types, intended for device-wide effect are classified as global sources. Reset
sources intended for regional effect are classified as local sources.
Each Reset Manager provides two reset outputs. One is a cold reset generated from the group of global
and local cold reset sources it receives. The other is a warm+cold reset generated from the combined
groups of, global and local, cold and warm reset sources it receives.
The Reset Manager asserts one, or both, of its reset outputs asynchronously upon reset source assertion.
Reset deassertion is extended beyond the time the source gets de-asserted. The reset manager will then
extend the active period of the reset outputs beyond the release of the reset source, according to the
PRCM’s internal constraints and device’s constraints. Some reset durations can be software-configured.
Most (but not all) reset sources are logged by PRCM’s reset status registers. The same reset output can
generally be activated by several reset sources and the same reset source can generally activate several
reset outputs. All the reset signals output of the PRCM are active low. Several conventions are used in
this document for signal and port names. They include:
• "_RST" in a signal or port name is used to denote reset signal.
• "_PWRON_RST" in a signal or port name is used to denote a cold reset source
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CLK_M_OSC
PORz
(1) nRESETIN_OUT is not defined (can either be driven low or pulled up high) until all supplies are fully ramped
up. For nRESETIN_OUT to maintain a valid low state until the supples are ramped, an external buffer should
be implemented, as shown in Figure 8-24.
(2) For information on tsx, see AM335x Sitara Processors (literature number SPRS717).
VIN of PMIC
Device
Open-drain
buffer
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Device VDDSHV6
1.8 or 3.3 V
PRCM
nRESETOUT
nRESET_IN_OUT Pullup RESET to
PRM peripherals on
nRESETIN board
Note: It is recommended to implement warm reset as an input only (for example, push button) or an output only (to
reset external peripherals), not both.
The device will have one pin nRESETIN_OUT which reflects chip reset status. This output will always
assert asynchronously when any chip watchdog timer reset occurs if any of the following reset events
occurs:
• POR (only internal stretched portion of reset event after bootstrap is latched)
• External Warm reset (nRESETIN_OUT pin, only internal stretched portion of reset event after
bootstrap is latched)
• Emulation reset (Cold or warm from ICEPICK)
• Reset requestor
• SW cold/warm reset
This output will remain asserted as long as PRCM keeps reset to the host processor asserted.
Note: TRST does not cause RSTOUTn assertion
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CLK_M_OSC
PORz
EMIF FIFO
drains and
DRAM is put
External warm reset assertion in self-refresh
detected on the nRESETIN_OUT pin
Tri-stated with
weak pullup
Warm reset out driven
on nRESETIN_OUT pin
Figure 8-27 shows the nRESETIN_OUT waveform when any one of the warm reset sources captured
except using nRESETIN_OUT itself as warm reset source.
CLK_M_OSC
PORz
EMIF FIFO
drains and
DRAM is put
Internal warm reset assertion in self-refresh
Tri-stated with
Tri-stated with
weak pullup
weak pullup
Warm reset out driven
on nRESETIN_OUT pin
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Note: The Bandgap macros for the LDOs will be reset on PORz only.
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(1)
The ROM software does not utilize this feature of DRAM content preservation. Hence, the AM335x re-boots like a cold boot for warm reset as well.
(2)
CORE PLL is an exception when EMAC switch reset isolation is enabled
(3)
Watchdog0 (secure watchdog) reset is not block-able by emulation
(4)
Only true if GMAC switch reset isolation is enabled in control registers, otherwise will be reset.
(5)
There are exception details in control module & PRCM registers which are captured in the register specifications in Chapter 8 and Chapter 9. This includes some pinmux registers which
are warm reset in-sensitive.
(6)
Exception details for debugss logic are captured in debugss specification.
(7)
Some special IOs/Muxing registers like test, emulation, GEMAC Switch (When under reset isolation mode), etc related will not be affected under warm reset conditions.
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8.1.9 IO State
All IOs except for JTAG i/f and Reset output (and any special cases mentioned in pinlist) should have their
output drivers tri-state and internal pulls enabled during assertion of all reset sources. JTAG i/f IO is
affected only by TRSTz.
Note: The PRUs and Cortex M3 processor are held under reset after global warm reset by assertion of
software source of reset. Other domains are held under reset after global warm reset until the MPU
software enables their respective interface clock.
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1250Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1251
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1252 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1253
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1254 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_
GPIO_3_GDBC GPIO_2_GDBC GPIO_1_GDBC LCDC_GCLK TIMER4_GCLK
LK LK LK
R-0h R-0h R-0h R-0h R-1h R-1h R-0h R-0h
15 14 13 12 11 10 9 8
CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_
TIMER3_GCLK TIMER2_GCLK TIMER7_GCLK CAN_CLK UART_GFCLK L4LS_GCLK
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1255
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1256 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved Reserved Reserved
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved Reserved CLKACTIVITY_ Reserved CLKTRCTRL
L3S_GCLK
R-0h R-0h R-1h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1257
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CLKACTIVITY_ CLKACTIVITY_ Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKTRCTRL
MCASP_GCLK CPTS_RFT_G L3_GCLK MMC_FCLK EMIF_GCLK
CLK
R-0h R-0h R-0h R-1h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1258 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1259
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1260 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1261
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1262 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1263
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1264 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1265
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1266 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1267
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23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1268 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1269
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1270 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1271
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1272 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1273
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1274 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1275
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1276 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1277
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1278 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1279
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1280 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1281
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1282 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1283
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23 22 21 20 19 18 17 16
Reserved OPTFCLKEN_ IDLEST
GPIO_1_GDBC
LK
R-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1284 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved OPTFCLKEN_ IDLEST
GPIO_2_GDBC
LK
R-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1285
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23 22 21 20 19 18 17 16
Reserved OPTFCLKEN_ IDLEST
GPIO_3_GDBC
LK
R-0h R/W-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1286 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1287
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23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1288 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1289
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1290 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1291
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1292 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1293
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Power, Reset, and Clock Management www.ti.com
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1294 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1295
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Power, Reset, and Clock Management www.ti.com
23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1296 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1297
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Power, Reset, and Clock Management www.ti.com
23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1298 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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www.ti.com Power, Reset, and Clock Management
23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1299
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23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1300 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1301
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1302 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1303
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1304 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
CPSW_5MHZ_ CPSW_50MHZ CPSW_250MH L4HS_GCLK
GCLK _GCLK Z_GCLK
R-0h R-1h R-1h R-1h R-1h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1305
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1306 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
OCPWP_L4_G OCPWP_L3_G
CLK CLK
R-0h R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1307
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1308 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
PRU_ICSS_UA PRU_ICSS_IE PRU_ICSS_OC
RT_GCLK P_GCLK P_GCLK
R-0h R-0h R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1309
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ Reserved CLKTRCTRL
CPSW_125MH
z_GCLK
R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1310 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKACTIVITY_ Reserved CLKTRCTRL
LCDC_L4_OCP LCDC_L3_OCP
_GCLK _GCLK
R-0h R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1311
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1312 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ Reserved CLKTRCTRL
CLK_24MHZ_G
CLK
R-0h R-0h R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1313
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1314Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1315
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1316 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1317
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1318 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1319
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1320 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1321
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1322 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1323
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1324 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1325
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1326 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1327
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1328 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1329
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1330 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1331
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1332 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1333
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1334 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1335
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1336 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1337
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1338 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1339
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1340 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1341
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1342 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1343
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1344 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1345
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1346 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1347
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1348 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1349
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1350 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1351
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1352 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1353
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1354 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1355
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1356 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1357
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1358 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1359
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1360 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1361
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1362 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1363
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1364 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1365
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1366 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1367
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1368 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1369
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1370 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1371
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1372 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1373
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1374 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1375
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1376 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1377
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1378 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1379
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1380 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MII_CLK_SEL Reserved
R-0h R/W-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1381
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1382 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1383
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved CLKSEL
R-0h R-0h R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1384 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1385
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL_GFX_ CLKDIV_SEL_
FCLK GFX_FCLK
R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1386 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1387
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1388 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1389
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKSEL
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1390 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved CLKACTIVITY_ CLKTRCTRL
MPU_CLK
R-0h R-1h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1391
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1392Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1393
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
CLKOUT2EN Reserved CLKOUT2DIV CLKOUT2SOURCE
R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1394 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1395
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23 22 21 20 19 18 17 16
Reserved Reserved IDLEST
R-0h R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1396 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved CLKACTIVITY_ CLKACTIVITY_
RTC_32KCLK L4_RTC_GCLK
R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1397
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1398 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_ CLKACTIVITY_
GFX_FCLK GFX_L3_GCLK
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1399
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23 22 21 20 19 18 17 16
Reserved STBYST IDLEST
R-0h R-1h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1400 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_
L4LS_GFX_GC
LK
R-0h R-1h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1401
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1402 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1403
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1404 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved CLKACTIVITY_ CLKACTIVITY_
CUST_EFUSE L4_CEFUSE_G
_SYS_CLK ICLK
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
Reserved CLKTRCTRL
R-0h R/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1405
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23 22 21 20 19 18 17 16
Reserved IDLEST
R-0h R-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved MODULEMODE
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1406 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1407
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Rev
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1408 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_per_recal_ dpll_ddr_recal_ dpll_disp_recal dpll_core_recal dpll_mpu_recal ForceWkup_st Reserved Transition_st
st st _st _st _st
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1409
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_disp_recal dpll_ddr_recal_ dpll_per_recal_ dpll_core_recal dpll_mpu_recal ForceWkup_en Reserved Transition_en
_en en en _en _en
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1410 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_per_recal_ dpll_ddr_recal_ dpll_disp_recal dpll_core_recal dpll_mpu_recal ForceWkup_st Reserved Transition_st
st st _st _st _st
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1411
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
dpll_disp_recal dpll_ddr_recal_ dpll_per_recal_ dpll_core_recal dpll_mpu_recal ForceWkup_en Reserved Transition_en
_en en en _en _en
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1412 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1413
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved Reserved PRU_ICSS_LR Reserved
ST
R-0h R-0h R-0h R/W-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1414 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
pru_icss_mem_ ram_mem_statest InTransition Reserved PER_mem_statest Reserved
statest
R-3h R-3h R-0h R-0h R-3h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LogicStateSt PowerStateSt
R-0h R-1h R-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1415
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1416 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
pru_icss_mem_ pru_icss_mem_ONState LowPowerState LogicRETState Reserved PowerState
RETState Change
R/W-1h R/W-3h R/W-0h R/W-1h R-0h R/W-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1417
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1418 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved Reserved WKUP_M3_LR Reserved
ST
R-0h R-0h R/W-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1419
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LowPowerState LogicRETState Reserved Reserved
Change
R-0h R/W-0h R/W-1h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1420 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved Reserved InTransition Reserved Debugss_mem_statest Reserved
R-0h R-0h R-0h R-0h R-3h R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LogicStateSt Reserved
R-0h R-1h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1421
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
ICECRUSHER EMULATION_ WKUP_M3_LR Reserved
_M3_RST M3_RST ST
R/W-0h R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1422Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1423
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23 22 21 20 19 18 17 16
mpu_l2_RETSt mpu_l1_RETSt MPU_L2_ONState MPU_L1_ONState MPU_RAM_ONState
ate ate
R/W-1h R/W-1h R-3h R-3h R/W-3h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved LowPowerState Reserved LogicRETState PowerState
Change
R-0h R/W-0h R-0h R/W-1h R/W-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1424 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1425
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23 22 21 20 19 18 17 16
Reserved InTransition Reserved
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
Reserved MPU_L2_StateSt
R-0h R-1h
7 6 5 4 3 2 1 0
MPU_L1_StateSt MPU_RAM_StateSt Reserved LogicStateSt PowerStateSt
R-1h R-1h R-0h R-1h R-3h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
1426 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved Reserved
R-0h R-0h
7 6 5 4 3 2 1 0
Reserved ICECRUSHER EMULATION_ Reserved Reserved Reserved Reserved
_MPU_RST MPU_RST
R-0h R/W-0h R/W-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1427
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1428 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1429
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1430 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1431
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1432 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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SPRUH73Q – October 2011 – Revised December 2019 Power, Reset, and Clock Management (PRCM) 1433
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1434 Power, Reset, and Clock Management (PRCM) SPRUH73Q – October 2011 – Revised December 2019
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