NETAJI SUBHAS UNIVERSITY OF

TECHNOLOGY
DELHI

DIGITAL CIRCUITS AND SYSTEMS

PROJECT REPORT

MEALY SEQUENTIAL CIRCUIT

Faculty Name : Bhawna Aggrawal

DEPARTMENT OF INSTRUMENTATION AND CONTROL ENGINEERING

NAME : VIKAS YADAV

Design a Mealy sequential circuit which investigates an input sequence X and which
will produce an output of Z = 1 if the total number of 1’s received iseven (consider
zero 1’s to be an even number of 1’s) and the sequence 00 has occurred at least
once.

Note : The total number of 1’s received includesthose received before and after 00.

Example: X = 1 0 1 0 1 0 0 1 1 0 1

Z=00000001001

Notice that the circuit does not reset to the start state when an output of Z = 1
occurs. However, your circuit should have a start state and should beprovided with a
method of manually resetting the flip-flops to the start state. A minimum solution
requires six states. Design your circuit using NANDgates, NOR gates, and three D flip-
flops. Any solution which is minimal for your state assignment and uses 12 or fewer
gates and inverters isacceptable; the best known solution uses seven. (Assign 000 to
the start state.)
 SOLUTION

In this problem the Mealy circuit is described with 6 states.

• The initial state is S0 which represents that there has been an even number of 1’s
and 00 has not occurred yet.

• The next state is S1 and it can be used to represent an even number of 1’s and that
the last input was 0.

• The next state is S2 and it can be used to represent an odd number of 1’s and that
00 has not occurred yet.

• The next state is S3 and it can be used to represent an even number of 1’s and that
00 has occurred.

• The next state is S4 and it can be used to represent an odd number of 1’s and that
the last input was 0.

• The next state is S5 and it can be used to represent an odd number of 1’s and that
00 has occurred.

Now determine the next states and outputs. For example if the current state is S0
and the next input is 0 then the next state shouldbe S1 since now we still have an
even number of 1’s but the previous input was 0. If the next input is 1 then the next
state is S2 since nowwe have an odd number of 1’s and 00 has not yet occurred. The
output for both cases is 0 since 00 has not occurred yet. Now do thesame analysis
for the rest of the states.

The state table is shown in Table 1:

State Next state Output

X = 0, X = 1 X = 0, X = 1
S0 S1,S2 0, 0

S1 S3,S2 1, 0

S2 S4,S0 0, 0

S3 S3,S5 1, 0

S4 S5,S0 0, 0

S5 S5,S3 0, 1

The verification of state table using the first input sequence is shown in Table 2:

Current state Input Next state Output

S0 0 S1 0

S1 1 S2 0

S2 1 S0 0

S0 0 S1 0

S1 0 S3 1

S3 1 S5 0
S5 0 S5 0

S5 1 S3 1

S3 0 S3 1

S3 0 S3 1

The verification of state table using the second input sequence is shown in Table 3:

Current state Input Next state Output

S0 1 S2 0

S2 0 S4 0

S4 1 S0 0

S0 1 S2 0

S2 1 S0 0

S0 1 S2 0

S2 0 S4 0

S4 0 S5 0
S5 1 S3 1

S3 1 S5 0

S5 1 S3 1

S3 0 S3 1

As for both input sequences the state table was able to correctly produce the correct output
sequence. This means that the state table is correct.

Now a state assignment needs to be chosen one where S0 is 000. Observe that S4 and S5
have the same next state when X is 0 so those should be adjacent. The same is true for S1
and S3. Also states S0 and S1 share the same next state when X is 1 so those two states
should be adjacent. This same is true for S2 and S4. Also states that are next states for the
same state should be adjacent, for example states S5 and S3 should be adjacent since they
are next states for S5.

The state assignment table is shown in Table 4:

0 1

00 S0 S4

01 S5

11 S3

10 S1 S2
Now plug in the state assignment to the state table as shown in Table 5:

State Next state

Output

X = 0, X = 1 X = 0, X = 1

000 010, 110 0, 0

010 111, 110 1, 0

110 100, 000 0, 0

111 111, 101 1, 0

100 101, 000 0, 0

101 101, 111 0, 1

The input is and the output is .

0001 1100

0010 ----

0011 ----

0100 1111

0101 1100

0110 ----

0111 ----

1000 1010

1001 0000

1011 1111

1100 1000

1101 0000

1110 1111
1111 1010

The truth table to get the Karnaugh map for Q1+ :

The logic expression for is:

The truth table to get the Karnaugh map for Q2+ :

The logic expression for Q2+ :

The truth table to get the Karnaugh map for Q3+ :

The truth table to get the Karnaugh map for Z is :

From Figure 5, the logic expression for is :

Now using De ’Morgan’s Law convert the logic expressions determined from the
Karnaugh maps into the ones shown below. These can be implemented with NAND
and/or NOR gates and inverters.
STATE DIAGRAM FOR MEALY MACHINE :

VHDL CODE
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

ENTITY mealy IS

port (

clk : in std_logic;

din : in std_logic;

rst : in std_logic;

dout : out std_logic;

);

END mealy;

ARCHITECTURE behavior OF mealy IS

TYPE Statetype IS (a,b,c,d,e,f);

SIGNAL Currstate, Nextstate: Statetype;

BEGIN

synchronous_process : PROCESS(clk)

BEGIN

if rising_edge(clk) then

if(rst='1') then

present_state<=a;
 else

present_state<=next_state;

end if;

end if;

END PROCESS ;

END;

next_state_and_output_decoder : process(present_state,din)

begin

dout<='0';

case(present_state) is

when a=>

if(din='0') then

next_state<=c;

dout<='0';

else

next_state<=b;

dout<='0';

end if;

when b=>

if(din='0') then

next_state<=d;

dout<='0';
 else

next_state<=a;

dout<='0';

end if;

when c=>

if (din='0') then

next_stage<=e;

dout<='1';

else

next_state<=b;

dout<='0';

end if;

when d=>

if (din='0') then

next_state<=e;

dout<='1';

else

next_state<=f;

dout<='0';

when f=>

if(din='0') then

next_state=f;
 dout<='0';

else

next_state=e;

dout<='1';

end if;

when other=>

next_state<=a;

dout<='0';

end case;

end process;

end behavior;